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| author | Nick Clifton <nickc@redhat.com> | 2014-05-20 09:38:00 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@gcc.gnu.org> | 2014-05-20 09:38:00 +0000 |
| commit | 8f0e7f6f6baab4910f91509466dda26de42035de (patch) | |
| tree | e60217148a710474973b2fa2c8fed3f1a258ac0b /gcc | |
| parent | 8ec7c36a530a4c0944556d885857fcf5a24f3073 (diff) | |
| download | gcc-8f0e7f6f6baab4910f91509466dda26de42035de.zip gcc-8f0e7f6f6baab4910f91509466dda26de42035de.tar.gz gcc-8f0e7f6f6baab4910f91509466dda26de42035de.tar.bz2 | |
msp430.md (zero_extendpsisi2): Use + constraint on operand 0 in order to prevent confusion about the number of...
* config/msp430/msp430.md (zero_extendpsisi2): Use + constraint on
operand 0 in order to prevent confusion about the number of
registers involved.
From-SVN: r210636
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/msp430/msp430.md | 8 |
2 files changed, 13 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 26142ba..3acd963 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2014-05-20 Nick Clifton <nickc@redhat.com> + + * config/msp430/msp430.md (zero_extendpsisi2): Use + constraint on + operand 0 in order to prevent confusion about the number of + registers involved. + 2014-05-20 Richard Biener <rguenther@suse.de> PR tree-optimization/61221 diff --git a/gcc/config/msp430/msp430.md b/gcc/config/msp430/msp430.md index ceff537..ecdc493 100644 --- a/gcc/config/msp430/msp430.md +++ b/gcc/config/msp430/msp430.md @@ -618,9 +618,15 @@ ; when the PSI value is negative.. ; ; Note: using PUSHM.A #1 is two bytes smaller than using PUSHX.A.... +; +; Note: We use a + constraint on operand 0 as otherwise GCC gets confused +; about extending a single PSI mode register into a pair of SImode registers +; with the same starting register. It thinks that the upper register of +; the pair is unused and so it can clobber it. Try compiling 20050826-2.c +; at -O2 to see this. (define_insn "zero_extendpsisi2" - [(set (match_operand:SI 0 "register_operand" "=r") + [(set (match_operand:SI 0 "register_operand" "+r") (zero_extend:SI (match_operand:PSI 1 "register_operand" "r")))] "" "* |