Daily bump.

6 files changed, 426 insertions, 1 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e6e212a..3744064 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,223 @@
+2023-06-07  Roger Sayle  <roger@nextmovesoftware.com>
+
+	* wide-int.cc (wi::bitreverse_large): Use HOST_WIDE_INT_1U to
+	avoid sign extension/undefined behaviour when setting each bit.
+
+2023-06-07  Roger Sayle  <roger@nextmovesoftware.com>
+	    Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/i386-expand.cc (ix86_expand_builtin) <handlecarry>:
+	Use new x86_stc instruction when the carry flag must be set.
+	* config/i386/i386.cc (ix86_cc_mode): Use CCCmode for *x86_cmc.
+	(ix86_rtx_costs): Provide accurate rtx_costs for *x86_cmc.
+	* config/i386/i386.h (TARGET_SLOW_STC): New define.
+	* config/i386/i386.md (UNSPEC_STC): New UNSPEC for stc.
+	(x86_stc): New define_insn.
+	(define_peephole2): Convert x86_stc into alternate implementation
+	on pentium4 without -Os when a QImode register is available.
+	(*x86_cmc): New define_insn.
+	(define_peephole2): Convert *x86_cmc into alternate implementation
+	on pentium4 without -Os when a QImode register is available.
+	(*setccc): New define_insn_and_split for a no-op CCCmode move.
+	(*setcc_qi_negqi_ccc_1_<mode>): New define_insn_and_split to
+	recognize (and eliminate) the carry flag being copied to itself.
+	(*setcc_qi_negqi_ccc_2_<mode>): Likewise.
+	* config/i386/x86-tune.def (X86_TUNE_SLOW_STC): New tuning flag.
+
+2023-06-07  Andrew Pinski  <apinski@marvell.com>
+
+	* match.pd: Fix comment for the
+	`(zero_one ==/!= 0) ? y : z <op> y` patterns.
+
+2023-06-07  Jeff Law  <jlaw@ventanamicro.com>
+	    Jeff Law   <jlaw@ventanamicro.com>
+
+	* config/riscv/bitmanip.md (rotrdi3, rotrsi3, rotlsi3): New expanders.
+	(rotrsi3_sext): Expose generator.
+	(rotlsi3 pattern): Hide generator.
+	* config/riscv/riscv-protos.h (riscv_emit_binary): New function
+	declaration.
+	* config/riscv/riscv.cc (riscv_emit_binary): Removed static
+	* config/riscv/riscv.md (addsi3, subsi3, negsi2): Hide generator.
+	(mulsi3, <optab>si3): Likewise.
+	(addsi3, subsi3, negsi2, mulsi3, <optab>si3): New expanders.
+	(addv<mode>4, subv<mode>4, mulv<mode>4): Use riscv_emit_binary.
+	(<u>mulsidi3): Likewise.
+	(addsi3_extended, subsi3_extended, negsi2_extended): Expose generator.
+	(mulsi3_extended, <optab>si3_extended): Likewise.
+	(splitter for shadd feeding divison): Update RTL pattern to account
+	for changes in how 32 bit ops are expanded for TARGET_64BIT.
+	* loop-iv.cc (get_biv_step_1): Process src of extension when it PLUS.
+
+2023-06-07  Dimitar Dimitrov  <dimitar@dinux.eu>
+
+	PR target/109725
+	* config/riscv/riscv.cc (riscv_print_operand): Calculate
+	memmodel only when it is valid.
+
+2023-06-07  Dimitar Dimitrov  <dimitar@dinux.eu>
+
+	* config/riscv/riscv.cc (riscv_const_insns): Recursively call
+	for constant element of a vector.
+
+2023-06-07  Jakub Jelinek  <jakub@redhat.com>
+
+	* match.pd (zero_one_valued_p): Don't handle integer_zerop specially,
+	instead compare tree_nonzero_bits <= 1U rather than just == 1.
+
+2023-06-07  Alex Coplan  <alex.coplan@arm.com>
+
+	PR target/110132
+	* config/aarch64/aarch64-builtins.cc (aarch64_general_simulate_builtin):
+	New. Use it ...
+	(aarch64_init_ls64_builtins): ... here. Switch to declaring public ACLE
+	names for builtins.
+	(aarch64_general_init_builtins): Ensure we invoke the arm_acle.h
+	setup if in_lto_p, just like we do for SVE.
+	* config/aarch64/arm_acle.h: (__arm_ld64b): Delete.
+	(__arm_st64b): Delete.
+	(__arm_st64bv): Delete.
+	(__arm_st64bv0): Delete.
+
+2023-06-07  Alex Coplan  <alex.coplan@arm.com>
+
+	PR target/110100
+	* config/aarch64/aarch64-builtins.cc (aarch64_expand_builtin_ls64):
+	Use input operand for the destination address.
+	* config/aarch64/aarch64.md (st64b): Fix constraint on address
+	operand.
+
+2023-06-07  Alex Coplan  <alex.coplan@arm.com>
+
+	PR target/110100
+	* config/aarch64/aarch64-builtins.cc (aarch64_init_ls64_builtins_types):
+	Replace eight consecutive spaces with tabs.
+	(aarch64_init_ls64_builtins): Likewise.
+	(aarch64_expand_builtin_ls64): Likewise.
+	* config/aarch64/aarch64.md (ld64b): Likewise.
+	(st64b): Likewise.
+	(st64bv): Likewise
+	(st64bv0): Likewise.
+
+2023-06-07  Vladimir N. Makarov  <vmakarov@redhat.com>
+
+	* ira-costs.cc: (find_costs_and_classes): Constrain classes of pic
+	offset table pseudo to a general reg subset.
+
+2023-06-07  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/aarch64/aarch64-simd.md (aarch64_sqmovun<mode><vczle><vczbe>):
+	Rename to...
+	(*aarch64_sqmovun<mode>_insn<vczle><vczbe>): ... This.  Reimplement
+	with RTL codes.
+	(aarch64_sqmovun<mode> [SD_HSDI]): Reimplement with RTL codes.
+	(aarch64_sqxtun2<mode>_le): Likewise.
+	(aarch64_sqxtun2<mode>_be): Likewise.
+	(aarch64_sqxtun2<mode>): Adjust for the above.
+	(aarch64_sqmovun<mode>): New define_expand.
+	* config/aarch64/iterators.md (UNSPEC_SQXTUN): Delete.
+	(half_mask): New mode attribute.
+	* config/aarch64/predicates.md (aarch64_simd_umax_half_mode):
+	New predicate.
+
+2023-06-07  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/aarch64/aarch64-simd.md (aarch64_addp<mode><vczle><vczbe>):
+	Reimplement as...
+	(aarch64_addp<mode>_insn): ... This...
+	(aarch64_addp<mode><vczle><vczbe>_insn): ... And this.
+	(aarch64_addp<mode>): New define_expand.
+
+2023-06-07  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
+
+	* config/riscv/riscv-protos.h (expand_vec_perm_const): New function.
+	* config/riscv/riscv-v.cc
+	(rvv_builder::can_duplicate_repeating_sequence_p): Support POLY
+	handling.
+	(rvv_builder::single_step_npatterns_p): New function.
+	(rvv_builder::npatterns_all_equal_p): Ditto.
+	(const_vec_all_in_range_p): Support POLY handling.
+	(gen_const_vector_dup): Ditto.
+	(emit_vlmax_gather_insn): Add vrgatherei16.
+	(emit_vlmax_masked_gather_mu_insn): Ditto.
+	(expand_const_vector): Add VLA SLP const vector support.
+	(expand_vec_perm): Support POLY.
+	(struct expand_vec_perm_d): New struct.
+	(shuffle_generic_patterns): New function.
+	(expand_vec_perm_const_1): Ditto.
+	(expand_vec_perm_const): Ditto.
+	* config/riscv/riscv.cc (riscv_vectorize_vec_perm_const): Ditto.
+	(TARGET_VECTORIZE_VEC_PERM_CONST): New targethook.
+
+2023-06-07  Andrew Pinski  <apinski@marvell.com>
+
+	PR middle-end/110117
+	* expr.cc (expand_single_bit_test): Handle
+	const_int from expand_expr.
+
+2023-06-07  Andrew Pinski  <apinski@marvell.com>
+
+	* expr.cc (do_store_flag): Rearrange the
+	TER code so that it overrides the nonzero bits
+	info if we had `a & POW2`.
+
+2023-06-07  Andrew Pinski  <apinski@marvell.com>
+
+	PR tree-optimization/110134
+	* match.pd (-A CMP -B -> B CMP A): Allow EQ/NE for all integer
+	types.
+	(-A CMP CST -> B CMP (-CST)): Likewise.
+
+2023-06-07  Andrew Pinski  <apinski@marvell.com>
+
+	PR tree-optimization/89263
+	PR tree-optimization/99069
+	PR tree-optimization/20083
+	PR tree-optimization/94898
+	* match.pd: Add patterns to optimize `a ? onezero : onezero` with
+	one of the operands are constant.
+
+2023-06-07  Andrew Pinski  <apinski@marvell.com>
+
+	* match.pd (zero_one_valued_p): Match 0 integer constant
+	too.
+
+2023-06-07  Pan Li  <pan2.li@intel.com>
+
+	* config/riscv/riscv-vector-builtins-types.def
+	(vfloat32mf2_t): Take RVV_REQUIRE_ELEN_FP_16 as requirement.
+	(vfloat32m1_t): Ditto.
+	(vfloat32m2_t): Ditto.
+	(vfloat32m4_t): Ditto.
+	(vfloat32m8_t): Ditto.
+	(vint16mf4_t): Ditto.
+	(vint16mf2_t): Ditto.
+	(vint16m1_t): Ditto.
+	(vint16m2_t): Ditto.
+	(vint16m4_t): Ditto.
+	(vint16m8_t): Ditto.
+	(vuint16mf4_t): Ditto.
+	(vuint16mf2_t): Ditto.
+	(vuint16m1_t): Ditto.
+	(vuint16m2_t): Ditto.
+	(vuint16m4_t): Ditto.
+	(vuint16m8_t): Ditto.
+	(vint32mf2_t): Ditto.
+	(vint32m1_t): Ditto.
+	(vint32m2_t): Ditto.
+	(vint32m4_t): Ditto.
+	(vint32m8_t): Ditto.
+	(vuint32mf2_t): Ditto.
+	(vuint32m1_t): Ditto.
+	(vuint32m2_t): Ditto.
+	(vuint32m4_t): Ditto.
+	(vuint32m8_t): Ditto.
+
+2023-06-07  Jason Merrill  <jason@redhat.com>
+
+	PR c++/58487
+	* doc/invoke.texi: Document it.
+
 2023-06-06  Roger Sayle  <roger@nextmovesoftware.com>
 
 	* doc/rtl.texi (bitreverse, copysign): Document new RTX codes.
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 2e61d1d..73ca44c 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230607
+20230608
diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog
index 9e4c877..6ba50eb 100644
--- a/gcc/c-family/ChangeLog
+++ b/gcc/c-family/ChangeLog
@@ -1,3 +1,8 @@
+2023-06-07  Jason Merrill  <jason@redhat.com>
+
+	PR c++/58487
+	* c.opt: Add -Wnrvo.
+
 2023-05-26  Martin Uecker  <uecker@tugraz.at>
 
 	* c-attribs.cc (build_attr_access_from_parms): Split loop to first
diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index d00a2aa..9591649 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,54 @@
+2023-06-07  Jason Merrill  <jason@redhat.com>
+
+	PR c++/58487
+	PR c++/53637
+	* cp-tree.h (INIT_EXPR_NRV_P): New.
+	* semantics.cc (finalize_nrv_r): Check it.
+	* name-lookup.h (decl_in_scope_p): Declare.
+	* name-lookup.cc (decl_in_scope_p): New.
+	* typeck.cc (check_return_expr): Allow non-NRV
+	returns if the NRV is no longer in scope.
+
+2023-06-07  Jason Merrill  <jason@redhat.com>
+
+	PR c++/58487
+	* typeck.cc (want_nrvo_p): New.
+	(check_return_expr): Handle -Wnrvo.
+
+2023-06-07  Jason Merrill  <jason@redhat.com>
+
+	PR c++/51571
+	PR c++/92407
+	* decl.cc (finish_function): Simplify NRV handling.
+	* except.cc (maybe_set_retval_sentinel): Also set if NRV.
+	(maybe_splice_retval_cleanup): Don't add the cleanup region
+	if we don't need it.
+	* semantics.cc (nrv_data): Add simple field.
+	(finalize_nrv): Set it.
+	(finalize_nrv_r): Check it and retval sentinel.
+	* cp-tree.h (finalize_nrv): Adjust declaration.
+	* typeck.cc (check_return_expr): Remove named_labels check.
+
+2023-06-07  Jason Merrill  <jason@redhat.com>
+
+	PR c++/92407
+	* typeck.cc (check_return_expr): Prevent NRV in the presence of
+	named labels.
+
+2023-06-07  Jason Merrill  <jason@redhat.com>
+
+	PR c++/33799
+	* except.cc (maybe_splice_retval_cleanup): Change
+	recognition of function body and try scopes.
+	* semantics.cc (do_poplevel): Call it after poplevel.
+	(at_try_scope): New.
+	* cp-tree.h (maybe_splice_retval_cleanup): Adjust.
+
+2023-06-07  Jason Merrill  <jason@redhat.com>
+
+	* semantics.cc (finalize_nrv_r): [RETURN_EXPR]: Only replace the
+	INIT_EXPR.
+
 2023-06-06  Kwok Cheung Yeung  <kcy@codesourcery.com>
 	    Tobias Burnus  <tobias@codesourcery.com>
 
diff --git a/gcc/m2/ChangeLog b/gcc/m2/ChangeLog
index 72ae734..1d87464 100644
--- a/gcc/m2/ChangeLog
+++ b/gcc/m2/ChangeLog
@@ -1,3 +1,17 @@
+2023-06-07  Jakub Jelinek  <jakub@redhat.com>
+
+	* Make-lang.in: Build $(generated_files) before building
+	all $(GM2_C_OBJS).
+
+2023-06-07  Gaius Mulley  <gaiusmod2@gmail.com>
+
+	PR modula2/110019
+	* gm2-compiler/SymbolKey.mod (SearchAndDo): Reformatted.
+	(ForeachNodeDo): Reformatted.
+	* gm2-compiler/SymbolTable.mod (AddListify): Join list
+	with "," or "and" if more than one word is in the list.
+	* m2.flex: Remove -1 from atoi(yytext) line number.
+
 2023-06-03  Gaius Mulley  <gaiusmod2@gmail.com>
 
 	PR modula2/110003
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index f782b56..3f970b0 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,138 @@
+2023-06-07  Roger Sayle  <roger@nextmovesoftware.com>
+	    Uros Bizjak  <ubizjak@gmail.com>
+
+	* gcc.target/i386/cmc-1.c: New test case.
+	* gcc.target/i386/stc-1.c: Likewise.
+
+2023-06-07  Jason Merrill  <jason@redhat.com>
+
+	PR c++/58487
+	PR c++/53637
+	* g++.dg/opt/nrv26.C: New test.
+	* g++.dg/opt/nrv26a.C: New test.
+	* g++.dg/opt/nrv27.C: New test.
+
+2023-06-07  Jeff Law  <jlaw@ventanamicro.com>
+	    Jeff Law   <jlaw@ventanamicro.com>
+
+	* gcc.target/riscv/shift-and-2.c: New tests.
+	* gcc.target/riscv/shift-shift-2.c: Adjust expected output.
+	* gcc.target/riscv/sign-extend.c: New test.
+	* gcc.target/riscv/zbb-rol-ror-03.c: Adjust expected output.
+
+2023-06-07  Alex Coplan  <alex.coplan@arm.com>
+
+	PR target/110132
+	* lib/target-supports.exp (check_effective_target_aarch64_asm_FUNC_ok):
+	Extend to ls64.
+	* g++.target/aarch64/acle/acle.exp: New.
+	* g++.target/aarch64/acle/ls64.C: New test.
+	* g++.target/aarch64/acle/ls64_lto.C: New test.
+	* gcc.target/aarch64/acle/ls64_lto.c: New test.
+	* gcc.target/aarch64/acle/pr110132.c: New test.
+
+2023-06-07  Alex Coplan  <alex.coplan@arm.com>
+
+	PR target/110100
+	* gcc.target/aarch64/acle/pr110100.c: New test.
+
+2023-06-07  Vladimir N. Makarov  <vmakarov@redhat.com>
+
+	* gcc.target/sparc/pr109541.c: New.
+
+2023-06-07  Jeff Law  <jlaw@ventanamicro.com>
+
+	* gcc.target/hppa/shadd-3.c: Update expected output.
+
+2023-06-07  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
+
+	* gcc.target/riscv/rvv/autovec/scalable-1.c: Adapt testcase for VLA
+	vectorizer.
+	* gcc.target/riscv/rvv/autovec/v-1.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/zve64d-1.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/zve64f-1.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/partial/slp-1.c: New test.
+	* gcc.target/riscv/rvv/autovec/partial/slp-2.c: New test.
+	* gcc.target/riscv/rvv/autovec/partial/slp-3.c: New test.
+	* gcc.target/riscv/rvv/autovec/partial/slp-4.c: New test.
+	* gcc.target/riscv/rvv/autovec/partial/slp-5.c: New test.
+	* gcc.target/riscv/rvv/autovec/partial/slp-6.c: New test.
+	* gcc.target/riscv/rvv/autovec/partial/slp-7.c: New test.
+	* gcc.target/riscv/rvv/autovec/partial/slp_run-1.c: New test.
+	* gcc.target/riscv/rvv/autovec/partial/slp_run-2.c: New test.
+	* gcc.target/riscv/rvv/autovec/partial/slp_run-3.c: New test.
+	* gcc.target/riscv/rvv/autovec/partial/slp_run-4.c: New test.
+	* gcc.target/riscv/rvv/autovec/partial/slp_run-5.c: New test.
+	* gcc.target/riscv/rvv/autovec/partial/slp_run-6.c: New test.
+	* gcc.target/riscv/rvv/autovec/partial/slp_run-7.c: New test.
+
+2023-06-07  Andrew Pinski  <apinski@marvell.com>
+
+	PR middle-end/110117
+	* gcc.dg/pr110117-1.c: New test.
+	* gcc.dg/pr110117-2.c: New test.
+
+2023-06-07  Andrew Pinski  <apinski@marvell.com>
+
+	PR tree-optimization/110134
+	* gcc.dg/tree-ssa/negneq-1.c: New test.
+	* gcc.dg/tree-ssa/negneq-2.c: New test.
+	* gcc.dg/tree-ssa/negneq-3.c: New test.
+	* gcc.dg/tree-ssa/negneq-4.c: New test.
+
+2023-06-07  Andrew Pinski  <apinski@marvell.com>
+
+	* gcc.dg/tree-ssa/phi-opt-2.c: Adjust the testcase.
+	* gcc.dg/tree-ssa/phi-opt-25b.c: Adjust the testcase.
+	* gcc.dg/tree-ssa/ssa-thread-21.c: Disable phiopt.
+	* gcc.dg/tree-ssa/phi-opt-27.c: New test.
+	* gcc.dg/tree-ssa/phi-opt-28.c: New test.
+	* gcc.dg/tree-ssa/phi-opt-29.c: New test.
+	* gcc.dg/tree-ssa/phi-opt-30.c: New test.
+	* gcc.dg/tree-ssa/phi-opt-31.c: New test.
+	* gcc.dg/tree-ssa/phi-opt-32.c: New test.
+
+2023-06-07  Jason Merrill  <jason@redhat.com>
+
+	PR c++/58487
+	* g++.dg/opt/nrv25.C: New test.
+
+2023-06-07  Jason Merrill  <jason@redhat.com>
+
+	PR c++/51571
+	PR c++/92407
+	* g++.dg/opt/nrv23.C: New test.
+
+2023-06-07  Jason Merrill  <jason@redhat.com>
+
+	PR c++/92407
+	* g++.dg/opt/nrv22.C: New test.
+
+2023-06-07  Jason Merrill  <jason@redhat.com>
+
+	PR c++/33799
+	* g++.dg/eh/return1.C: Add label cases.
+
+2023-06-07  Jason Merrill  <jason@redhat.com>
+
+	* g++.dg/contracts/contracts-post7.C: New test.
+
+2023-06-07  Jason Merrill  <jason@redhat.com>
+
+	PR c++/58050
+	* g++.dg/opt/nrv24.C: New test.
+
+2023-06-07  Gaius Mulley  <gaiusmod2@gmail.com>
+
+	PR modula2/110019
+	* gm2/cpp/fail/cpp-fail.exp: New test.
+	* gm2/cpp/fail/foocpp.mod: New test.
+
 2023-06-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 
 	* gcc.target/riscv/rvv/autovec/widen/widen-8.c: New test.