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| author | Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> | 2023-05-22 16:04:37 +0900 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2023-05-23 13:01:46 -0700 |
| commit | 8a20b4bc50bdc8d61610974d60d5851f3fd8b70f (patch) | |
| tree | 20240dfc087d92b108ececb38709773b9cc45f69 /gcc | |
| parent | e33d2dcb463161a110ac345a451132ce8b2b23d9 (diff) | |
| download | gcc-8a20b4bc50bdc8d61610974d60d5851f3fd8b70f.zip gcc-8a20b4bc50bdc8d61610974d60d5851f3fd8b70f.tar.gz gcc-8a20b4bc50bdc8d61610974d60d5851f3fd8b70f.tar.bz2 | |
xtensa: Merge '*addx' and '*subx' insn patterns into one
By making use of the 'addsub_operator' added in the last patch.
gcc/ChangeLog:
* config/xtensa/xtensa.md (*addsubx): Rename from '*addx',
and change to also accept '*subx' pattern.
(*subx): Remove.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/xtensa/xtensa.md | 31 |
1 files changed, 13 insertions, 18 deletions
diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md index c75fde1..6c1d8ee 100644 --- a/gcc/config/xtensa/xtensa.md +++ b/gcc/config/xtensa/xtensa.md @@ -170,15 +170,24 @@ (set_attr "mode" "SI") (set_attr "length" "2,2,3,3,3")]) -(define_insn "*addx" +(define_insn "*addsubx" [(set (match_operand:SI 0 "register_operand" "=a") - (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "r") + (match_operator:SI 4 "addsub_operator" + [(ashift:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 3 "addsubx_operand" "i")) - (match_operand:SI 2 "register_operand" "r")))] + (match_operand:SI 2 "register_operand" "r")]))] "TARGET_ADDX" { operands[3] = GEN_INT (1 << INTVAL (operands[3])); - return "addx%3\t%0, %1, %2"; + switch (GET_CODE (operands[4])) + { + case PLUS: + return "addx%3\t%0, %1, %2"; + case MINUS: + return "subx%3\t%0, %1, %2"; + default: + gcc_unreachable (); + } } [(set_attr "type" "arith") (set_attr "mode" "SI") @@ -207,20 +216,6 @@ (set_attr "mode" "SI") (set_attr "length" "3")]) -(define_insn "*subx" - [(set (match_operand:SI 0 "register_operand" "=a") - (minus:SI (ashift:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:SI 3 "addsubx_operand" "i")) - (match_operand:SI 2 "register_operand" "r")))] - "TARGET_ADDX" -{ - operands[3] = GEN_INT (1 << INTVAL (operands[3])); - return "subx%3\t%0, %1, %2"; -} - [(set_attr "type" "arith") - (set_attr "mode" "SI") - (set_attr "length" "3")]) - (define_insn "subsf3" [(set (match_operand:SF 0 "register_operand" "=f") (minus:SF (match_operand:SF 1 "register_operand" "f") |