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| author | Alan Lawrence <alan.lawrence@arm.com> | 2014-11-04 12:05:52 +0000 |
|---|---|---|
| committer | Alan Lawrence <alalaw01@gcc.gnu.org> | 2014-11-04 12:05:52 +0000 |
| commit | 89edc9866776ba7805b40b592a2bb91252f8e1b5 (patch) | |
| tree | 45808ba2a019b97364e7c6c34cdc28a8f4dfb2e4 /gcc | |
| parent | 95d47b10bedd6cbdd7d18f8d59ea5bcee14d04a6 (diff) | |
| download | gcc-89edc9866776ba7805b40b592a2bb91252f8e1b5.zip gcc-89edc9866776ba7805b40b592a2bb91252f8e1b5.tar.gz gcc-89edc9866776ba7805b40b592a2bb91252f8e1b5.tar.bz2 | |
[ARM] Migrate to new reduc_plus_scal_optab
config/arm/neon.md (reduc_plus_*): Rename to...
(reduc_plus_scal_*): ...this; reduce to temp and extract scalar result.
From-SVN: r217079
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/arm/neon.md | 43 |
2 files changed, 28 insertions, 20 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5eb313d..a2568e4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2014-11-04 Alan Lawrence <alan.lawrence@arm.com> + + config/arm/neon.md (reduc_plus_*): Rename to... + (reduc_plus_scal_*): ...this; reduce to temp and extract scalar result. + 2014-11-04 Michael Collison <michael.collison@linaro.org> * config/aarch64/iterators.md (lconst_atomic): New mode attribute diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index a0ec446..4827015 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -1349,33 +1349,47 @@ ;; Reduction operations -(define_expand "reduc_splus_<mode>" - [(match_operand:VD 0 "s_register_operand" "") +(define_expand "reduc_plus_scal_<mode>" + [(match_operand:<V_elem> 0 "nonimmediate_operand" "") (match_operand:VD 1 "s_register_operand" "")] "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)" { - neon_pairwise_reduce (operands[0], operands[1], <MODE>mode, + rtx vec = gen_reg_rtx (<MODE>mode); + neon_pairwise_reduce (vec, operands[1], <MODE>mode, &gen_neon_vpadd_internal<mode>); + /* The same result is actually computed into every element. */ + emit_insn (gen_vec_extract<mode> (operands[0], vec, const0_rtx)); DONE; }) -(define_expand "reduc_splus_<mode>" - [(match_operand:VQ 0 "s_register_operand" "") +(define_expand "reduc_plus_scal_<mode>" + [(match_operand:<V_elem> 0 "nonimmediate_operand" "") (match_operand:VQ 1 "s_register_operand" "")] "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations) && !BYTES_BIG_ENDIAN" { rtx step1 = gen_reg_rtx (<V_HALF>mode); - rtx res_d = gen_reg_rtx (<V_HALF>mode); emit_insn (gen_quad_halves_plus<mode> (step1, operands[1])); - emit_insn (gen_reduc_splus_<V_half> (res_d, step1)); - emit_insn (gen_move_lo_quad_<mode> (operands[0], res_d)); + emit_insn (gen_reduc_plus_scal_<V_half> (operands[0], step1)); + + DONE; +}) + +(define_expand "reduc_plus_scal_v2di" + [(match_operand:DI 0 "nonimmediate_operand" "=w") + (match_operand:V2DI 1 "s_register_operand" "")] + "TARGET_NEON && !BYTES_BIG_ENDIAN" +{ + rtx vec = gen_reg_rtx (V2DImode); + + emit_insn (gen_arm_reduc_plus_internal_v2di (vec, operands[1])); + emit_insn (gen_vec_extractv2di (operands[0], vec, const0_rtx)); DONE; }) -(define_insn "reduc_splus_v2di" +(define_insn "arm_reduc_plus_internal_v2di" [(set (match_operand:V2DI 0 "s_register_operand" "=w") (unspec:V2DI [(match_operand:V2DI 1 "s_register_operand" "w")] UNSPEC_VPADD))] @@ -1384,17 +1398,6 @@ [(set_attr "type" "neon_add_q")] ) -;; NEON does not distinguish between signed and unsigned addition except on -;; widening operations. -(define_expand "reduc_uplus_<mode>" - [(match_operand:VDQI 0 "s_register_operand" "") - (match_operand:VDQI 1 "s_register_operand" "")] - "TARGET_NEON && (<Is_d_reg> || !BYTES_BIG_ENDIAN)" -{ - emit_insn (gen_reduc_splus_<mode> (operands[0], operands[1])); - DONE; -}) - (define_expand "reduc_smin_<mode>" [(match_operand:VD 0 "s_register_operand" "") (match_operand:VD 1 "s_register_operand" "")] |