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author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-08-10 17:21:46 +0800 |
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committer | Pan Li <pan2.li@intel.com> | 2023-08-10 20:29:47 +0800 |
commit | 887f13916b18f46b563d527ad5001c6384e44a60 (patch) | |
tree | 450ff376aae54ff84db00b0a20d3e0849cf9cfc3 /gcc | |
parent | 9b8ebdb60c463fa3641692a21ca0ce24fba89260 (diff) | |
download | gcc-887f13916b18f46b563d527ad5001c6384e44a60.zip gcc-887f13916b18f46b563d527ad5001c6384e44a60.tar.gz gcc-887f13916b18f46b563d527ad5001c6384e44a60.tar.bz2 |
RISC-V: Support TU for integer ternary OP[PR110964]
PR target/110964
gcc/ChangeLog:
PR target/110964
* config/riscv/riscv-v.cc (expand_cond_len_ternop): Add integer ternary.
gcc/testsuite/ChangeLog:
PR target/110964
* gcc.target/riscv/rvv/autovec/pr110964.c: New test.
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/config/riscv/riscv-v.cc | 3 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110964.c | 13 |
2 files changed, 14 insertions, 2 deletions
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index c9f0a4a..a3062c9 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -3604,8 +3604,7 @@ expand_cond_len_ternop (unsigned icode, rtx *ops) if (FLOAT_MODE_P (mode)) emit_nonvlmax_fp_ternary_tu_insn (icode, RVV_TERNOP_TU, ops, len); else - /* FIXME: Enable this case when we support it in the middle-end. */ - gcc_unreachable (); + emit_nonvlmax_tu_insn (icode, RVV_TERNOP_TU, ops, len); } else { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110964.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110964.c new file mode 100644 index 0000000..cf2d1fb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110964.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -Ofast" } */ + +int *a; +long b, c; + +int d () +{ + const int e; + for (; a < e; a++) /* { dg-warning "comparison between pointer and integer" } */ + c += *a * b; +} + |