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| author | Uros Bizjak <ubizjak@gmail.com> | 2023-12-18 22:18:05 +0100 |
|---|---|---|
| committer | Uros Bizjak <ubizjak@gmail.com> | 2023-12-18 22:18:56 +0100 |
| commit | 86b6daefc8ca00f6879779f6002ca575920d38d2 (patch) | |
| tree | a0605969566d35e7aeaeb687335a0b3eac2758ae /gcc | |
| parent | b77691a90fc8a7e917417ce747bf78669304f951 (diff) | |
| download | gcc-86b6daefc8ca00f6879779f6002ca575920d38d2.zip gcc-86b6daefc8ca00f6879779f6002ca575920d38d2.tar.gz gcc-86b6daefc8ca00f6879779f6002ca575920d38d2.tar.bz2 | |
i386: Eliminate redundant compare between set{z,nz} and j{z,nz}
Eliminate redundant compare between set{z,nz} and j{z,nz}:
setz %al; test %al,%al; jz <...> -> setz %al; jnz <...> and
setnz %al, test %al,%al; jz <...> -> setnz %al; jz <...>.
We can use the original Zero-flag value instead of setting the
temporary register and testing it for zero.
gcc/ChangeLog:
* config/i386/i386.md (redundant compare peephole2):
New peephole2 pattern.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/i386/i386.md | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index f83064e..e862368 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -18118,6 +18118,35 @@ FAIL; }) +;; Eliminate redundant compare between set{z,nz} and j{z,nz}: +;; setz %al; test %al,%al; jz <...> -> setz %al; jnz <...> and +;; setnz %al, test %al,%al; jz <...> -> setnz %al; jz <...>. +(define_peephole2 + [(set (match_operand:QI 0 "nonimmediate_operand") + (match_operator:QI 1 "bt_comparison_operator" + [(reg:CCZ FLAGS_REG) (const_int 0)])) + (set (reg:CCZ FLAGS_REG) + (compare:CCZ (match_dup 0) (const_int 0))) + (set (pc) + (if_then_else (match_operator 2 "bt_comparison_operator" + [(reg:CCZ FLAGS_REG) (const_int 0)]) + (match_operand 3) + (pc)))] + "peep2_regno_dead_p (3, FLAGS_REG)" + [(set (match_dup 0) + (match_op_dup 1 [(reg:CCZ FLAGS_REG) (const_int 0)])) + (set (pc) + (if_then_else (match_dup 2) + (match_dup 3) + (pc)))] +{ + if (GET_CODE (operands[1]) == EQ) + { + operands[2] = shallow_copy_rtx (operands[2]); + PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2]))); + } +}) + ;; The SSE store flag instructions saves 0 or 0xffffffff to the result. ;; subsequent logical operations are used to imitate conditional moves. ;; 0xffffffff is NaN, but not in normalized form, so we can't represent |