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authorRichard Henderson <rth@cygnus.com>1999-03-11 06:02:42 -0800
committerRichard Henderson <rth@gcc.gnu.org>1999-03-11 06:02:42 -0800
commit827e80cc8b2870fe81e6c7857ce5d8eb78edc59e (patch)
treea75e6c2302d98a23a7946256a85846e6cfa8e5bd /gcc
parenta7adf08e8429685a68f3b2629806ff2c03e781a5 (diff)
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* alpha.md (ev5_e0): Conflict loads and stores.
From-SVN: r25705
Diffstat (limited to 'gcc')
-rw-r--r--gcc/ChangeLog2
-rw-r--r--gcc/config/alpha/alpha.md9
2 files changed, 9 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 21a9c22..f9e698a 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -3,6 +3,8 @@ Thu Mar 11 14:00:58 1999 Richard Henderson <rth@cygnus.com>
* alpha.h (HARD_REGNO_MODE_OK): Disallow QI/HImode in fp regs.
(MODES_TIEABLE_P): Update.
+ * alpha.md (ev5_e0): Conflict loads and stores.
+
Thu Mar 11 13:55:52 1999 Richard Henderson <rth@cygnus.com>
* machmode.h (smallest_mode_for_size): Prototype.
diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md
index 82c1089..55bdc11 100644
--- a/gcc/config/alpha/alpha.md
+++ b/gcc/config/alpha/alpha.md
@@ -155,13 +155,18 @@
; Memory takes at least 2 clocks. Return one from here and fix up with
; user-defined latencies in adjust_cost.
-; ??? How to: "An instruction of class LD cannot be issued in the _second_
-; cycle after an instruction of class ST is issued."
(define_function_unit "ev5_ebox" 2 0
(and (eq_attr "cpu" "ev5")
(eq_attr "type" "ild,fld,ldsym"))
1 1)
+; Loads can dual issue with one another, but loads and stores do not mix.
+(define_function_unit "ev5_e0" 1 0
+ (and (eq_attr "cpu" "ev5")
+ (eq_attr "type" "ild,fld,ldsym"))
+ 1 1
+ [(eq_attr "type" "ist,fst")])
+
; Stores, shifts, multiplies can only issue to E0
(define_function_unit "ev5_e0" 1 0
(and (eq_attr "cpu" "ev5")