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| author | Walter Lee <walt@tilera.com> | 2016-11-19 02:30:41 +0000 |
|---|---|---|
| committer | Walter Lee <walt@gcc.gnu.org> | 2016-11-19 02:30:41 +0000 |
| commit | 814049be46390dc4fb5c938abf13619b38e696d8 (patch) | |
| tree | 9321f2670ad72e16575266333f983f2f13a8fc01 /gcc | |
| parent | 7a384912f9f80b69d7b0857f1bb1f722203f3e2d (diff) | |
| download | gcc-814049be46390dc4fb5c938abf13619b38e696d8.zip gcc-814049be46390dc4fb5c938abf13619b38e696d8.tar.gz gcc-814049be46390dc4fb5c938abf13619b38e696d8.tar.bz2 | |
TILE-Gx: fix clzsi2 for big-endian.
* config/tilegx/tilegx.md (clzsi2): Fix for big-endian.
From-SVN: r242616
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/config/tilegx/tilegx.md | 27 |
2 files changed, 18 insertions, 13 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6793869..13b60c2 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2016-11-18 Walter Lee <walt@tilera.com> + + * config/tilegx/tilegx.md (clzsi2): Fix for big-endian. + 2016-11-18 Jakub Jelinek <jakub@redhat.com> PR middle-end/78419 diff --git a/gcc/config/tilegx/tilegx.md b/gcc/config/tilegx/tilegx.md index 361d51c..55c345c 100644 --- a/gcc/config/tilegx/tilegx.md +++ b/gcc/config/tilegx/tilegx.md @@ -1798,19 +1798,20 @@ [(set_attr "type" "Y0")]) (define_expand "clzsi2" - [(set (match_dup 2) - (zero_extend:DI (match_operand:SI 1 "reg_or_0_operand" ""))) - (set (match_dup 2) - (ashift:DI (match_dup 2) - (const_int 32))) - (set (match_dup 2) - (clz:DI (match_dup 2))) - (set (match_operand:SI 0 "register_operand" "") - (subreg:SI (match_dup 2) 0))] - "" - { - operands[2] = gen_reg_rtx (DImode); - }) + [(set (match_operand:SI 0 "register_operand" "=r") + (clz:SI (match_operand:SI 1 "reg_or_0_operand" "rO")))] + "" + { + rtx tmp1 = gen_reg_rtx (DImode); + rtx tmp2 = gen_reg_rtx (DImode); + rtx tmp3 = gen_reg_rtx (DImode); + + emit_insn (gen_zero_extendsidi2 (tmp1, operands[1])); + emit_insn (gen_ashldi3 (tmp2, tmp1, (GEN_INT (32)))); + emit_insn (gen_clzdi2 (tmp3, tmp2)); + emit_move_insn (operands[0], gen_lowpart (SImode, tmp3)); + DONE; + }) (define_insn "ctz<mode>2" [(set (match_operand:I48MODE 0 "register_operand" "=r") |