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| author | Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org> | 2011-03-15 16:14:21 +0000 |
|---|---|---|
| committer | Ramana Radhakrishnan <ramana@gcc.gnu.org> | 2011-03-15 16:14:21 +0000 |
| commit | 80fffdef8fb97cc8e1774cfdaf2eabd07c9a7867 (patch) | |
| tree | 7ad79e45595c25990addd5141b192080efc5640c /gcc | |
| parent | 930672adb7c3ae012e0af46eb19b0e8de1974cfb (diff) | |
| download | gcc-80fffdef8fb97cc8e1774cfdaf2eabd07c9a7867.zip gcc-80fffdef8fb97cc8e1774cfdaf2eabd07c9a7867.tar.gz gcc-80fffdef8fb97cc8e1774cfdaf2eabd07c9a7867.tar.bz2 | |
re PR c++/47688 ([C++0x] Segfault when assigning lambda to std::function variable)
Fix PR 47688
2011-03-18 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
PR target/47668
gcc/
* config/arm/arm.md (arm_movtas_ze): Use 'L' instead of 'c'
in the output template.
gcc/testsuite/
* gcc.target/arm/pr47688.c: New.
From-SVN: r171000
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 4 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/pr47688.c | 26 |
4 files changed, 40 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d3f2eef..572309c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2011-03-15 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org> + + PR target/47668 + * config/arm/arm.md (arm_movtas_ze): Use 'L' instead of 'c' + in the output template. + 2011-03-15 Richard Guenther <rguenther@suse.de> PR middle-end/47650 diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 6f31e62..b0f31f5 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -10580,13 +10580,15 @@ [(set_attr "conds" "clob")] ) +;; We only care about the lower 16 bits of the constant +;; being inserted into the upper 16 bits of the register. (define_insn "*arm_movtas_ze" [(set (zero_extract:SI (match_operand:SI 0 "s_register_operand" "+r") (const_int 16) (const_int 16)) (match_operand:SI 1 "const_int_operand" ""))] "arm_arch_thumb2" - "movt%?\t%0, %c1" + "movt%?\t%0, %L1" [(set_attr "predicable" "yes") (set_attr "length" "4")] ) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 753f900..2897366 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2011-03-15 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org> + + PR target/47688 + * gcc.target/arm/pr47688.c: New. + 2011-03-15 Richard Guenther <rguenther@suse.de> PR middle-end/47650 diff --git a/gcc/testsuite/gcc.target/arm/pr47688.c b/gcc/testsuite/gcc.target/arm/pr47688.c new file mode 100644 index 0000000..2236769 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr47688.c @@ -0,0 +1,26 @@ +/* { dg-options "-mthumb -O2" } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-final { scan-assembler-not "-32768" } } */ + +typedef union +{ + unsigned long int u_32_value; + struct + { + unsigned short int u_16_value_0; + unsigned short int u_16_value_1; + } u_16_values; +} my_union; + + +unsigned long int Test(const unsigned short int wXe) +{ + my_union dwCalcVal; + + dwCalcVal.u_16_values.u_16_value_0=wXe; + dwCalcVal.u_16_values.u_16_value_1=0x8000u; + + dwCalcVal.u_32_value /=3; + + return (dwCalcVal.u_32_value); +} |