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| author | Richard Henderson <rth@cygnus.com> | 1998-11-06 11:43:53 -0800 |
|---|---|---|
| committer | Richard Henderson <rth@gcc.gnu.org> | 1998-11-06 11:43:53 -0800 |
| commit | 80df65c95e51ff36d97aa13eed0d0e6a4fa1beee (patch) | |
| tree | 232008f49240050d5a83b13421d9b72afef7881a /gcc | |
| parent | d30e8ef0dcdb0ae77a98d79879fe07600d9c4c77 (diff) | |
| download | gcc-80df65c95e51ff36d97aa13eed0d0e6a4fa1beee.zip gcc-80df65c95e51ff36d97aa13eed0d0e6a4fa1beee.tar.gz gcc-80df65c95e51ff36d97aa13eed0d0e6a4fa1beee.tar.bz2 | |
alpha.c (add_operand): Simplify the CONST_INT match.
* alpha.c (add_operand): Simplify the CONST_INT match.
(sext_add_operand): Correct typo in comparison by using
CONST_OK_FOR_LETTER_P.
* alpha.md (s?addq): Use sext_add_operand to allow the negative
constant alternatives to be generated.
(mulsi3, muldi3, umuldi3_highpart): Loosen constraints to allow
small constants, since the hw instructions do.
From-SVN: r23551
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 10 | ||||
| -rw-r--r-- | gcc/config/alpha/alpha.c | 8 | ||||
| -rw-r--r-- | gcc/config/alpha/alpha.md | 25 |
3 files changed, 28 insertions, 15 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1c94751..e420927 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +Fri Nov 6 19:37:33 1998 Richard Henderson <rth@cygnus.com> + + * alpha.c (add_operand): Simplify the CONST_INT match. + (sext_add_operand): Correct typo in comparison by using + CONST_OK_FOR_LETTER_P. + * alpha.md (s?addq): Use sext_add_operand to allow the negative + constant alternatives to be generated. + (mulsi3, muldi3, umuldi3_highpart): Loosen constraints to allow + small constants, since the hw instructions do. + Fri Nov 6 20:15:19 1998 Bernd Schmidt <crux@pool.informatik.rwth-aachen.de> * reload1.c (emit_reload_insns): When rewriting the SET_DEST of a diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c index c9506a6..3de6f59 100644 --- a/gcc/config/alpha/alpha.c +++ b/gcc/config/alpha/alpha.c @@ -386,9 +386,9 @@ add_operand (op, mode) enum machine_mode mode; { if (GET_CODE (op) == CONST_INT) + /* Constraints I, J, O and P are covered by K. */ return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'K') - || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L') - || CONST_OK_FOR_LETTER_P (INTVAL (op), 'O')); + || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')); else if (GET_CODE (op) == CONSTANT_P_RTX) return 1; @@ -404,8 +404,8 @@ sext_add_operand (op, mode) enum machine_mode mode; { if (GET_CODE (op) == CONST_INT) - return ((unsigned HOST_WIDE_INT) INTVAL (op) < 255 - || (unsigned HOST_WIDE_INT) (- INTVAL (op)) < 255); + return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'I') + || CONST_OK_FOR_LETTER_P (INTVAL (op), 'O')); else if (GET_CODE (op) == CONSTANT_P_RTX) return 1; diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index 8ae03e6..f1d8554 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -598,7 +598,7 @@ [(set (match_operand:DI 0 "register_operand" "=r,r") (plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ") (match_operand:DI 2 "const48_operand" "I,I")) - (match_operand:DI 3 "reg_or_8bit_operand" "rI,O")))] + (match_operand:DI 3 "sext_add_operand" "rI,O")))] "" "@ s%2addq %r1,%3,%0 @@ -784,38 +784,41 @@ (define_insn "mulsi3" [(set (match_operand:SI 0 "register_operand" "=r") (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ") - (match_operand:SI 2 "reg_or_0_operand" "rJ")))] + (match_operand:SI 2 "reg_or_8bit_operand" "rI")))] "" - "mull %r1,%r2,%0" + "mull %r1,%2,%0" [(set_attr "type" "imul") (set_attr "opsize" "si")]) (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") - (sign_extend:DI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ") - (match_operand:SI 2 "reg_or_0_operand" "rJ"))))] + (sign_extend:DI + (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ") + (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))] "" - "mull %r1,%r2,%0" + "mull %r1,%2,%0" [(set_attr "type" "imul") (set_attr "opsize" "si")]) (define_insn "muldi3" [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ") - (match_operand:DI 2 "reg_or_0_operand" "rJ")))] + (match_operand:DI 2 "reg_or_8bit_operand" "rI")))] "" - "mulq %r1,%r2,%0" + "mulq %r1,%2,%0" [(set_attr "type" "imul")]) (define_insn "umuldi3_highpart" [(set (match_operand:DI 0 "register_operand" "=r") (truncate:DI (lshiftrt:TI - (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r")) - (zero_extend:TI (match_operand:DI 2 "register_operand" "r"))) + (mult:TI (zero_extend:TI + (match_operand:DI 1 "reg_or_0_operand" "%rJ")) + (zero_extend:TI + (match_operand:DI 2 "reg_or_8bit_operand" "rI"))) (const_int 64))))] "" - "umulh %1,%2,%0" + "umulh %r1,%2,%0" [(set_attr "type" "imul") (set_attr "opsize" "udi")]) |