diff options
| author | Wilco Dijkstra <wdijkstr@arm.com> | 2016-12-08 19:18:33 +0000 |
|---|---|---|
| committer | Wilco Dijkstra <wilco@gcc.gnu.org> | 2016-12-08 19:18:33 +0000 |
| commit | 80d435794edaea1d7191b3ae93d988d31a2a6b20 (patch) | |
| tree | e2fecc79734bfc862c1cce548342eddf0fd76f1f /gcc | |
| parent | 7bf65250f195566a57ab6338aef7aa4d13c035a2 (diff) | |
| download | gcc-80d435794edaea1d7191b3ae93d988d31a2a6b20.zip gcc-80d435794edaea1d7191b3ae93d988d31a2a6b20.tar.gz gcc-80d435794edaea1d7191b3ae93d988d31a2a6b20.tar.bz2 | |
This patch fixes an issue in aarch64_classify_address.
This patch fixes an issue in aarch64_classify_address. TImode and TFmode
can either use a 64-bit LDP/STP or 128-bit LDR/STR. The addressing mode
must be carefully modelled as the intersection of both. This is done for
the immediate offsets, however load_store_pair_p must be set as well to
avoid LDP with a PC-relative address if aarch64_pcrelative_literal_loads
is true.
gcc/
PR target/78733
* config/aarch64/aarch64.c (aarch64_classify_address):
Set load_store_pair_p for TImode and TFmode.
testsuite/
* gcc.target/aarch64/pr78733.c: New test.
From-SVN: r243456
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.c | 5 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 |
3 files changed, 15 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1becd5f..ccb8281 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -3,6 +3,12 @@ * gcc.target/i386/i386.h (HARD_REGNO_NREGS): Use GENERAL_REGNO_P. (HARD_REGNO_NREGS_HAS_PADDING): Ditto. Simplify macro. +2015-12-08 Wilco Dijkstra <wdijkstr@arm.com> + + PR target/78733 + * config/aarch64/aarch64.c (aarch64_classify_address): + Set load_store_pair_p for TImode and TFmode. + 2016-12-08 David Malcolm <dmalcolm@redhat.com> * emit-rtl.c (gen_reg_rtx): Move regno_pointer_align and diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 1a06432..e87831f 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -4273,8 +4273,11 @@ aarch64_classify_address (struct aarch64_address_info *info, enum rtx_code code = GET_CODE (x); rtx op0, op1; - /* On BE, we use load/store pair for all large int mode load/stores. */ + /* On BE, we use load/store pair for all large int mode load/stores. + TI/TFmode may also use a load/store pair. */ bool load_store_pair_p = (outer_code == PARALLEL + || mode == TImode + || mode == TFmode || (BYTES_BIG_ENDIAN && aarch64_vect_struct_mode_p (mode))); diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 6342b9d..ba30327 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2015-12-08 Wilco Dijkstra <wdijkstr@arm.com> + + PR target/78733 + * gcc.target/aarch64/pr78733.c: New test. + 2016-12-08 Nathan Sidwell <nathan@acm.org> PR c++/78551 |