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| author | Michael Meissner <meissner@linux.ibm.com> | 2021-07-20 12:56:19 -0400 |
|---|---|---|
| committer | Michael Meissner <meissner@linux.ibm.com> | 2021-07-20 12:56:19 -0400 |
| commit | 7fcb33455c9dc9359d98cd6bffe7f32f282ed713 (patch) | |
| tree | f69c61bf41227703a3a1a3aace58a7bd7ba7cdf5 /gcc | |
| parent | e0e82856d535f56c916382f892ed2435dde54d4d (diff) | |
| download | gcc-7fcb33455c9dc9359d98cd6bffe7f32f282ed713.zip gcc-7fcb33455c9dc9359d98cd6bffe7f32f282ed713.tar.gz gcc-7fcb33455c9dc9359d98cd6bffe7f32f282ed713.tar.bz2 | |
PR 100167: Fix vector long long multiply/divide tests on power10.
This patch updates the vector long long multiply and divide tests to
supply the correct code information if power10 code generation is used.
2021-06-18 Michael Meissner <meissner@linux.ibm.com>
gcc/testsuite/
PR testsuite/100167
* gcc.target/powerpc/fold-vec-div-longlong.c: Fix expected code
generation on power10.
* gcc.target/powerpc/fold-vec-mult-longlong.c: Likewise.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c | 7 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c | 7 |
2 files changed, 10 insertions, 4 deletions
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c index 312e984..f6a9b29 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c @@ -19,5 +19,8 @@ test6 (vector unsigned long long x, vector unsigned long long y) { return vec_div (x, y); } -/* { dg-final { scan-assembler-times {\mdivd\M} 2 } } */ -/* { dg-final { scan-assembler-times {\mdivdu\M} 2 } } */ + +/* { dg-final { scan-assembler-times {\mdivd\M} 2 { target { ! has_arch_pwr10 } } } } */ +/* { dg-final { scan-assembler-times {\mdivdu\M} 2 { target { ! has_arch_pwr10 } } } } */ +/* { dg-final { scan-assembler-times {\mvdivsd\M} 1 { target { has_arch_pwr10 } } } } */ +/* { dg-final { scan-assembler-times {\mvdivud\M} 1 { target { has_arch_pwr10 } } } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c index 38dba9f..dff073d 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c @@ -20,5 +20,8 @@ test6 (vector unsigned long long x, vector unsigned long long y) return vec_mul (x, y); } -/* { dg-final { scan-assembler-times "\[ \t\]mulld " 4 { target lp64 } } } */ - +/* Power10 can generate the vmulld instruction even in 32-bit. Before power10, + we limit the code to lp64, since 32-bit cannot generate the mulld + instruction. */ +/* { dg-final { scan-assembler-times {\mmulld\M} 4 { target { lp64 && { ! has_arch_pwr10 } } } } } */ +/* { dg-final { scan-assembler-times {\mvmulld\M} 2 { target { has_arch_pwr10 } } } } */ |