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| author | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2023-04-23 14:44:13 +0100 |
|---|---|---|
| committer | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2023-04-23 14:44:13 +0100 |
| commit | 7e26fd6bcd39f53bc917f55f8cce6101180c1dcd (patch) | |
| tree | 2f05b9206b2a8d47ec5965239c07be5235aef965 /gcc | |
| parent | 3b13c59c835f92b353ef318398e39907cdeec4fa (diff) | |
| download | gcc-7e26fd6bcd39f53bc917f55f8cce6101180c1dcd.zip gcc-7e26fd6bcd39f53bc917f55f8cce6101180c1dcd.tar.gz gcc-7e26fd6bcd39f53bc917f55f8cce6101180c1dcd.tar.bz2 | |
aarch64: Annotate fcvtn pattern for vec_concat with zeroes
Using the define_substs in aarch64-simd.md this is a straightforward annotation to remove
a redundant fmov insn.
So the codegen goes from:
foo_d:
fcvtn v0.2s, v0.2d
fmov d0, d0
ret
to the simple:
foo_d:
fcvtn v0.2s, v0.2d
ret
Bootstrapped and tested on aarch64-none-linux-gnu.
gcc/ChangeLog:
* config/aarch64/aarch64-simd.md (aarch64_float_truncate_lo_): Rename to...
(aarch64_float_truncate_lo_<mode><vczle><vczbe>): ... This.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/float_truncate_zero.c: New test.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 2 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/float_truncate_zero.c | 32 |
2 files changed, 33 insertions, 1 deletions
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 4a1ec71..7bd4362 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -3331,7 +3331,7 @@ } ) -(define_insn "aarch64_float_truncate_lo_<mode>" +(define_insn "aarch64_float_truncate_lo_<mode><vczle><vczbe>" [(set (match_operand:VDF 0 "register_operand" "=w") (float_truncate:VDF (match_operand:<VWIDE> 1 "register_operand" "w")))] diff --git a/gcc/testsuite/gcc.target/aarch64/float_truncate_zero.c b/gcc/testsuite/gcc.target/aarch64/float_truncate_zero.c new file mode 100644 index 0000000..41775d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/float_truncate_zero.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-additional-options "--save-temps -O1" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#include <arm_neon.h> + +/* +** foo: +** fcvtn v0.4h, v0.4s +** ret +*/ + +float16x8_t +foo (float32x4_t a) +{ + float16x4_t b = vcvt_f16_f32 (a); + return vcombine_f16 (b, vdup_n_f16 (0.0)); +} + +/* +** foo_d: +** fcvtn v0.2s, v0.2d +** ret +*/ + +float32x4_t +foo_d (float64x2_t a) +{ + float32x2_t b = vcvt_f32_f64 (a); + return vcombine_f32 (b, vdup_n_f32 (0.0)); +} + |