[AArch64] Don't allow -mgeneral-regs-only to change the .arch assembler directives

	* config/aarch64/aarch64.c (aarch64_override_options_internal):
	Do not alter target_flags due to TARGET_GENERAL_REGS_ONLY_P.
	* doc/invoke.texi (AArch64 options): Mention that -mgeneral-regs-only
	does not affect the assembler directives.

	* gcc.target/aarch64/mgeneral-regs_4.c: New test.

From-SVN: r231275

5 files changed, 23 insertions, 17 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 59c50e0..9390f2b 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2015-12-04  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/aarch64/aarch64.c (aarch64_override_options_internal):
+	Do not alter target_flags due to TARGET_GENERAL_REGS_ONLY_P.
+	* doc/invoke.texi (AArch64 options): Mention that -mgeneral-regs-only
+	does not affect the assembler directives.
+
 2015-12-04  Dominik Vogt  <vogt@linux.vnet.ibm.com>
 
 	* config/s390/s390.c (s390_asm_file_start): Implement hook function to
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 5e3b5e0..ae4cfb3 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -8118,19 +8118,6 @@ aarch64_override_options_internal (struct gcc_options *opts)
   if (opts->x_flag_strict_volatile_bitfields < 0 && abi_version_at_least (2))
     opts->x_flag_strict_volatile_bitfields = 1;
 
-  /* -mgeneral-regs-only sets a mask in target_flags, make sure that
-     aarch64_isa_flags does not contain the FP/SIMD/Crypto feature flags
-     in case some code tries reading aarch64_isa_flags directly to check if
-     FP is available.  Reuse the aarch64_parse_extension machinery since it
-     knows how to disable any other flags that fp implies.  */
-  if (TARGET_GENERAL_REGS_ONLY_P (opts->x_target_flags))
-    {
-      /* aarch64_parse_extension takes char* rather than const char* because
-	 it is usually called from within other parsing functions.  */
-      char tmp_str[] = "+nofp";
-      aarch64_parse_extension (tmp_str, &opts->x_aarch64_isa_flags);
-    }
-
   initialize_aarch64_code_model (opts);
   initialize_aarch64_tls_size (opts);
 
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 586f11f..3138c7d 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -12480,10 +12480,9 @@ Generate big-endian code.  This is the default when GCC is configured for an
 
 @item -mgeneral-regs-only
 @opindex mgeneral-regs-only
-Generate code which uses only the general-purpose registers.  This is equivalent
-to feature modifier @option{nofp} of @option{-march} or @option{-mcpu}, except
-that @option{-mgeneral-regs-only} takes precedence over any conflicting feature
-modifier regardless of sequence.
+Generate code which uses only the general-purpose registers.  This will prevent
+the compiler from using floating-point and Advanced SIMD registers but will not
+impose any restrictions on the assembler.
 
 @item -mlittle-endian
 @opindex mlittle-endian
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index b304173..50df41c 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2015-12-04  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* gcc.target/aarch64/mgeneral-regs_4.c: New test.
+
 2015-12-04  Dominik Vogt  <vogt@linux.vnet.ibm.com>
 
 	* gcc.dg/Wframe-address.c: S/390 requires the -mbackchain option to
diff --git a/gcc/testsuite/gcc.target/aarch64/mgeneral-regs_4.c b/gcc/testsuite/gcc.target/aarch64/mgeneral-regs_4.c
new file mode 100644
index 0000000..8eb50aa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/mgeneral-regs_4.c
@@ -0,0 +1,9 @@
+/* { dg-options "-mgeneral-regs-only -march=armv8-a+simd+fp -O2" } */
+
+int
+test (void)
+{
+  return 1;
+}
+
+/* { dg-final { scan-assembler "\.arch.*fp.*simd" } } */