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| author | Alan Modra <amodra@gmail.com> | 2019-05-21 23:06:04 +0930 |
|---|---|---|
| committer | Alan Modra <amodra@gcc.gnu.org> | 2019-05-21 23:06:04 +0930 |
| commit | 78e5da0aa817ac7e84a5f0e803a5b8b94fa122e0 (patch) | |
| tree | 742d0f748538ef5a69eb6d4ce8d8a55f84539ca2 /gcc | |
| parent | 4f8b89f092467f9550cb2aa873c2e30ac809c08a (diff) | |
| download | gcc-78e5da0aa817ac7e84a5f0e803a5b8b94fa122e0.zip gcc-78e5da0aa817ac7e84a5f0e803a5b8b94fa122e0.tar.gz gcc-78e5da0aa817ac7e84a5f0e803a5b8b94fa122e0.tar.bz2 | |
PR90545, gcc.target/powerpc/fold-vec-splats-floatdouble.c fails
I figure a tweak to register_move_cost is better than sprinkling ?s
in instruction operand alternatives.
PR target/90545
* config/rs6000/rs6000.c (rs6000_register_move_cost): Increase
power9 direct move cost.
* testsuite/gcc.target/powerpc/fold-vec-splats-floatdouble.c:
Correct comments and rename functions to suit parameters.
From-SVN: r271464
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.c | 8 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/powerpc/fold-vec-splats-floatdouble.c | 8 |
3 files changed, 19 insertions, 5 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index cd55c4d..eff11af 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2019-05-21 Alan Modra <amodra@gmail.com> + + PR target/90545 + * config/rs6000/rs6000.c (rs6000_register_move_cost): Increase + power9 direct move cost. + * testsuite/gcc.target/powerpc/fold-vec-splats-floatdouble.c: + Correct comments and rename functions to suit parameters. + 2019-05-21 Richard Biener <rguenther@suse.de> PR middle-end/90510 diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 9842981..693f2e1 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -34657,8 +34657,14 @@ rs6000_register_move_cost (machine_mode mode, { if (TARGET_DIRECT_MOVE) { + /* Keep the cost for direct moves above that for within + a register class even if the actual processor cost is + comparable. We do this because a direct move insn + can't be a nop, whereas with ideal register + allocation a move within the same class might turn + out to be a nop. */ if (rs6000_tune == PROCESSOR_POWER9) - ret = 2 * hard_regno_nregs (FIRST_GPR_REGNO, mode); + ret = 3 * hard_regno_nregs (FIRST_GPR_REGNO, mode); else ret = 4 * hard_regno_nregs (FIRST_GPR_REGNO, mode); /* SFmode requires a conversion when moving between gprs diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-splats-floatdouble.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-splats-floatdouble.c index c4544f1..3c7cc7c 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-splats-floatdouble.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-splats-floatdouble.c @@ -8,20 +8,20 @@ #include <altivec.h> vector float -test1d (float x) +test1f (float x) { return vec_splats (x); } vector double -test1f (double x) +test1d (double x) { return vec_splats (x); } -// float test generates the permute instruction. +// double test generates the permute instruction. /* { dg-final { scan-assembler-times "xxpermdi" 1 } } */ -// double test generates a convert (double to single non-signalling) followed by a splat. +// float test generates a convert (double to single non-signalling) followed by a splat. /* { dg-final { scan-assembler-times {\mxscvdpspn?\M} 1 } } */ /* { dg-final { scan-assembler-times {\mvspltw\M|\mxxspltw\M} 1 } } */ |