diff options
| author | Jan Beulich <jbeulich@suse.com> | 2019-06-28 13:21:53 +0000 |
|---|---|---|
| committer | Jan Beulich <jbeulich@gcc.gnu.org> | 2019-06-28 13:21:53 +0000 |
| commit | 778d120f731f303c243b8a440c0cdfdf6b91339b (patch) | |
| tree | 60ee96d018817b24084bf8fd7f0ed8ea657bdcea /gcc | |
| parent | c0569d342ca43a2e90f1fd823dada3364705e5a9 (diff) | |
| download | gcc-778d120f731f303c243b8a440c0cdfdf6b91339b.zip gcc-778d120f731f303c243b8a440c0cdfdf6b91339b.tar.gz gcc-778d120f731f303c243b8a440c0cdfdf6b91339b.tar.bz2 | |
x86: improve GFNI insns
There's no need for three alternatives: "v" without TARGET_AVX512F is
the same as "x".
From-SVN: r272784
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/i386/sse.md | 43 |
2 files changed, 26 insertions, 23 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f30fedc..9cc900d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,6 +1,12 @@ 2019-06-28 Jan Beulich <jbeulich@suse.com> * config/i386/sse.md (vgf2p8affineinvqb_<mode><mask_name>, + vgf2p8affineqb_<mode><mask_name>, vgf2p8mulb_<mode><mask_name>): + Eliminate redundant alternative. + +2019-06-28 Jan Beulich <jbeulich@suse.com> + + * config/i386/sse.md (vgf2p8affineinvqb_<mode><mask_name>, vgf2p8affineqb_<mode><mask_name>): Drop % constraint modifier. Use vector_operand. diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 713e3c8..6831487 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -22110,56 +22110,53 @@ "vpopcnt<ssemodesuffix>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}") (define_insn "vgf2p8affineinvqb_<mode><mask_name>" - [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,x,v") + [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,v") (unspec:VI1_AVX512F - [(match_operand:VI1_AVX512F 1 "register_operand" "0,x,v") - (match_operand:VI1_AVX512F 2 "vector_operand" "xBm,xm,vm") - (match_operand:QI 3 "const_0_to_255_operand" "n,n,n")] + [(match_operand:VI1_AVX512F 1 "register_operand" "0,v") + (match_operand:VI1_AVX512F 2 "vector_operand" "xBm,vm") + (match_operand:QI 3 "const_0_to_255_operand" "n,n")] UNSPEC_GF2P8AFFINEINV))] "TARGET_GFNI" "@ gf2p8affineinvqb\t{%3, %2, %0| %0, %2, %3} - vgf2p8affineinvqb\t{%3, %2, %1, %0<mask_operand4>| %0<mask_operand4>, %1, %2, %3} vgf2p8affineinvqb\t{%3, %2, %1, %0<mask_operand4>| %0<mask_operand4>, %1, %2, %3}" - [(set_attr "isa" "noavx,avx,avx512f") - (set_attr "prefix_data16" "1,*,*") + [(set_attr "isa" "noavx,avx") + (set_attr "prefix_data16" "1,*") (set_attr "prefix_extra" "1") - (set_attr "prefix" "orig,maybe_evex,evex") + (set_attr "prefix" "orig,maybe_evex") (set_attr "mode" "<sseinsnmode>")]) (define_insn "vgf2p8affineqb_<mode><mask_name>" - [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,x,v") + [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,v") (unspec:VI1_AVX512F - [(match_operand:VI1_AVX512F 1 "register_operand" "0,x,v") - (match_operand:VI1_AVX512F 2 "vector_operand" "xBm,xm,vm") - (match_operand:QI 3 "const_0_to_255_operand" "n,n,n")] + [(match_operand:VI1_AVX512F 1 "register_operand" "0,v") + (match_operand:VI1_AVX512F 2 "vector_operand" "xBm,vm") + (match_operand:QI 3 "const_0_to_255_operand" "n,n")] UNSPEC_GF2P8AFFINE))] "TARGET_GFNI" "@ gf2p8affineqb\t{%3, %2, %0| %0, %2, %3} - vgf2p8affineqb\t{%3, %2, %1, %0<mask_operand4>| %0<mask_operand4>, %1, %2, %3} vgf2p8affineqb\t{%3, %2, %1, %0<mask_operand4>| %0<mask_operand4>, %1, %2, %3}" - [(set_attr "isa" "noavx,avx,avx512f") - (set_attr "prefix_data16" "1,*,*") + [(set_attr "isa" "noavx,avx") + (set_attr "prefix_data16" "1,*") (set_attr "prefix_extra" "1") - (set_attr "prefix" "orig,maybe_evex,evex") + (set_attr "prefix" "orig,maybe_evex") (set_attr "mode" "<sseinsnmode>")]) (define_insn "vgf2p8mulb_<mode><mask_name>" - [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,x,v") + [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,v") (unspec:VI1_AVX512F - [(match_operand:VI1_AVX512F 1 "register_operand" "%0,x,v") - (match_operand:VI1_AVX512F 2 "nonimmediate_operand" "xBm,xm,vm")] + [(match_operand:VI1_AVX512F 1 "register_operand" "%0,v") + (match_operand:VI1_AVX512F 2 "vector_operand" "xBm,vm")] UNSPEC_GF2P8MUL))] "TARGET_GFNI" "@ gf2p8mulb\t{%2, %0| %0, %2} - vgf2p8mulb\t{%2, %1, %0<mask_operand3>| %0<mask_operand3>, %1, %2} vgf2p8mulb\t{%2, %1, %0<mask_operand3>| %0<mask_operand3>, %1, %2}" - [(set_attr "isa" "noavx,avx,avx512f") - (set_attr "prefix_data16" "1,*,*") + [(set_attr "isa" "noavx,avx") + (set_attr "prefix_data16" "1,*") (set_attr "prefix_extra" "1") - (set_attr "prefix" "orig,maybe_evex,evex") + (set_attr "prefix" "orig,maybe_evex") (set_attr "mode" "<sseinsnmode>")]) (define_insn "vpshrd_<mode><mask_name>" |