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| author | James Greenhalgh <james.greenhalgh@arm.com> | 2013-05-01 10:46:00 +0000 |
|---|---|---|
| committer | James Greenhalgh <jgreenhalgh@gcc.gnu.org> | 2013-05-01 10:46:00 +0000 |
| commit | 75dd5aceb27fb1f07bfacff3aa5968b273cc13eb (patch) | |
| tree | efa0bf873bbaafe0d059f33a9de352bcf67ad506 /gcc | |
| parent | ad755ff16d3dae0788c1cde3fe0e960b00103cf6 (diff) | |
| download | gcc-75dd5aceb27fb1f07bfacff3aa5968b273cc13eb.zip gcc-75dd5aceb27fb1f07bfacff3aa5968b273cc13eb.tar.gz gcc-75dd5aceb27fb1f07bfacff3aa5968b273cc13eb.tar.bz2 | |
[AArch64] Add combiner patterns for FAC instructions
gcc/
* config/aarch64/aarch64-simd.md (*aarch64_fac<optab><mode>): New.
* config/aarch64/iterators.md (FAC_COMPARISONS): New.
From-SVN: r198494
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 17 | ||||
| -rw-r--r-- | gcc/config/aarch64/iterators.md | 3 |
3 files changed, 25 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d0392c8..ccc1fc7 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2013-05-01 James Greenhalgh <james.greenhalgh@arm.com> + * config/aarch64/aarch64-simd.md (*aarch64_fac<optab><mode>): New. + * config/aarch64/iterators.md (FAC_COMPARISONS): New. + +2013-05-01 James Greenhalgh <james.greenhalgh@arm.com> + * config/aarch64/aarch64-simd.md (vcond<mode>_internal): Handle special cases for constant masks. (vcond<mode><mode>): Allow nonmemory_operands for outcome vectors. diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index dfe4acb..21c2a68 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -3400,6 +3400,23 @@ (set_attr "simd_mode" "<MODE>")] ) +;; fac(ge|gt) +;; Note we can also handle what would be fac(le|lt) by +;; generating fac(ge|gt). + +(define_insn "*aarch64_fac<optab><mode>" + [(set (match_operand:<V_cmp_result> 0 "register_operand" "=w") + (neg:<V_cmp_result> + (FAC_COMPARISONS:<V_cmp_result> + (abs:VALLF (match_operand:VALLF 1 "register_operand" "w")) + (abs:VALLF (match_operand:VALLF 2 "register_operand" "w")) + )))] + "TARGET_SIMD" + "fac<n_optab>\t%<v>0<Vmtype>, %<v><cmp_1><Vmtype>, %<v><cmp_2><Vmtype>" + [(set_attr "simd_type" "simd_fcmp") + (set_attr "simd_mode" "<MODE>")] +) + ;; addp (define_insn "aarch64_addp<mode>" diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 0b9f9e8..00e315d 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -553,6 +553,9 @@ ;; Unsigned comparison operators. (define_code_iterator UCOMPARISONS [ltu leu geu gtu]) +;; Unsigned comparison operators. +(define_code_iterator FAC_COMPARISONS [lt le ge gt]) + ;; ------------------------------------------------------------------- ;; Code Attributes ;; ------------------------------------------------------------------- |