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| author | Eric Botcazou <ebotcazou@adacore.com> | 2013-11-20 13:58:12 +0000 |
|---|---|---|
| committer | Eric Botcazou <ebotcazou@gcc.gnu.org> | 2013-11-20 13:58:12 +0000 |
| commit | 74e25e34f85cc0a274cc82fd572ea62f619f8ccf (patch) | |
| tree | a8aae0c036dd880dbf4332000688e9f9a37e0d06 /gcc | |
| parent | c34fb198320a6a433f5ad4c10b9d0c7e6f280e28 (diff) | |
| download | gcc-74e25e34f85cc0a274cc82fd572ea62f619f8ccf.zip gcc-74e25e34f85cc0a274cc82fd572ea62f619f8ccf.tar.gz gcc-74e25e34f85cc0a274cc82fd572ea62f619f8ccf.tar.bz2 | |
arm.c (arm_dwarf_register_span): Take into account the endianness of the D registers for the legacy encodings.
* config/arm/arm.c (arm_dwarf_register_span): Take into account the
endianness of the D registers for the legacy encodings.
From-SVN: r205118
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/arm/arm.c | 33 |
2 files changed, 31 insertions, 7 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1064cfe..02b9cf5 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2013-11-20 Eric Botcazou <ebotcazou@adacore.com> + + * config/arm/arm.c (arm_dwarf_register_span): Take into account the + endianness of the D registers for the legacy encodings. + 2013-11-20 Richard Earnshaw <rearnsha@arm.com> PR rtl-optimization/54300 diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index e8b5f83..0d68f01 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -27992,10 +27992,11 @@ arm_dbx_register_number (unsigned int regno) static rtx arm_dwarf_register_span (rtx rtl) { + enum machine_mode mode; unsigned regno; + rtx parts[8]; int nregs; int i; - rtx p; regno = REGNO (rtl); if (!IS_VFP_REGNUM (regno)) @@ -28008,15 +28009,33 @@ arm_dwarf_register_span (rtx rtl) corresponding D register. Until GDB supports this, we shall use the legacy encodings. We also use these encodings for D0-D15 for compatibility with older debuggers. */ - if (VFP_REGNO_OK_FOR_SINGLE (regno)) + mode = GET_MODE (rtl); + if (GET_MODE_SIZE (mode) < 8) return NULL_RTX; - nregs = GET_MODE_SIZE (GET_MODE (rtl)) / 8; - p = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nregs)); - for (i = 0; i < nregs; i++) - XVECEXP (p, 0, i) = gen_rtx_REG (DImode, regno + i); + if (VFP_REGNO_OK_FOR_SINGLE (regno)) + { + nregs = GET_MODE_SIZE (mode) / 4; + for (i = 0; i < nregs; i += 2) + if (TARGET_BIG_END) + { + parts[i] = gen_rtx_REG (SImode, regno + i + 1); + parts[i + 1] = gen_rtx_REG (SImode, regno + i); + } + else + { + parts[i] = gen_rtx_REG (SImode, regno + i); + parts[i + 1] = gen_rtx_REG (SImode, regno + i + 1); + } + } + else + { + nregs = GET_MODE_SIZE (mode) / 8; + for (i = 0; i < nregs; i++) + parts[i] = gen_rtx_REG (DImode, regno + i); + } - return p; + return gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (nregs , parts)); } #if ARM_UNWIND_INFO |