alpha.c (reg_or_0_operand): Use CONST0_RTX.

        * config/alpha/alpha.c (reg_or_0_operand): Use CONST0_RTX.
        (const0_operand): New.
        (reg_or_fp0_operand, fp0_operand): Remove.
        * config/alpha/alpha.h (PREDICATE_CODES): Update.
        * config/alpha/alpha-protos.h: Update.
        * config/alpha/alpha.md: Replace all uses of reg_or_fp0_operand
        and fp0_operand with reg_or_0_operand and const0_operand.

From-SVN: r54226

5 files changed, 159 insertions, 161 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7f985e0..532d0f7 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2002-06-03  Richard Henderson  <rth@redhat.com>
+
+	* config/alpha/alpha.c (reg_or_0_operand): Use CONST0_RTX.
+	(const0_operand): New.
+	(reg_or_fp0_operand, fp0_operand): Remove.
+	* config/alpha/alpha.h (PREDICATE_CODES): Update.
+	* config/alpha/alpha-protos.h: Update.
+	* config/alpha/alpha.md: Replace all uses of reg_or_fp0_operand
+	and fp0_operand with reg_or_0_operand and const0_operand.
+
 2002-06-03  Dan Nicolaescu  <dann@godzilla.ics.uci.edu>
 
 	* alias.c (nonoverlapping_memrefs_p): Fix off by one error.
diff --git a/gcc/config/alpha/alpha-protos.h b/gcc/config/alpha/alpha-protos.h
index cbe8e34..5f58b34 100644
--- a/gcc/config/alpha/alpha-protos.h
+++ b/gcc/config/alpha/alpha-protos.h
@@ -47,8 +47,7 @@ extern int or_operand PARAMS ((rtx, enum machine_mode));
 extern int mode_width_operand PARAMS ((rtx, enum machine_mode));
 extern int mode_mask_operand PARAMS ((rtx, enum machine_mode));
 extern int mul8_operand PARAMS ((rtx, enum machine_mode));
-extern int fp0_operand PARAMS ((rtx, enum machine_mode));
-extern int reg_or_fp0_operand PARAMS ((rtx, enum machine_mode));
+extern int const0_operand PARAMS ((rtx, enum machine_mode));
 extern int hard_fp_register_operand PARAMS ((rtx, enum machine_mode));
 extern int hard_int_register_operand PARAMS ((rtx, enum machine_mode));
 extern int reg_or_cint_operand PARAMS ((rtx, enum machine_mode));
diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c
index bee3dc1..91cbc12 100644
--- a/gcc/config/alpha/alpha.c
+++ b/gcc/config/alpha/alpha.c
@@ -581,7 +581,7 @@ reg_or_0_operand (op, mode)
       register rtx op;
       enum machine_mode mode;
 {
-  return op == const0_rtx || register_operand (op, mode);
+  return op == CONST0_RTX (mode) || register_operand (op, mode);
 }
 
 /* Return 1 if OP is a constant in the range of 0-63 (for a shift) or
@@ -748,25 +748,14 @@ mul8_operand (op, mode)
 	  && (INTVAL (op) & 7) == 0);
 }
 
-/* Return 1 if OP is the constant zero in floating-point.  */
+/* Return 1 if OP is the zero constant for MODE.  */
 
 int
-fp0_operand (op, mode)
+const0_operand (op, mode)
      register rtx op;
      enum machine_mode mode;
 {
-  return (GET_MODE (op) == mode
-	  && GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode));
-}
-
-/* Return 1 if OP is the floating-point constant zero or a register.  */
-
-int
-reg_or_fp0_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  return fp0_operand (op, mode) || register_operand (op, mode);
+  return op == CONST0_RTX (mode);
 }
 
 /* Return 1 if OP is a hard floating-point register.  */
diff --git a/gcc/config/alpha/alpha.h b/gcc/config/alpha/alpha.h
index 289973a..a969a6c 100644
--- a/gcc/config/alpha/alpha.h
+++ b/gcc/config/alpha/alpha.h
@@ -1919,7 +1919,8 @@ do {						\
 /* Define the codes that are matched by predicates in alpha.c.  */
 
 #define PREDICATE_CODES 						\
-  {"reg_or_0_operand", {SUBREG, REG, CONST_INT}},			\
+  {"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE,		\
+			CONST_VECTOR}},					\
   {"reg_or_6bit_operand", {SUBREG, REG, CONST_INT}},			\
   {"reg_or_8bit_operand", {SUBREG, REG, CONST_INT}},			\
   {"cint8_operand", {CONST_INT}},					\
@@ -1932,14 +1933,13 @@ do {						\
   {"mode_mask_operand", {CONST_INT}},					\
   {"mul8_operand", {CONST_INT}},					\
   {"mode_width_operand", {CONST_INT}},					\
-  {"reg_or_fp0_operand", {SUBREG, REG, CONST_DOUBLE}},			\
   {"alpha_comparison_operator", {EQ, LE, LT, LEU, LTU}},		\
   {"alpha_zero_comparison_operator", {EQ, NE, LE, LT, LEU, LTU}},	\
   {"alpha_swapped_comparison_operator", {EQ, GE, GT, GEU, GTU}},	\
   {"signed_comparison_operator", {EQ, NE, LE, LT, GE, GT}},		\
   {"alpha_fp_comparison_operator", {EQ, LE, LT, UNORDERED}},		\
   {"divmod_operator", {DIV, MOD, UDIV, UMOD}},				\
-  {"fp0_operand", {CONST_DOUBLE}},					\
+  {"const0_operand", {CONST_INT, CONST_DOUBLE, CONST_VECTOR}},		\
   {"current_file_function_operand", {SYMBOL_REF}},			\
   {"direct_call_operand", {SYMBOL_REF}},				\
   {"local_symbolic_operand", {SYMBOL_REF, CONST, LABEL_REF}},		\
diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md
index 85e5f4c..d5d22a2 100644
--- a/gcc/config/alpha/alpha.md
+++ b/gcc/config/alpha/alpha.md
@@ -2096,35 +2096,35 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 (define_insn "abssf2"
   [(set (match_operand:SF 0 "register_operand" "=f")
-	(abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
+	(abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
   "TARGET_FP"
   "cpys $f31,%R1,%0"
   [(set_attr "type" "fcpys")])
 
 (define_insn "*nabssf2"
   [(set (match_operand:SF 0 "register_operand" "=f")
-	(neg:SF (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
+	(neg:SF (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG"))))]
   "TARGET_FP"
   "cpysn $f31,%R1,%0"
   [(set_attr "type" "fadd")])
 
 (define_insn "absdf2"
   [(set (match_operand:DF 0 "register_operand" "=f")
-	(abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
+	(abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
   "TARGET_FP"
   "cpys $f31,%R1,%0"
   [(set_attr "type" "fcpys")])
 
 (define_insn "*nabsdf2"
   [(set (match_operand:DF 0 "register_operand" "=f")
-	(neg:DF (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG"))))]
+	(neg:DF (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG"))))]
   "TARGET_FP"
   "cpysn $f31,%R1,%0"
   [(set_attr "type" "fadd")])
 
 (define_expand "abstf2"
   [(parallel [(set (match_operand:TF 0 "register_operand" "")
-		   (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
+		   (neg:TF (match_operand:TF 1 "reg_or_0_operand" "")))
 	      (use (match_dup 2))])]
   "TARGET_HAS_XFLOATING_LIBS"
 {
@@ -2137,7 +2137,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 (define_insn_and_split "*abstf_internal"
   [(set (match_operand:TF 0 "register_operand" "=r")
-	(abs:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG")))
+	(abs:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
    (use (match_operand:DI 2 "register_operand" "r"))]
   "TARGET_HAS_XFLOATING_LIBS"
   "#"
@@ -2147,21 +2147,21 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 (define_insn "negsf2"
   [(set (match_operand:SF 0 "register_operand" "=f")
-	(neg:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
+	(neg:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
   "TARGET_FP"
   "cpysn %R1,%R1,%0"
   [(set_attr "type" "fadd")])
 
 (define_insn "negdf2"
   [(set (match_operand:DF 0 "register_operand" "=f")
-	(neg:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
+	(neg:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
   "TARGET_FP"
   "cpysn %R1,%R1,%0"
   [(set_attr "type" "fadd")])
 
 (define_expand "negtf2"
   [(parallel [(set (match_operand:TF 0 "register_operand" "")
-		   (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
+		   (neg:TF (match_operand:TF 1 "reg_or_0_operand" "")))
 	      (use (match_dup 2))])]
   "TARGET_HAS_XFLOATING_LIBS"
 {
@@ -2174,7 +2174,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 (define_insn_and_split "*negtf_internal"
   [(set (match_operand:TF 0 "register_operand" "=r")
-	(neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG")))
+	(neg:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
    (use (match_operand:DI 2 "register_operand" "r"))]
   "TARGET_HAS_XFLOATING_LIBS"
   "#"
@@ -2184,8 +2184,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 (define_insn "*addsf_ieee"
   [(set (match_operand:SF 0 "register_operand" "=&f")
-	(plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
-		 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
+	(plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
+		 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
   "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
   "add%,%/ %R1,%R2,%0"
   [(set_attr "type" "fadd")
@@ -2195,8 +2195,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 (define_insn "addsf3"
   [(set (match_operand:SF 0 "register_operand" "=f")
-	(plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
-		 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
+	(plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
+		 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
   "TARGET_FP"
   "add%,%/ %R1,%R2,%0"
   [(set_attr "type" "fadd")
@@ -2206,8 +2206,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 (define_insn "*adddf_ieee"
   [(set (match_operand:DF 0 "register_operand" "=&f")
-	(plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
-		 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
+	(plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
+		 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
   "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
   "add%-%/ %R1,%R2,%0"
   [(set_attr "type" "fadd")
@@ -2217,8 +2217,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 (define_insn "adddf3"
   [(set (match_operand:DF 0 "register_operand" "=f")
-	(plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
-		 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
+	(plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
+		 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
   "TARGET_FP"
   "add%-%/ %R1,%R2,%0"
   [(set_attr "type" "fadd")
@@ -2229,8 +2229,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 (define_insn "*adddf_ext1"
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(plus:DF (float_extend:DF
-		  (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
-		 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
+		  (match_operand:SF 1 "reg_or_0_operand" "fG"))
+		 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
   "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
   "add%-%/ %R1,%R2,%0"
   [(set_attr "type" "fadd")
@@ -2241,9 +2241,9 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 (define_insn "*adddf_ext2"
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(plus:DF (float_extend:DF
-		  (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
+		  (match_operand:SF 1 "reg_or_0_operand" "%fG"))
 		 (float_extend:DF
-		  (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
+		  (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
   "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
   "add%-%/ %R1,%R2,%0"
   [(set_attr "type" "fadd")
@@ -2269,7 +2269,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 (define_insn "*cvtql"
   [(set (match_operand:SI 0 "register_operand" "=f")
-	(unspec:SI [(match_operand:DI 1 "reg_or_fp0_operand" "fG")]
+	(unspec:SI [(match_operand:DI 1 "reg_or_0_operand" "fG")]
 		   UNSPEC_CVTQL))]
   "TARGET_FP"
   "cvtql%/ %R1,%0"
@@ -2279,7 +2279,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 (define_insn_and_split "*fix_truncdfsi_ieee"
   [(set (match_operand:SI 0 "memory_operand" "=m")
-	(subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
+	(subreg:SI (fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")) 0))
    (clobber (match_scratch:DI 2 "=&f"))
    (clobber (match_scratch:SI 3 "=&f"))]
   "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
@@ -2294,7 +2294,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 (define_insn_and_split "*fix_truncdfsi_internal"
   [(set (match_operand:SI 0 "memory_operand" "=m")
-	(subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
+	(subreg:SI (fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")) 0))
    (clobber (match_scratch:DI 2 "=f"))]
   "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
   "#"
@@ -2309,7 +2309,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 (define_insn "*fix_truncdfdi_ieee"
   [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
-	(fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
+	(fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")))]
   "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
   "cvt%-q%/ %R1,%0"
   [(set_attr "type" "fadd")
@@ -2319,7 +2319,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 (define_insn "fix_truncdfdi2"
   [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
-	(fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
+	(fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")))]
   "TARGET_FP"
   "cvt%-q%/ %R1,%0"
   [(set_attr "type" "fadd")
@@ -2332,7 +2332,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 (define_insn_and_split "*fix_truncsfsi_ieee"
   [(set (match_operand:SI 0 "memory_operand" "=m")
 	(subreg:SI (fix:DI (float_extend:DF
-		 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
+		 (match_operand:SF 1 "reg_or_0_operand" "fG"))) 0))
    (clobber (match_scratch:DI 2 "=&f"))
    (clobber (match_scratch:SI 3 "=&f"))]
   "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
@@ -2348,7 +2348,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 (define_insn_and_split "*fix_truncsfsi_internal"
   [(set (match_operand:SI 0 "memory_operand" "=m")
 	(subreg:SI (fix:DI (float_extend:DF
-		 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
+		 (match_operand:SF 1 "reg_or_0_operand" "fG"))) 0))
    (clobber (match_scratch:DI 2 "=f"))]
   "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
   "#"
@@ -2364,7 +2364,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 (define_insn "*fix_truncsfdi_ieee"
   [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
 	(fix:DI (float_extend:DF
-		 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
+		 (match_operand:SF 1 "reg_or_0_operand" "fG"))))]
   "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
   "cvt%-q%/ %R1,%0"
   [(set_attr "type" "fadd")
@@ -2375,7 +2375,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 (define_insn "fix_truncsfdi2"
   [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
 	(fix:DI (float_extend:DF
-		 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
+		 (match_operand:SF 1 "reg_or_0_operand" "fG"))))]
   "TARGET_FP"
   "cvt%-q%/ %R1,%0"
   [(set_attr "type" "fadd")
@@ -2502,7 +2502,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 (define_insn "*truncdfsf2_ieee"
   [(set (match_operand:SF 0 "register_operand" "=&f")
-	(float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
+	(float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
   "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
   "cvt%-%,%/ %R1,%0"
   [(set_attr "type" "fadd")
@@ -2512,7 +2512,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 (define_insn "truncdfsf2"
   [(set (match_operand:SF 0 "register_operand" "=f")
-	(float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
+	(float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
   "TARGET_FP"
   "cvt%-%,%/ %R1,%0"
   [(set_attr "type" "fadd")
@@ -2554,8 +2554,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 (define_insn "*divsf3_ieee"
   [(set (match_operand:SF 0 "register_operand" "=&f")
-	(div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
-		(match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
+	(div:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
+		(match_operand:SF 2 "reg_or_0_operand" "fG")))]
   "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
   "div%,%/ %R1,%R2,%0"
   [(set_attr "type" "fdiv")
@@ -2566,8 +2566,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 (define_insn "divsf3"
   [(set (match_operand:SF 0 "register_operand" "=f")
-	(div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
-		(match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
+	(div:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
+		(match_operand:SF 2 "reg_or_0_operand" "fG")))]
   "TARGET_FP"
   "div%,%/ %R1,%R2,%0"
   [(set_attr "type" "fdiv")
@@ -2578,8 +2578,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 (define_insn "*divdf3_ieee"
   [(set (match_operand:DF 0 "register_operand" "=&f")
-	(div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
-		(match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
+	(div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
+		(match_operand:DF 2 "reg_or_0_operand" "fG")))]
   "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
   "div%-%/ %R1,%R2,%0"
   [(set_attr "type" "fdiv")
@@ -2589,8 +2589,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 (define_insn "divdf3"
   [(set (match_operand:DF 0 "register_operand" "=f")
-	(div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
-		(match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
+	(div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
+		(match_operand:DF 2 "reg_or_0_operand" "fG")))]
   "TARGET_FP"
   "div%-%/ %R1,%R2,%0"
   [(set_attr "type" "fdiv")
@@ -2600,8 +2600,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 (define_insn "*divdf_ext1"
   [(set (match_operand:DF 0 "register_operand" "=f")
-	(div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
-		(match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
+	(div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
+		(match_operand:DF 2 "reg_or_0_operand" "fG")))]
   "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
   "div%-%/ %R1,%R2,%0"
   [(set_attr "type" "fdiv")
@@ -2611,9 +2611,9 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 (define_insn "*divdf_ext2"
   [(set (match_operand:DF 0 "register_operand" "=f")
-	(div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
+	(div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
 		(float_extend:DF
-		 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
+		 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
   "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
   "div%-%/ %R1,%R2,%0"
   [(set_attr "type" "fdiv")
@@ -2623,8 +2623,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 (define_insn "*divdf_ext3"
   [(set (match_operand:DF 0 "register_operand" "=f")
-	(div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
-		(float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
+	(div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
+		(float_extend:DF (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
   "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
   "div%-%/ %R1,%R2,%0"
   [(set_attr "type" "fdiv")
@@ -2641,8 +2641,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 (define_insn "*mulsf3_ieee"
   [(set (match_operand:SF 0 "register_operand" "=&f")
-	(mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
-		 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
+	(mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
+		 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
   "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
   "mul%,%/ %R1,%R2,%0"
   [(set_attr "type" "fmul")
@@ -2652,8 +2652,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 (define_insn "mulsf3"
   [(set (match_operand:SF 0 "register_operand" "=f")
-	(mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
-		 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
+	(mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
+		 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
   "TARGET_FP"
   "mul%,%/ %R1,%R2,%0"
   [(set_attr "type" "fmul")
@@ -2663,8 +2663,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 (define_insn "*muldf3_ieee"
   [(set (match_operand:DF 0 "register_operand" "=&f")
-	(mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
-		 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
+	(mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
+		 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
   "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
   "mul%-%/ %R1,%R2,%0"
   [(set_attr "type" "fmul")
@@ -2674,8 +2674,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 (define_insn "muldf3"
   [(set (match_operand:DF 0 "register_operand" "=f")
-	(mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
-		 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
+	(mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
+		 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
   "TARGET_FP"
   "mul%-%/ %R1,%R2,%0"
   [(set_attr "type" "fmul")
@@ -2686,8 +2686,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 (define_insn "*muldf_ext1"
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(mult:DF (float_extend:DF
-		  (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
-		 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
+		  (match_operand:SF 1 "reg_or_0_operand" "fG"))
+		 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
   "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
   "mul%-%/ %R1,%R2,%0"
   [(set_attr "type" "fmul")
@@ -2698,9 +2698,9 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 (define_insn "*muldf_ext2"
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(mult:DF (float_extend:DF
-		  (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
+		  (match_operand:SF 1 "reg_or_0_operand" "%fG"))
 		 (float_extend:DF
-		  (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
+		  (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
   "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
   "mul%-%/ %R1,%R2,%0"
   [(set_attr "type" "fmul")
@@ -2717,8 +2717,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 (define_insn "*subsf3_ieee"
   [(set (match_operand:SF 0 "register_operand" "=&f")
-	(minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
-		  (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
+	(minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
+		  (match_operand:SF 2 "reg_or_0_operand" "fG")))]
   "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
   "sub%,%/ %R1,%R2,%0"
   [(set_attr "type" "fadd")
@@ -2728,8 +2728,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 (define_insn "subsf3"
   [(set (match_operand:SF 0 "register_operand" "=f")
-	(minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
-		  (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
+	(minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
+		  (match_operand:SF 2 "reg_or_0_operand" "fG")))]
   "TARGET_FP"
   "sub%,%/ %R1,%R2,%0"
   [(set_attr "type" "fadd")
@@ -2739,8 +2739,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 (define_insn "*subdf3_ieee"
   [(set (match_operand:DF 0 "register_operand" "=&f")
-	(minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
-		  (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
+	(minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
+		  (match_operand:DF 2 "reg_or_0_operand" "fG")))]
   "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
   "sub%-%/ %R1,%R2,%0"
   [(set_attr "type" "fadd")
@@ -2750,8 +2750,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 (define_insn "subdf3"
   [(set (match_operand:DF 0 "register_operand" "=f")
-	(minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
-		  (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
+	(minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
+		  (match_operand:DF 2 "reg_or_0_operand" "fG")))]
   "TARGET_FP"
   "sub%-%/ %R1,%R2,%0"
   [(set_attr "type" "fadd")
@@ -2762,8 +2762,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 (define_insn "*subdf_ext1"
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(minus:DF (float_extend:DF
-		   (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
-		  (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
+		   (match_operand:SF 1 "reg_or_0_operand" "fG"))
+		  (match_operand:DF 2 "reg_or_0_operand" "fG")))]
   "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
   "sub%-%/ %R1,%R2,%0"
   [(set_attr "type" "fadd")
@@ -2773,9 +2773,9 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 (define_insn "*subdf_ext2"
   [(set (match_operand:DF 0 "register_operand" "=f")
-	(minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
+	(minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
 		  (float_extend:DF
-		   (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
+		   (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
   "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
   "sub%-%/ %R1,%R2,%0"
   [(set_attr "type" "fadd")
@@ -2786,9 +2786,9 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 (define_insn "*subdf_ext3"
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(minus:DF (float_extend:DF
-		   (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
+		   (match_operand:SF 1 "reg_or_0_operand" "fG"))
 		  (float_extend:DF
-		   (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
+		   (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
   "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
   "sub%-%/ %R1,%R2,%0"
   [(set_attr "type" "fadd")
@@ -2805,7 +2805,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 (define_insn "*sqrtsf2_ieee"
   [(set (match_operand:SF 0 "register_operand" "=&f")
-	(sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
+	(sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
   "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
   "sqrt%,%/ %R1,%0"
   [(set_attr "type" "fsqrt")
@@ -2816,7 +2816,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 (define_insn "sqrtsf2"
   [(set (match_operand:SF 0 "register_operand" "=f")
-	(sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
+	(sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
   "TARGET_FP && TARGET_FIX"
   "sqrt%,%/ %R1,%0"
   [(set_attr "type" "fsqrt")
@@ -2827,7 +2827,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 (define_insn "*sqrtdf2_ieee"
   [(set (match_operand:DF 0 "register_operand" "=&f")
-	(sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
+	(sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
   "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
   "sqrt%-%/ %R1,%0"
   [(set_attr "type" "fsqrt")
@@ -2837,7 +2837,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 (define_insn "sqrtdf2"
   [(set (match_operand:DF 0 "register_operand" "=f")
-	(sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
+	(sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
   "TARGET_FP && TARGET_FIX"
   "sqrt%-%/ %1,%0"
   [(set_attr "type" "fsqrt")
@@ -3397,8 +3397,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 (define_insn "*cmpdf_ieee"
   [(set (match_operand:DF 0 "register_operand" "=&f")
 	(match_operator:DF 1 "alpha_fp_comparison_operator"
-			   [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
-			    (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
+			   [(match_operand:DF 2 "reg_or_0_operand" "fG")
+			    (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
   "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
   "cmp%-%C1%/ %R2,%R3,%0"
   [(set_attr "type" "fadd")
@@ -3408,8 +3408,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 (define_insn "*cmpdf_internal"
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(match_operator:DF 1 "alpha_fp_comparison_operator"
-			   [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
-			    (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
+			   [(match_operand:DF 2 "reg_or_0_operand" "fG")
+			    (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
   "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
   "cmp%-%C1%/ %R2,%R3,%0"
   [(set_attr "type" "fadd")
@@ -3420,8 +3420,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
   [(set (match_operand:DF 0 "register_operand" "=&f")
 	(match_operator:DF 1 "alpha_fp_comparison_operator"
 			   [(float_extend:DF
-			     (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
-			    (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
+			     (match_operand:SF 2 "reg_or_0_operand" "fG"))
+			    (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
   "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
   "cmp%-%C1%/ %R2,%R3,%0"
   [(set_attr "type" "fadd")
@@ -3432,8 +3432,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(match_operator:DF 1 "alpha_fp_comparison_operator"
 			   [(float_extend:DF
-			     (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
-			    (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
+			     (match_operand:SF 2 "reg_or_0_operand" "fG"))
+			    (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
   "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
   "cmp%-%C1%/ %R2,%R3,%0"
   [(set_attr "type" "fadd")
@@ -3443,9 +3443,9 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 (define_insn "*cmpdf_ieee_ext2"
   [(set (match_operand:DF 0 "register_operand" "=&f")
 	(match_operator:DF 1 "alpha_fp_comparison_operator"
-			   [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
+			   [(match_operand:DF 2 "reg_or_0_operand" "fG")
 			    (float_extend:DF
-			     (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
+			     (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
   "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
   "cmp%-%C1%/ %R2,%R3,%0"
   [(set_attr "type" "fadd")
@@ -3455,9 +3455,9 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 (define_insn "*cmpdf_ext2"
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(match_operator:DF 1 "alpha_fp_comparison_operator"
-			   [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
+			   [(match_operand:DF 2 "reg_or_0_operand" "fG")
 			    (float_extend:DF
-			     (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
+			     (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
   "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
   "cmp%-%C1%/ %R2,%R3,%0"
   [(set_attr "type" "fadd")
@@ -3468,9 +3468,9 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
   [(set (match_operand:DF 0 "register_operand" "=&f")
 	(match_operator:DF 1 "alpha_fp_comparison_operator"
 			   [(float_extend:DF
-			     (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
+			     (match_operand:SF 2 "reg_or_0_operand" "fG"))
 			    (float_extend:DF
-			     (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
+			     (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
   "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
   "cmp%-%C1%/ %R2,%R3,%0"
   [(set_attr "type" "fadd")
@@ -3481,9 +3481,9 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(match_operator:DF 1 "alpha_fp_comparison_operator"
 			   [(float_extend:DF
-			     (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
+			     (match_operand:SF 2 "reg_or_0_operand" "fG"))
 			    (float_extend:DF
-			     (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
+			     (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
   "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
   "cmp%-%C1%/ %R2,%R3,%0"
   [(set_attr "type" "fadd")
@@ -3494,10 +3494,10 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
   [(set (match_operand:DF 0 "register_operand" "=f,f")
 	(if_then_else:DF
 	 (match_operator 3 "signed_comparison_operator"
-			 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
-			  (match_operand:DF 2 "fp0_operand" "G,G")])
-	 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
-	 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
+			 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
+			  (match_operand:DF 2 "const0_operand" "G,G")])
+	 (match_operand:DF 1 "reg_or_0_operand" "fG,0")
+	 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
   "TARGET_FP"
   "@
    fcmov%C3 %R4,%R1,%0
@@ -3508,10 +3508,10 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
   [(set (match_operand:SF 0 "register_operand" "=f,f")
 	(if_then_else:SF
 	 (match_operator 3 "signed_comparison_operator"
-			 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
-			  (match_operand:DF 2 "fp0_operand" "G,G")])
-	 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
-	 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
+			 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
+			  (match_operand:DF 2 "const0_operand" "G,G")])
+	 (match_operand:SF 1 "reg_or_0_operand" "fG,0")
+	 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
   "TARGET_FP"
   "@
    fcmov%C3 %R4,%R1,%0
@@ -3522,10 +3522,10 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
   [(set (match_operand:DF 0 "register_operand" "=f,f")
 	(if_then_else:DF
 	 (match_operator 3 "signed_comparison_operator"
-			 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
-			  (match_operand:DF 2 "fp0_operand" "G,G")])
-	 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
-	 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
+			 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
+			  (match_operand:DF 2 "const0_operand" "G,G")])
+	 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
+	 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
   "TARGET_FP"
   "@
    fcmov%C3 %R4,%R1,%0
@@ -3537,10 +3537,10 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 	(if_then_else:DF
 	 (match_operator 3 "signed_comparison_operator"
 			 [(float_extend:DF
-			   (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
-			  (match_operand:DF 2 "fp0_operand" "G,G")])
-	 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
-	 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
+			   (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
+			  (match_operand:DF 2 "const0_operand" "G,G")])
+	 (match_operand:DF 1 "reg_or_0_operand" "fG,0")
+	 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
   "TARGET_FP"
   "@
    fcmov%C3 %R4,%R1,%0
@@ -3552,10 +3552,10 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 	(if_then_else:SF
 	 (match_operator 3 "signed_comparison_operator"
 			 [(float_extend:DF
-			   (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
-			  (match_operand:DF 2 "fp0_operand" "G,G")])
-	 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
-	 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
+			   (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
+			  (match_operand:DF 2 "const0_operand" "G,G")])
+	 (match_operand:SF 1 "reg_or_0_operand" "fG,0")
+	 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
   "TARGET_FP"
   "@
    fcmov%C3 %R4,%R1,%0
@@ -3567,10 +3567,10 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 	(if_then_else:DF
 	 (match_operator 3 "signed_comparison_operator"
 			 [(float_extend:DF
-			   (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
-			  (match_operand:DF 2 "fp0_operand" "G,G")])
-	 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
-	 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
+			   (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
+			  (match_operand:DF 2 "const0_operand" "G,G")])
+	 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
+	 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
   "TARGET_FP"
   "@
    fcmov%C3 %R4,%R1,%0
@@ -3579,8 +3579,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 (define_expand "maxdf3"
   [(set (match_dup 3)
-	(le:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
-	       (match_operand:DF 2 "reg_or_fp0_operand" "")))
+	(le:DF (match_operand:DF 1 "reg_or_0_operand" "")
+	       (match_operand:DF 2 "reg_or_0_operand" "")))
    (set (match_operand:DF 0 "register_operand" "")
 	(if_then_else:DF (eq (match_dup 3) (match_dup 4))
 			 (match_dup 1) (match_dup 2)))]
@@ -3592,8 +3592,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 (define_expand "mindf3"
   [(set (match_dup 3)
-	(lt:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
-	       (match_operand:DF 2 "reg_or_fp0_operand" "")))
+	(lt:DF (match_operand:DF 1 "reg_or_0_operand" "")
+	       (match_operand:DF 2 "reg_or_0_operand" "")))
    (set (match_operand:DF 0 "register_operand" "")
 	(if_then_else:DF (ne (match_dup 3) (match_dup 4))
 			 (match_dup 1) (match_dup 2)))]
@@ -3605,8 +3605,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 (define_expand "maxsf3"
   [(set (match_dup 3)
-	(le:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
-	       (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
+	(le:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))
+	       (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" ""))))
    (set (match_operand:SF 0 "register_operand" "")
 	(if_then_else:SF (eq (match_dup 3) (match_dup 4))
 			 (match_dup 1) (match_dup 2)))]
@@ -3618,8 +3618,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 (define_expand "minsf3"
   [(set (match_dup 3)
-	(lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
-	       (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
+	(lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))
+	       (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" ""))))
    (set (match_operand:SF 0 "register_operand" "")
 	(if_then_else:SF (ne (match_dup 3) (match_dup 4))
 		      (match_dup 1) (match_dup 2)))]
@@ -3633,8 +3633,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
   [(set (pc)
 	(if_then_else
 	 (match_operator 1 "signed_comparison_operator"
-			 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
-			  (match_operand:DF 3 "fp0_operand" "G")])
+			 [(match_operand:DF 2 "reg_or_0_operand" "fG")
+			  (match_operand:DF 3 "const0_operand" "G")])
 	 (label_ref (match_operand 0 "" ""))
 	 (pc)))]
   "TARGET_FP"
@@ -3646,8 +3646,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 	(if_then_else
 	 (match_operator 1 "signed_comparison_operator"
 			 [(float_extend:DF
-			   (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
-			  (match_operand:DF 3 "fp0_operand" "G")])
+			   (match_operand:SF 2 "reg_or_0_operand" "fG"))
+			  (match_operand:DF 3 "const0_operand" "G")])
 	 (label_ref (match_operand 0 "" ""))
 	 (pc)))]
   "TARGET_FP"
@@ -3658,8 +3658,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 ;; and compares.
 
 (define_expand "cmpdf"
-  [(set (cc0) (compare (match_operand:DF 0 "reg_or_fp0_operand" "")
-		       (match_operand:DF 1 "reg_or_fp0_operand" "")))]
+  [(set (cc0) (compare (match_operand:DF 0 "reg_or_0_operand" "")
+		       (match_operand:DF 1 "reg_or_0_operand" "")))]
   "TARGET_FP"
 {
   alpha_compare.op0 = operands[0];
@@ -4904,7 +4904,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 	(match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
   "TARGET_FPREGS && ! TARGET_FIX
    && (register_operand (operands[0], SFmode)
-       || reg_or_fp0_operand (operands[1], SFmode))"
+       || reg_or_0_operand (operands[1], SFmode))"
   "@
    cpys %R1,%R1,%0
    ld%, %0,%1
@@ -4919,7 +4919,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 	(match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
   "TARGET_FPREGS && TARGET_FIX
    && (register_operand (operands[0], SFmode)
-       || reg_or_fp0_operand (operands[1], SFmode))"
+       || reg_or_0_operand (operands[1], SFmode))"
   "@
    cpys %R1,%R1,%0
    ld%, %0,%1
@@ -4936,7 +4936,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 	(match_operand:SF 1 "input_operand" "rG,m,r"))]
   "! TARGET_FPREGS
    && (register_operand (operands[0], SFmode)
-       || reg_or_fp0_operand (operands[1], SFmode))"
+       || reg_or_0_operand (operands[1], SFmode))"
   "@
    bis $31,%r1,%0
    ldl %0,%1
@@ -4948,7 +4948,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 	(match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
   "TARGET_FPREGS && ! TARGET_FIX
    && (register_operand (operands[0], DFmode)
-       || reg_or_fp0_operand (operands[1], DFmode))"
+       || reg_or_0_operand (operands[1], DFmode))"
   "@
    cpys %R1,%R1,%0
    ld%- %0,%1
@@ -4963,7 +4963,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 	(match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
   "TARGET_FPREGS && TARGET_FIX
    && (register_operand (operands[0], DFmode)
-       || reg_or_fp0_operand (operands[1], DFmode))"
+       || reg_or_0_operand (operands[1], DFmode))"
   "@
    cpys %R1,%R1,%0
    ld%- %0,%1
@@ -4980,7 +4980,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 	(match_operand:DF 1 "input_operand" "rG,m,r"))]
   "! TARGET_FPREGS
    && (register_operand (operands[0], DFmode)
-       || reg_or_fp0_operand (operands[1], DFmode))"
+       || reg_or_0_operand (operands[1], DFmode))"
   "@
    bis $31,%r1,%0
    ldq %0,%1
@@ -4994,7 +4994,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
   [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
 	(match_operand:TF 1 "input_operand" "roG,rG"))]
   "register_operand (operands[0], TFmode)
-   || reg_or_fp0_operand (operands[1], TFmode)"
+   || reg_or_0_operand (operands[1], TFmode)"
   "#"
   "reload_completed"
   [(set (match_dup 0) (match_dup 2))
@@ -5015,7 +5015,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
   ""
 {
   if (GET_CODE (operands[0]) == MEM
-      && ! reg_or_fp0_operand (operands[1], SFmode))
+      && ! reg_or_0_operand (operands[1], SFmode))
     operands[1] = force_reg (SFmode, operands[1]);
 })
 
@@ -5025,7 +5025,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
   ""
 {
   if (GET_CODE (operands[0]) == MEM
-      && ! reg_or_fp0_operand (operands[1], DFmode))
+      && ! reg_or_0_operand (operands[1], DFmode))
     operands[1] = force_reg (DFmode, operands[1]);
 })
 
@@ -5035,7 +5035,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
   ""
 {
   if (GET_CODE (operands[0]) == MEM
-      && ! reg_or_fp0_operand (operands[1], TFmode))
+      && ! reg_or_0_operand (operands[1], TFmode))
     operands[1] = force_reg (TFmode, operands[1]);
 })