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| author | Andre Simoes Dias Vieira <andre.simoesdiasvieira@arm.com> | 2020-03-20 09:18:18 +0000 |
|---|---|---|
| committer | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2020-03-20 09:22:47 +0000 |
| commit | 719c864225e28c33a0737a331a772781ce8e6591 (patch) | |
| tree | 2629bebd41444c0506da2e70425c5cc5af570db6 /gcc | |
| parent | 005f6fc59e5fceb658e11f153402711ee7f12c1a (diff) | |
| download | gcc-719c864225e28c33a0737a331a772781ce8e6591.zip gcc-719c864225e28c33a0737a331a772781ce8e6591.tar.gz gcc-719c864225e28c33a0737a331a772781ce8e6591.tar.bz2 | |
gcc, Arm: Revert changes to {get,set}_fpscr
MVE made changes to {get,set}_fpscr to enable the compiler to optimize
unneccesary gets and sets when using these for intrinsics that use and/or write
the carry bit. However, these actually get and set the full FPSCR register and
are used by fp env intrinsics to modify the fp context. So MVE should not be
using these.
gcc/ChangeLog:
2020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/arm/unspecs.md (UNSPEC_GET_FPSCR): Rename this to ...
(VUNSPEC_GET_FPSCR): ... this, and move it to vunspec.
* config/arm/vfp.md: (get_fpscr, set_fpscr): Revert to old patterns.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/arm/unspecs.md | 2 | ||||
| -rw-r--r-- | gcc/config/arm/vfp.md | 7 |
3 files changed, 10 insertions, 5 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ccda62f..ded73b3 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com> + * config/arm/unspecs.md (UNSPEC_GET_FPSCR): Rename this to ... + (VUNSPEC_GET_FPSCR): ... this, and move it to vunspec. + * config/arm/vfp.md: (get_fpscr, set_fpscr): Revert to old patterns. + +2020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com> + * config/arm/mve.md (mve_mov<mode>): Fix R->R case. 2020-03-20 Jakub Jelinek <jakub@redhat.com> diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index e76609f..f0b1f46 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -170,7 +170,6 @@ UNSPEC_TORC ; Used by the intrinsic form of the iWMMXt TORC instruction. UNSPEC_TORVSC ; Used by the intrinsic form of the iWMMXt TORVSC instruction. UNSPEC_TEXTRC ; Used by the intrinsic form of the iWMMXt TEXTRC instruction. - UNSPEC_GET_FPSCR ; Represent fetch of FPSCR content. ]) @@ -217,6 +216,7 @@ VUNSPEC_SLX ; Represent a store-register-release-exclusive. VUNSPEC_LDA ; Represent a store-register-acquire. VUNSPEC_STL ; Represent a store-register-release. + VUNSPEC_GET_FPSCR ; Represent fetch of FPSCR content. VUNSPEC_SET_FPSCR ; Represent assign of FPSCR content. VUNSPEC_PROBE_STACK_RANGE ; Represent stack range probing. VUNSPEC_CDP ; Represent the coprocessor cdp instruction. diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index eb6ae7b..dfb1031 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -2096,9 +2096,8 @@ ;; Write Floating-point Status and Control Register. (define_insn "set_fpscr" - [(set (reg:SI VFPCC_REGNUM) - (unspec_volatile:SI - [(match_operand:SI 0 "register_operand" "r")] VUNSPEC_SET_FPSCR))] + [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] + VUNSPEC_SET_FPSCR)] "TARGET_VFP_BASE" "mcr\\tp10, 7, %0, cr1, cr0, 0\\t @SET_FPSCR" [(set_attr "type" "mrs")]) @@ -2106,7 +2105,7 @@ ;; Read Floating-point Status and Control Register. (define_insn "get_fpscr" [(set (match_operand:SI 0 "register_operand" "=r") - (unspec:SI [(reg:SI VFPCC_REGNUM)] UNSPEC_GET_FPSCR))] + (unspec_volatile:SI [(const_int 0)] VUNSPEC_GET_FPSCR))] "TARGET_VFP_BASE" "mrc\\tp10, 7, %0, cr1, cr0, 0\\t @GET_FPSCR" [(set_attr "type" "mrs")]) |