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| author | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2017-03-16 10:03:11 +0000 |
|---|---|---|
| committer | Kyrylo Tkachov <ktkachov@gcc.gnu.org> | 2017-03-16 10:03:11 +0000 |
| commit | 6d06971da12fb1b8730257abbd49447760baed8d (patch) | |
| tree | e1cbe23b379d4b53d399e49fc76d2dc8d557e8dc /gcc | |
| parent | f5a3ad8ae5a51a9418d0fa3482198ec4f0a89a44 (diff) | |
| download | gcc-6d06971da12fb1b8730257abbd49447760baed8d.zip gcc-6d06971da12fb1b8730257abbd49447760baed8d.tar.gz gcc-6d06971da12fb1b8730257abbd49447760baed8d.tar.bz2 | |
[AArch64] Use 'x' constraint for vector HFmode multiplication by indexed element instructions
* config/aarch64/iterators.md (h_con): Return "x" for V4HF and V8HF.
* config/aarch64/aarch64-simd.md (*aarch64_fma4_elt_from_dup<mode>):
Use h_con constraint for operand 1.
(*aarch64_fnma4_elt_from_dup<mode>): Likewise.
(*aarch64_mulx_elt_from_dup<mode>): Likewise for operand 2.
From-SVN: r246189
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 6 | ||||
| -rw-r--r-- | gcc/config/aarch64/iterators.md | 4 |
3 files changed, 13 insertions, 5 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 82ab3d7..e2e1015 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2017-03-16 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * config/aarch64/iterators.md (h_con): Return "x" for V4HF and V8HF. + * config/aarch64/aarch64-simd.md (*aarch64_fma4_elt_from_dup<mode>): + Use h_con constraint for operand 1. + (*aarch64_fnma4_elt_from_dup<mode>): Likewise. + (*aarch64_mulx_elt_from_dup<mode>): Likewise for operand 2. + 2017-03-15 Jeff Law <law@redhat.com> PR tree-optimization/71437 diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 7ad3a76..8a3a551 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1647,7 +1647,7 @@ [(set (match_operand:VMUL 0 "register_operand" "=w") (fma:VMUL (vec_duplicate:VMUL - (match_operand:<VEL> 1 "register_operand" "w")) + (match_operand:<VEL> 1 "register_operand" "<h_con>")) (match_operand:VMUL 2 "register_operand" "w") (match_operand:VMUL 3 "register_operand" "0")))] "TARGET_SIMD" @@ -1726,7 +1726,7 @@ (neg:VMUL (match_operand:VMUL 2 "register_operand" "w")) (vec_duplicate:VMUL - (match_operand:<VEL> 1 "register_operand" "w")) + (match_operand:<VEL> 1 "register_operand" "<h_con>")) (match_operand:VMUL 3 "register_operand" "0")))] "TARGET_SIMD" "fmls\t%0.<Vtype>, %2.<Vtype>, %1.<Vetype>[0]" @@ -3178,7 +3178,7 @@ (unspec:VHSDF [(match_operand:VHSDF 1 "register_operand" "w") (vec_duplicate:VHSDF - (match_operand:<VEL> 2 "register_operand" "w"))] + (match_operand:<VEL> 2 "register_operand" "<h_con>"))] UNSPEC_FMULX))] "TARGET_SIMD" "fmulx\t%0.<Vtype>, %1.<Vtype>, %2.<Vetype>[0]"; diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 1ddf6ad..43be7fd 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -749,11 +749,11 @@ (DF "to_128") (V2DF "to_64")]) ;; For certain vector-by-element multiplication instructions we must -;; constrain the HI cases to use only V0-V15. This is covered by +;; constrain the 16-bit cases to use only V0-V15. This is covered by ;; the 'x' constraint. All other modes may use the 'w' constraint. (define_mode_attr h_con [(V2SI "w") (V4SI "w") (V4HI "x") (V8HI "x") - (V4HF "w") (V8HF "w") + (V4HF "x") (V8HF "x") (V2SF "w") (V4SF "w") (V2DF "w") (DF "w")]) |