[2/4] aarch64: Convert UABDL2 and SABDL2 patterns to standard RTL codes

Similar to the previous patch for UABDL and SABDL, this patch covers the *2 versions that vec_select the high half
of its input to do the asbsdiff and extend. A define_expand is added for the intrinsic to create the "select-high-half" RTX the pattern expects.

Bootstrapped and tested on aarch64-none-linux-gnu.

gcc/ChangeLog:

	* config/aarch64/aarch64-simd.md (aarch64_<sur>abdl2<mode>): Rename to...
	(aarch64_<su>abdl2<mode>_insn): ... This.  Use RTL codes instead of unspec.
	(aarch64_<su>abdl2<mode>): New define_expand.
	* config/aarch64/aarch64.md (UNSPEC_SABDL2, UNSPEC_UABDL2): Delete.
	* config/aarch64/iterators.md (ABDL2): Delete.
	(sur): Remove handling of UNSPEC_SABDL2 and UNSPEC_UABDL2.

3 files changed, 33 insertions, 11 deletions

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index b46eb1d..6c62868 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -914,16 +914,44 @@
   [(set_attr "type" "neon_abd<q>")]
 )
 
-(define_insn "aarch64_<sur>abdl2<mode>"
+(define_insn "aarch64_<su>abdl2<mode>_insn"
   [(set (match_operand:<VDBLW> 0 "register_operand" "=w")
-	(unspec:<VDBLW> [(match_operand:VQW 1 "register_operand" "w")
-			 (match_operand:VQW 2 "register_operand" "w")]
-	ABDL2))]
+	(zero_extend:<VDBLW>
+	  (minus:<VHALF>
+	    (USMAX:<VHALF>
+	      (vec_select:<VHALF>
+		(match_operand:VQW 1 "register_operand" "w")
+		(match_operand:VQW 3 "vect_par_cnst_hi_half" ""))
+	      (vec_select:<VHALF>
+		(match_operand:VQW 2 "register_operand" "w")
+		(match_dup 3)))
+	    (<max_opp>:<VHALF>
+	      (vec_select:<VHALF>
+		(match_dup 1)
+		(match_dup 3))
+	      (vec_select:<VHALF>
+		(match_dup 2)
+		(match_dup 3))))))]
+
   "TARGET_SIMD"
-  "<sur>abdl2\t%0.<Vwtype>, %1.<Vtype>, %2.<Vtype>"
+  "<su>abdl2\t%0.<Vwtype>, %1.<Vtype>, %2.<Vtype>"
   [(set_attr "type" "neon_abd<q>")]
 )
 
+(define_expand "aarch64_<su>abdl2<mode>"
+  [(match_operand:<VDBLW> 0 "register_operand")
+   (USMAX:VQW
+     (match_operand:VQW 1 "register_operand")
+     (match_operand:VQW 2 "register_operand"))]
+  "TARGET_SIMD"
+  {
+    rtx hi = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
+    emit_insn (gen_aarch64_<su>abdl2<mode>_insn (operands[0], operands[1],
+						 operands[2], hi));
+    DONE;
+  }
+)
+
 (define_insn "aarch64_<sur>abal<mode>"
   [(set (match_operand:<VWIDE> 0 "register_operand" "=w")
 	(unspec:<VWIDE> [(match_operand:VD_BHSI 2 "register_operand" "w")
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index a1f35f2..1b2bdf5 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -206,7 +206,6 @@
     UNSPEC_RBIT
     UNSPEC_SABAL
     UNSPEC_SABAL2
-    UNSPEC_SABDL2
     UNSPEC_SADALP
     UNSPEC_SCVTF
     UNSPEC_SETMEM
@@ -229,7 +228,6 @@
     UNSPEC_TLSLE48
     UNSPEC_UABAL
     UNSPEC_UABAL2
-    UNSPEC_UABDL2
     UNSPEC_UADALP
     UNSPEC_UCVTF
     UNSPEC_USHL_2S
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index b7d67a6..bd4415d 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -2573,9 +2573,6 @@
 ;; The unspec codes for the SABAL2, UABAL2 AdvancedSIMD instructions.
 (define_int_iterator ABAL2 [UNSPEC_SABAL2 UNSPEC_UABAL2])
 
-;; The unspec codes for the SABDL2, UABDL2 AdvancedSIMD instructions.
-(define_int_iterator ABDL2 [UNSPEC_SABDL2 UNSPEC_UABDL2])
-
 ;; The unspec codes for the SADALP, UADALP AdvancedSIMD instructions.
 (define_int_iterator ADALP [UNSPEC_SADALP UNSPEC_UADALP])
 
@@ -3359,7 +3356,6 @@
 		      (UNSPEC_ADDHN "") (UNSPEC_RADDHN "r")
 		      (UNSPEC_SABAL "s") (UNSPEC_UABAL "u")
 		      (UNSPEC_SABAL2 "s") (UNSPEC_UABAL2 "u")
-		      (UNSPEC_SABDL2 "s") (UNSPEC_UABDL2 "u")
 		      (UNSPEC_SADALP "s") (UNSPEC_UADALP "u")
 		      (UNSPEC_SUBHN "") (UNSPEC_RSUBHN "r")
 		      (UNSPEC_USQADD "us") (UNSPEC_SUQADD "su")