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| author | Richard Henderson <rth@cygnus.com> | 1998-11-04 20:04:04 -0800 |
|---|---|---|
| committer | Richard Henderson <rth@gcc.gnu.org> | 1998-11-04 20:04:04 -0800 |
| commit | 6c61c2bba11355ba204a14ea196235d5eeeb1e1e (patch) | |
| tree | 193ccdf22fa935d00929bbdd597d7d4974aeadf1 /gcc | |
| parent | 8f5d685581c011dd907c692b63b4e340a6de9b8d (diff) | |
| download | gcc-6c61c2bba11355ba204a14ea196235d5eeeb1e1e.zip gcc-6c61c2bba11355ba204a14ea196235d5eeeb1e1e.tar.gz gcc-6c61c2bba11355ba204a14ea196235d5eeeb1e1e.tar.bz2 | |
alpha.md (addsi3, subsi3): No new temporaries once cse is no longer expected.
* alpha.md (addsi3, subsi3): No new temporaries once cse is
no longer expected.
From-SVN: r23537
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/alpha/alpha.md | 30 |
2 files changed, 27 insertions, 8 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f851757..818cff0 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +Thu Nov 5 04:03:06 1998 Richard Henderson <rth@cygnus.com> + + * alpha.md (addsi3, subsi3): No new temporaries once cse is + no longer expected. + Thu Nov 5 03:29:19 1998 Richard Henderson <rth@cygnus.com> * alpha.md (addsi3, subsi3): Expand to a DImode temporary so as diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index c88497e..8ae03e6 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -427,10 +427,17 @@ "" " { - rtx tmp = gen_reg_rtx (DImode); - emit_insn (gen_adddi3 (tmp, gen_lowpart (DImode, operands[1]), - gen_lowpart (DImode, operands[2]))); - emit_move_insn (operands[0], gen_lowpart (SImode, tmp)); + rtx op1 = gen_lowpart (DImode, operands[1]); + rtx op2 = gen_lowpart (DImode, operands[2]); + + if (! cse_not_expected) + { + rtx tmp = gen_reg_rtx (DImode); + emit_insn (gen_adddi3 (tmp, op1, op2)); + emit_move_insn (operands[0], gen_lowpart (SImode, tmp)); + } + else + emit_insn (gen_adddi3 (gen_lowpart (DImode, operands[0]), op1, op2)); DONE; } ") @@ -714,10 +721,17 @@ "" " { - rtx tmp = gen_reg_rtx (DImode); - emit_insn (gen_subdi3 (tmp, gen_lowpart (DImode, operands[1]), - gen_lowpart (DImode, operands[2]))); - emit_move_insn (operands[0], gen_lowpart (SImode, tmp)); + rtx op1 = gen_lowpart (DImode, operands[1]); + rtx op2 = gen_lowpart (DImode, operands[2]); + + if (! cse_not_expected) + { + rtx tmp = gen_reg_rtx (DImode); + emit_insn (gen_subdi3 (tmp, op1, op2)); + emit_move_insn (operands[0], gen_lowpart (SImode, tmp)); + } + else + emit_insn (gen_subdi3 (gen_lowpart (DImode, operands[0]), op1, op2)); DONE; } ") |