RISC-V: Add VLS mask modes mov patterns

This patterns fix these following ICE FAILs when running the whole GCC testsuite
with enabling scalable vector by default.

All of these FAILs are fixed:
FAIL: c-c++-common/opaque-vector.c  -std=c++14 (internal compiler error: in emit_move_multi_word, at expr.cc:4079)
FAIL: c-c++-common/opaque-vector.c  -std=c++14 (test for excess errors)
FAIL: c-c++-common/opaque-vector.c  -std=c++17 (internal compiler error: in emit_move_multi_word, at expr.cc:4079)
FAIL: c-c++-common/opaque-vector.c  -std=c++17 (test for excess errors)
FAIL: c-c++-common/opaque-vector.c  -std=c++20 (internal compiler error: in emit_move_multi_word, at expr.cc:4079)
FAIL: c-c++-common/opaque-vector.c  -std=c++20 (test for excess errors)
FAIL: c-c++-common/opaque-vector.c  -std=c++98 (internal compiler error: in emit_move_multi_word, at expr.cc:4079)
FAIL: c-c++-common/opaque-vector.c  -std=c++98 (test for excess errors)
FAIL: c-c++-common/pr105998.c  -std=c++14 (internal compiler error: in emit_move_multi_word, at expr.cc:4079)
FAIL: c-c++-common/pr105998.c  -std=c++14 (test for excess errors)
FAIL: c-c++-common/pr105998.c  -std=c++17 (internal compiler error: in emit_move_multi_word, at expr.cc:4079)
FAIL: c-c++-common/pr105998.c  -std=c++17 (test for excess errors)
FAIL: c-c++-common/pr105998.c  -std=c++20 (internal compiler error: in emit_move_multi_word, at expr.cc:4079)
FAIL: c-c++-common/pr105998.c  -std=c++20 (test for excess errors)
FAIL: c-c++-common/pr105998.c  -std=c++98 (internal compiler error: in emit_move_multi_word, at expr.cc:4079)
FAIL: c-c++-common/pr105998.c  -std=c++98 (test for excess errors)
FAIL: c-c++-common/vector-scalar.c  -std=c++14 (internal compiler error: in emit_move_multi_word, at expr.cc:4079)
FAIL: c-c++-common/vector-scalar.c  -std=c++14 (test for excess errors)
FAIL: c-c++-common/vector-scalar.c  -std=c++17 (internal compiler error: in emit_move_multi_word, at expr.cc:4079)
FAIL: c-c++-common/vector-scalar.c  -std=c++17 (test for excess errors)
FAIL: c-c++-common/vector-scalar.c  -std=c++20 (internal compiler error: in emit_move_multi_word, at expr.cc:4079)
FAIL: c-c++-common/vector-scalar.c  -std=c++20 (test for excess errors)
FAIL: c-c++-common/vector-scalar.c  -std=c++98 (internal compiler error: in emit_move_multi_word, at expr.cc:4079)
FAIL: c-c++-common/vector-scalar.c  -std=c++98 (test for excess errors)
FAIL: g++.dg/ext/vector36.C  -std=gnu++14 (internal compiler error: in emit_move_multi_word, at expr.cc:4079)
FAIL: g++.dg/ext/vector36.C  -std=gnu++14 (test for excess errors)
FAIL: g++.dg/ext/vector36.C  -std=gnu++17 (internal compiler error: in emit_move_multi_word, at expr.cc:4079)
FAIL: g++.dg/ext/vector36.C  -std=gnu++17 (test for excess errors)
FAIL: g++.dg/ext/vector36.C  -std=gnu++20 (internal compiler error: in emit_move_multi_word, at expr.cc:4079)
FAIL: g++.dg/ext/vector36.C  -std=gnu++20 (test for excess errors)
FAIL: g++.dg/ext/vector36.C  -std=gnu++98 (internal compiler error: in emit_move_multi_word, at expr.cc:4079)
FAIL: g++.dg/ext/vector36.C  -std=gnu++98 (test for excess errors)
FAIL: g++.dg/pr58950.C  -std=gnu++14 (internal compiler error: in emit_move_multi_word, at expr.cc:4079)
FAIL: g++.dg/pr58950.C  -std=gnu++14 (test for excess errors)
FAIL: g++.dg/pr58950.C  -std=gnu++17 (internal compiler error: in emit_move_multi_word, at expr.cc:4079)
FAIL: g++.dg/pr58950.C  -std=gnu++17 (test for excess errors)
FAIL: g++.dg/pr58950.C  -std=gnu++20 (internal compiler error: in emit_move_multi_word, at expr.cc:4079)
FAIL: g++.dg/pr58950.C  -std=gnu++20 (test for excess errors)
FAIL: g++.dg/pr58950.C  -std=gnu++98 (internal compiler error: in emit_move_multi_word, at expr.cc:4079)
FAIL: g++.dg/pr58950.C  -std=gnu++98 (test for excess errors)
FAIL: c-c++-common/torture/builtin-shufflevector-2.c   -O0  (internal compiler error: in emit_move_multi_word, at expr.cc:4079)
FAIL: c-c++-common/torture/vector-compare-2.c   -O0  (internal compiler error: in emit_move_multi_word, at expr.cc:4079)
FAIL: c-c++-common/torture/vector-compare-2.c   -O0  (test for excess errors)
FAIL: g++.dg/torture/pr104450.C   -O0  (internal compiler error: in emit_move_multi_word, at expr.cc:4079)
FAIL: g++.dg/torture/pr104450.C   -O0  (test for excess errors)

FAIL: gcc.dg/analyzer/pr96713.c (internal compiler error: in emit_move_multi_word, at expr.cc:4079)
FAIL: gcc.dg/analyzer/pr96713.c (test for excess errors)
FAIL: c-c++-common/opaque-vector.c  -Wc++-compat  (internal compiler error: in emit_move_multi_word, at expr.cc:4079)
FAIL: c-c++-common/opaque-vector.c  -Wc++-compat  (test for excess errors)
FAIL: c-c++-common/pr105998.c  -Wc++-compat  (internal compiler error: in emit_move_multi_word, at expr.cc:4079)
FAIL: c-c++-common/pr105998.c  -Wc++-compat  (test for excess errors)
FAIL: c-c++-common/vector-scalar.c  -Wc++-compat  (internal compiler error: in emit_move_multi_word, at expr.cc:4079)
FAIL: c-c++-common/vector-scalar.c  -Wc++-compat  (test for excess errors)
FAIL: gcc.dg/pr100239.c (internal compiler error: in emit_move_multi_word, at expr.cc:4079)
FAIL: gcc.dg/pr100239.c (test for excess errors)
FAIL: gcc.dg/pr97238.c (internal compiler error: in emit_move_multi_word, at expr.cc:4079)
FAIL: gcc.dg/pr97238.c (test for excess errors)
FAIL: c-c++-common/torture/builtin-shufflevector-2.c   -O0  (internal compiler error: in emit_move_multi_word, at expr.cc:4079)
FAIL: gcc.dg/torture/pr70310.c   -O0  (internal compiler error: in emit_move_multi_word, at expr.cc:4079)
FAIL: gcc.dg/torture/pr70310.c   -O0  (test for excess errors)

gcc/ChangeLog:

	* config/riscv/autovec-vls.md: Add VLS mask modes mov patterns.
	* config/riscv/riscv.md: Ditto.
	* config/riscv/vector-iterators.md: Ditto.
	* config/riscv/vector.md: Ditto.

4 files changed, 76 insertions, 37 deletions

diff --git a/gcc/config/riscv/autovec-vls.md b/gcc/config/riscv/autovec-vls.md
index 31b6c4a..d208b41 100644
--- a/gcc/config/riscv/autovec-vls.md
+++ b/gcc/config/riscv/autovec-vls.md
@@ -128,8 +128,12 @@
     {
       emit_move_insn (operands[2], gen_int_mode (GET_MODE_NUNITS (<VLS_AVL_REG:MODE>mode),
 						 Pmode));
+      unsigned insn_flags
+        = GET_MODE_CLASS (<VLS_AVL_REG:MODE>mode) == MODE_VECTOR_BOOL
+						     ? riscv_vector::UNARY_MASK_OP
+						     : riscv_vector::UNARY_OP;
       riscv_vector::emit_nonvlmax_insn (code_for_pred_mov (<VLS_AVL_REG:MODE>mode),
-					 riscv_vector::UNARY_OP, operands, operands[2]);
+					insn_flags, operands, operands[2]);
     }
   DONE;
 }
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 14dc21b..b630b51 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -239,7 +239,8 @@
   V1DI,V2DI,V4DI,V8DI,V16DI,V32DI,V64DI,V128DI,V256DI,V512DI,
   V1HF,V2HF,V4HF,V8HF,V16HF,V32HF,V64HF,V128HF,V256HF,V512HF,V1024HF,V2048HF,
   V1SF,V2SF,V4SF,V8SF,V16SF,V32SF,V64SF,V128SF,V256SF,V512SF,V1024SF,
-  V1DF,V2DF,V4DF,V8DF,V16DF,V32DF,V64DF,V128DF,V256DF,V512DF"
+  V1DF,V2DF,V4DF,V8DF,V16DF,V32DF,V64DF,V128DF,V256DF,V512DF,
+  V1BI,V2BI,V4BI,V8BI,V16BI,V32BI,V64BI,V128BI,V256BI,V512BI,V1024BI,V2048BI,V4096BI"
   (const_string "unknown"))
 
 ;; True if the main data type is twice the size of a word.
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index caef815..7d9fcd2 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -795,6 +795,23 @@
   (RVVMF64BI "TARGET_MIN_VLEN > 32") RVVMF32BI RVVMF16BI RVVMF8BI RVVMF4BI RVVMF2BI RVVM1BI
 ])
 
+(define_mode_iterator VB_VLS [
+  (RVVMF64BI "TARGET_MIN_VLEN > 32") RVVMF32BI RVVMF16BI RVVMF8BI RVVMF4BI RVVMF2BI RVVM1BI
+  (V1BI "TARGET_VECTOR_VLS")
+  (V2BI "TARGET_VECTOR_VLS")
+  (V4BI "TARGET_VECTOR_VLS")
+  (V8BI "TARGET_VECTOR_VLS")
+  (V16BI "TARGET_VECTOR_VLS")
+  (V32BI "TARGET_VECTOR_VLS")
+  (V64BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
+  (V128BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
+  (V256BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
+  (V512BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
+  (V1024BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
+  (V2048BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
+  (V4096BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
+])
+
 (define_mode_iterator VWEXTI [
   RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32")
 
@@ -2444,7 +2461,13 @@
   (V2DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
   (V4DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
   (V8DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64")
-  (V16DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")])
+  (V16DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
+
+  (V1BI "TARGET_VECTOR_VLS")
+  (V2BI "TARGET_VECTOR_VLS")
+  (V4BI "TARGET_VECTOR_VLS")
+  (V8BI "TARGET_VECTOR_VLS")
+  (V16BI "TARGET_VECTOR_VLS")])
 
 ;; VLS modes that has NUNITS >= 32.
 (define_mode_iterator VLS_AVL_REG [
@@ -2491,7 +2514,16 @@
   (V64DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 512")
   (V128DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024")
   (V256DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048")
-  (V512DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096")])
+  (V512DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096")
+
+  (V32BI "TARGET_VECTOR_VLS")
+  (V64BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
+  (V128BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
+  (V256BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
+  (V512BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
+  (V1024BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
+  (V2048BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
+  (V4096BI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")])
 
 (define_mode_iterator VLSI [
   (V1QI "TARGET_VECTOR_VLS")
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index fc985ff..7c086d4 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -93,7 +93,8 @@
 			  RVVM2x4QI,RVVM1x4QI,RVVMF2x4QI,RVVMF4x4QI,RVVMF8x4QI,\
 			  RVVM2x3QI,RVVM1x3QI,RVVMF2x3QI,RVVMF4x3QI,RVVMF8x3QI,\
 			  RVVM4x2QI,RVVM2x2QI,RVVM1x2QI,RVVMF2x2QI,RVVMF4x2QI,RVVMF8x2QI,\
-			  V1QI,V2QI,V4QI,V8QI,V16QI,V32QI,V64QI,V128QI,V256QI,V512QI,V1024QI,V2048QI,V4096QI")
+			  V1QI,V2QI,V4QI,V8QI,V16QI,V32QI,V64QI,V128QI,V256QI,V512QI,V1024QI,V2048QI,V4096QI,\
+			  V1BI,V2BI,V4BI,V8BI,V16BI,V32BI,V64BI,V128BI,V256BI,V512BI,V1024BI,V2048BI,V4096BI")
 	 (const_int 8)
 	 (eq_attr "mode" "RVVM8HI,RVVM4HI,RVVM2HI,RVVM1HI,RVVMF2HI,RVVMF4HI,\
 			  RVVM1x8HI,RVVMF2x8HI,RVVMF4x8HI,\
@@ -330,19 +331,19 @@
 	 (eq_attr "mode" "RVVM1x2DF") (symbol_ref "riscv_vector::LMUL_1")
 
 	 ;; VLS modes.
-	 (eq_attr "mode" "V1QI") (symbol_ref "riscv_vector::get_vlmul(E_V1QImode)")
-	 (eq_attr "mode" "V2QI") (symbol_ref "riscv_vector::get_vlmul(E_V2QImode)")
-	 (eq_attr "mode" "V4QI") (symbol_ref "riscv_vector::get_vlmul(E_V4QImode)")
-	 (eq_attr "mode" "V8QI") (symbol_ref "riscv_vector::get_vlmul(E_V8QImode)")
-	 (eq_attr "mode" "V16QI") (symbol_ref "riscv_vector::get_vlmul(E_V16QImode)")
-	 (eq_attr "mode" "V32QI") (symbol_ref "riscv_vector::get_vlmul(E_V32QImode)")
-	 (eq_attr "mode" "V64QI") (symbol_ref "riscv_vector::get_vlmul(E_V64QImode)")
-	 (eq_attr "mode" "V128QI") (symbol_ref "riscv_vector::get_vlmul(E_V128QImode)")
-	 (eq_attr "mode" "V256QI") (symbol_ref "riscv_vector::get_vlmul(E_V256QImode)")
-	 (eq_attr "mode" "V512QI") (symbol_ref "riscv_vector::get_vlmul(E_V512QImode)")
-	 (eq_attr "mode" "V1024QI") (symbol_ref "riscv_vector::get_vlmul(E_V1024QImode)")
-	 (eq_attr "mode" "V2048QI") (symbol_ref "riscv_vector::get_vlmul(E_V2048QImode)")
-	 (eq_attr "mode" "V4096QI") (symbol_ref "riscv_vector::get_vlmul(E_V4096QImode)")
+	 (eq_attr "mode" "V1QI,V1BI") (symbol_ref "riscv_vector::get_vlmul(E_V1QImode)")
+	 (eq_attr "mode" "V2QI,V2BI") (symbol_ref "riscv_vector::get_vlmul(E_V2QImode)")
+	 (eq_attr "mode" "V4QI,V4BI") (symbol_ref "riscv_vector::get_vlmul(E_V4QImode)")
+	 (eq_attr "mode" "V8QI,V8BI") (symbol_ref "riscv_vector::get_vlmul(E_V8QImode)")
+	 (eq_attr "mode" "V16QI,V16BI") (symbol_ref "riscv_vector::get_vlmul(E_V16QImode)")
+	 (eq_attr "mode" "V32QI,V32BI") (symbol_ref "riscv_vector::get_vlmul(E_V32QImode)")
+	 (eq_attr "mode" "V64QI,V64BI") (symbol_ref "riscv_vector::get_vlmul(E_V64QImode)")
+	 (eq_attr "mode" "V128QI,V128BI") (symbol_ref "riscv_vector::get_vlmul(E_V128QImode)")
+	 (eq_attr "mode" "V256QI,V256BI") (symbol_ref "riscv_vector::get_vlmul(E_V256QImode)")
+	 (eq_attr "mode" "V512QI,V512BI") (symbol_ref "riscv_vector::get_vlmul(E_V512QImode)")
+	 (eq_attr "mode" "V1024QI,V1024BI") (symbol_ref "riscv_vector::get_vlmul(E_V1024QImode)")
+	 (eq_attr "mode" "V2048QI,V2048BI") (symbol_ref "riscv_vector::get_vlmul(E_V2048QImode)")
+	 (eq_attr "mode" "V4096QI,V4096BI") (symbol_ref "riscv_vector::get_vlmul(E_V4096QImode)")
 	 (eq_attr "mode" "V1HI") (symbol_ref "riscv_vector::get_vlmul(E_V1HImode)")
 	 (eq_attr "mode" "V2HI") (symbol_ref "riscv_vector::get_vlmul(E_V2HImode)")
 	 (eq_attr "mode" "V4HI") (symbol_ref "riscv_vector::get_vlmul(E_V4HImode)")
@@ -607,19 +608,19 @@
 	 (eq_attr "mode" "RVVM1x2DF") (const_int 64)
 
 	 ;; VLS modes.
-	 (eq_attr "mode" "V1QI") (symbol_ref "riscv_vector::get_ratio(E_V1QImode)")
-	 (eq_attr "mode" "V2QI") (symbol_ref "riscv_vector::get_ratio(E_V2QImode)")
-	 (eq_attr "mode" "V4QI") (symbol_ref "riscv_vector::get_ratio(E_V4QImode)")
-	 (eq_attr "mode" "V8QI") (symbol_ref "riscv_vector::get_ratio(E_V8QImode)")
-	 (eq_attr "mode" "V16QI") (symbol_ref "riscv_vector::get_ratio(E_V16QImode)")
-	 (eq_attr "mode" "V32QI") (symbol_ref "riscv_vector::get_ratio(E_V32QImode)")
-	 (eq_attr "mode" "V64QI") (symbol_ref "riscv_vector::get_ratio(E_V64QImode)")
-	 (eq_attr "mode" "V128QI") (symbol_ref "riscv_vector::get_ratio(E_V128QImode)")
-	 (eq_attr "mode" "V256QI") (symbol_ref "riscv_vector::get_ratio(E_V256QImode)")
-	 (eq_attr "mode" "V512QI") (symbol_ref "riscv_vector::get_ratio(E_V512QImode)")
-	 (eq_attr "mode" "V1024QI") (symbol_ref "riscv_vector::get_ratio(E_V1024QImode)")
-	 (eq_attr "mode" "V2048QI") (symbol_ref "riscv_vector::get_ratio(E_V2048QImode)")
-	 (eq_attr "mode" "V4096QI") (symbol_ref "riscv_vector::get_ratio(E_V4096QImode)")
+	 (eq_attr "mode" "V1QI,V1BI") (symbol_ref "riscv_vector::get_ratio(E_V1QImode)")
+	 (eq_attr "mode" "V2QI,V2BI") (symbol_ref "riscv_vector::get_ratio(E_V2QImode)")
+	 (eq_attr "mode" "V4QI,V4BI") (symbol_ref "riscv_vector::get_ratio(E_V4QImode)")
+	 (eq_attr "mode" "V8QI,V8BI") (symbol_ref "riscv_vector::get_ratio(E_V8QImode)")
+	 (eq_attr "mode" "V16QI,V16BI") (symbol_ref "riscv_vector::get_ratio(E_V16QImode)")
+	 (eq_attr "mode" "V32QI,V32BI") (symbol_ref "riscv_vector::get_ratio(E_V32QImode)")
+	 (eq_attr "mode" "V64QI,V64BI") (symbol_ref "riscv_vector::get_ratio(E_V64QImode)")
+	 (eq_attr "mode" "V128QI,V128BI") (symbol_ref "riscv_vector::get_ratio(E_V128QImode)")
+	 (eq_attr "mode" "V256QI,V256BI") (symbol_ref "riscv_vector::get_ratio(E_V256QImode)")
+	 (eq_attr "mode" "V512QI,V512BI") (symbol_ref "riscv_vector::get_ratio(E_V512QImode)")
+	 (eq_attr "mode" "V1024QI,V1024BI") (symbol_ref "riscv_vector::get_ratio(E_V1024QImode)")
+	 (eq_attr "mode" "V2048QI,V2048BI") (symbol_ref "riscv_vector::get_ratio(E_V2048QImode)")
+	 (eq_attr "mode" "V4096QI,V4096BI") (symbol_ref "riscv_vector::get_ratio(E_V4096QImode)")
 	 (eq_attr "mode" "V1HI") (symbol_ref "riscv_vector::get_ratio(E_V1HImode)")
 	 (eq_attr "mode" "V2HI") (symbol_ref "riscv_vector::get_ratio(E_V2HImode)")
 	 (eq_attr "mode" "V4HI") (symbol_ref "riscv_vector::get_ratio(E_V4HImode)")
@@ -802,6 +803,7 @@
 ;; The avl type value.
 (define_attr "avl_type" ""
   (cond [(eq_attr "mode" "V1QI,V2QI,V4QI,V8QI,V16QI,V32QI,V64QI,V128QI,V256QI,V512QI,V1024QI,V2048QI,V4096QI,
+			  V1BI,V2BI,V4BI,V8BI,V16BI,V32BI,V64BI,V128BI,V256BI,V512BI,V1024BI,V2048BI,V4096BI,
 			  V1HI,V2HI,V4HI,V8HI,V16HI,V32HI,V64HI,V128HI,V256HI,V512HI,V1024HI,V2048HI,
 			  V1SI,V2SI,V4SI,V8SI,V16SI,V32SI,V64SI,V128SI,V256SI,V512SI,V1024SI,
 			  V1DI,V2DI,V4DI,V8DI,V16DI,V32DI,V64DI,V128DI,V256DI,V512DI,
@@ -1540,16 +1542,16 @@
 ;; constraint alternative 3 match vmclr.m.
 ;; constraint alternative 4 match vmset.m.
 (define_insn_and_split "@pred_mov<mode>"
-  [(set (match_operand:VB 0 "nonimmediate_operand"               "=vr,   m,  vr,  vr,  vr")
-	(if_then_else:VB
-	  (unspec:VB
-	    [(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1, Wc1, Wc1, Wc1, Wc1")
+  [(set (match_operand:VB_VLS 0 "nonimmediate_operand"               "=vr,   m,  vr,  vr,  vr")
+	(if_then_else:VB_VLS
+	  (unspec:VB_VLS
+	    [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1, Wc1, Wc1, Wc1, Wc1")
 	     (match_operand 4 "vector_length_operand"            " rK,  rK,  rK,  rK,  rK")
 	     (match_operand 5 "const_int_operand"                "  i,   i,   i,   i,   i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	  (match_operand:VB 3 "vector_move_operand"              "  m,  vr,  vr, Wc0, Wc1")
-	  (match_operand:VB 2 "vector_undef_operand"             " vu,  vu,  vu,  vu,  vu")))]
+	  (match_operand:VB_VLS 3 "vector_move_operand"              "  m,  vr,  vr, Wc0, Wc1")
+	  (match_operand:VB_VLS 2 "vector_undef_operand"             " vu,  vu,  vu,  vu,  vu")))]
   "TARGET_VECTOR"
   "@
    vlm.v\t%0,%3