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| author | James Greenhalgh <james.greenhalgh@arm.com> | 2013-09-06 13:42:12 +0000 |
|---|---|---|
| committer | James Greenhalgh <jgreenhalgh@gcc.gnu.org> | 2013-09-06 13:42:12 +0000 |
| commit | 6a24a83ec41d47f1644689de4dddb6ccff12958a (patch) | |
| tree | 60997d3499d38056ac30aa897c878fbc7ee7f00f /gcc | |
| parent | b86923f0cd190c2be56575e634a7c0d16f6df134 (diff) | |
| download | gcc-6a24a83ec41d47f1644689de4dddb6ccff12958a.zip gcc-6a24a83ec41d47f1644689de4dddb6ccff12958a.tar.gz gcc-6a24a83ec41d47f1644689de4dddb6ccff12958a.tar.bz2 | |
[Patch AArch64] Fix types for some multiply instructions.
gcc/
* config/aarch64/aarch64.md
(*madd<mode>): Fix type attribute.
(*maddsi_uxtw): Likewise.
(*msub<mode>): Likewise.
(*msubsi_uxtw): Likewise.
(<su_optab>maddsidi4): Likewise.
(<su_optab>msubsidi4): Likewise.
From-SVN: r202330
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 10 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 12 |
2 files changed, 16 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6df6ca4..5ca9632 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,15 @@ 2013-09-06 James Greenhalgh <james.greenhalgh@arm.com> + * config/aarch64/aarch64.md + (*madd<mode>): Fix type attribute. + (*maddsi_uxtw): Likewise. + (*msub<mode>): Likewise. + (*msubsi_uxtw): Likewise. + (<su_optab>maddsidi4): Likewise. + (<su_optab>msubsidi4): Likewise. + +2013-09-06 James Greenhalgh <james.greenhalgh@arm.com> + * config/arm/types.md: Split fdiv<sd> as fsqrt<sd>, fdiv<sd>. * config/arm/arm.md (core_cycles): Remove fdiv. * config/arm/vfp.md: diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index ded37ef..e28764d 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -2281,7 +2281,7 @@ "" "madd\\t%<w>0, %<w>1, %<w>2, %<w>3" [(set_attr "v8type" "madd") - (set_attr "type" "mul") + (set_attr "type" "mla") (set_attr "mode" "<MODE>")] ) @@ -2295,7 +2295,7 @@ "" "madd\\t%w0, %w1, %w2, %w3" [(set_attr "v8type" "madd") - (set_attr "type" "mul") + (set_attr "type" "mla") (set_attr "mode" "SI")] ) @@ -2308,7 +2308,7 @@ "" "msub\\t%<w>0, %<w>1, %<w>2, %<w>3" [(set_attr "v8type" "madd") - (set_attr "type" "mul") + (set_attr "type" "mla") (set_attr "mode" "<MODE>")] ) @@ -2323,7 +2323,7 @@ "" "msub\\t%w0, %w1, %w2, %w3" [(set_attr "v8type" "madd") - (set_attr "type" "mul") + (set_attr "type" "mla") (set_attr "mode" "SI")] ) @@ -2373,7 +2373,7 @@ "" "<su>maddl\\t%0, %w1, %w2, %3" [(set_attr "v8type" "maddl") - (set_attr "type" "mul") + (set_attr "type" "<su>mlal") (set_attr "mode" "DI")] ) @@ -2387,7 +2387,7 @@ "" "<su>msubl\\t%0, %w1, %w2, %3" [(set_attr "v8type" "maddl") - (set_attr "type" "mul") + (set_attr "type" "<su>mlal") (set_attr "mode" "DI")] ) |