diff options
| author | Geng Qi <gengqi@linux.alibaba.com> | 2021-09-27 19:37:45 +0800 |
|---|---|---|
| committer | Jim Wilson <jimw@sifive.com> | 2021-09-28 16:31:49 -0700 |
| commit | 68c081bb437d7383481bb75e1f79975f63dc7661 (patch) | |
| tree | 3a9c75cd198a8ef71071871d1268104101e810bb /gcc | |
| parent | daa762f01d8cf932484b7df122a5e872439bc92c (diff) | |
| download | gcc-68c081bb437d7383481bb75e1f79975f63dc7661.zip gcc-68c081bb437d7383481bb75e1f79975f63dc7661.tar.gz gcc-68c081bb437d7383481bb75e1f79975f63dc7661.tar.bz2 | |
RISC-V: Pattern name fix mul*3_highpart -> smul*3_highpart.
No known code changes, just fixes an inconsistency that was noticed.
gcc/
* config/riscv/riscv.md (mulv<mode>4): Call gen_smul<mode>3_highpart.
(<u>mulditi3): Call <su>muldi3_highpart.
(<u>muldi3_highpart): Rename to <su>muldi3_highpart.
(<u>mulsidi3): Call <su>mulsi3_highpart.
(<u>mulsi3_highpart): Rename to <su>mulsi3_highpart.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/riscv/riscv.md | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index f88877f..98364f0 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -802,7 +802,7 @@ rtx hp = gen_reg_rtx (<MODE>mode); rtx lp = gen_reg_rtx (<MODE>mode); - emit_insn (gen_mul<mode>3_highpart (hp, operands[1], operands[2])); + emit_insn (gen_smul<mode>3_highpart (hp, operands[1], operands[2])); emit_insn (gen_mul<mode>3 (operands[0], operands[1], operands[2])); emit_insn (gen_ashr<mode>3 (lp, operands[0], GEN_INT (BITS_PER_WORD - 1))); @@ -899,14 +899,14 @@ emit_insn (gen_muldi3 (low, operands[1], operands[2])); rtx high = gen_reg_rtx (DImode); - emit_insn (gen_<u>muldi3_highpart (high, operands[1], operands[2])); + emit_insn (gen_<su>muldi3_highpart (high, operands[1], operands[2])); emit_move_insn (gen_lowpart (DImode, operands[0]), low); emit_move_insn (gen_highpart (DImode, operands[0]), high); DONE; }) -(define_insn "<u>muldi3_highpart" +(define_insn "<su>muldi3_highpart" [(set (match_operand:DI 0 "register_operand" "=r") (truncate:DI (lshiftrt:TI @@ -961,13 +961,13 @@ { rtx temp = gen_reg_rtx (SImode); emit_insn (gen_mulsi3 (temp, operands[1], operands[2])); - emit_insn (gen_<u>mulsi3_highpart (riscv_subword (operands[0], true), + emit_insn (gen_<su>mulsi3_highpart (riscv_subword (operands[0], true), operands[1], operands[2])); emit_insn (gen_movsi (riscv_subword (operands[0], false), temp)); DONE; }) -(define_insn "<u>mulsi3_highpart" +(define_insn "<su>mulsi3_highpart" [(set (match_operand:SI 0 "register_operand" "=r") (truncate:SI (lshiftrt:DI |