Merge commit '02c031088ac0bbf716aec52e027d615b7a5a572b^' into HEAD

278 files changed, 18868 insertions, 538 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a4c26b4..bc11164 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,107 @@
+2022-12-19  Jason Merrill  <jason@redhat.com>
+
+	* sort.cc: Disable -Wconditionally-supported in
+	CHECKING_P code.
+
+2022-12-19  Jason Merrill  <jason@redhat.com>
+
+	PR c++/64867
+	* configure.ac (strict_warn): Add -Wconditionally-supported.
+	* configure: Regenerate.
+
+2022-12-19  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/108164
+	* tree-vect-loop-manip.cc (vect_update_ivs_after_vectorizer):
+	Perform vect_step_op_add update in the appropriate type.
+
+2022-12-19  Richard Earnshaw  <rearnsha@arm.com>
+
+	* config/arm/arm-c.cc (__ARM_FEATURE_CLZ): Fix definition of
+	preprocessor macro when target has CLZ in another ISA.
+
+2022-12-19  Ju-Zhe Zhong  <juzhe.zhong@rivai.ai>
+
+	* config/riscv/vector.md: Remove vste.
+
+2022-12-19  Ju-Zhe Zhong  <juzhe.zhong@rivai.ai>
+
+	* config.gcc: Add riscv-vsetvl.o.
+	* config/riscv/riscv-passes.def (INSERT_PASS_BEFORE): Add VSETVL PASS
+	location.
+	* config/riscv/riscv-protos.h (make_pass_vsetvl): New function.
+	(enum avl_type): New enum.
+	(get_ta): New function.
+	(get_ma): Ditto.
+	(get_avl_type): Ditto.
+	(calculate_ratio): Ditto.
+	(enum tail_policy): New enum.
+	(enum mask_policy): Ditto.
+	* config/riscv/riscv-v.cc (calculate_ratio): New function.
+	(emit_pred_op): change the VLMAX mov codgen.
+	(get_ta): New function.
+	(get_ma): Ditto.
+	(enum tail_policy): Change enum.
+	(get_prefer_tail_policy): New function.
+	(enum mask_policy): Change enum.
+	(get_prefer_mask_policy): New function.
+	* config/riscv/t-riscv: Add riscv-vsetvl.o
+	* config/riscv/vector.md: Adjust attribute and pattern for VSETVL
+	PASS.
+	(@vlmax_avl<mode>): Ditto.
+	(@vsetvl<mode>_no_side_effects): Delete.
+	(vsetvl_vtype_change_only): New MD pattern.
+	(@vsetvl_discard_result<mode>): Ditto.
+	* config/riscv/riscv-vsetvl.cc: New file.
+	* config/riscv/riscv-vsetvl.h: New file.
+
+2022-12-19  Ju-Zhe Zhong  <juzhe.zhong@rivai.ai>
+
+	* config/riscv/riscv-vector-switch.def (ENTRY): Correct attributes.
+
+2022-12-19  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/108140
+	* config/aarch64/aarch64-builtins.cc
+	(aarch64_expand_builtin_data_intrinsic): Handle NULL target.
+
+2022-12-19  Jakub Jelinek  <jakub@redhat.com>
+
+	* config/gnu-user.h (LIBHWASAN_EARLY_SPEC): Add libhwasan_preinit.o
+	to link spec if not -shared.
+
+2022-12-19  Ju-Zhe Zhong  <juzhe.zhong@rivai.ai>
+
+	* config/riscv/riscv-v.cc (emit_vlmax_vsetvl): Pass through VLMUL enum
+	instead of machine mode.
+	* config/riscv/riscv-vector-builtins-bases.cc: Ditto.
+	* config/riscv/riscv.cc (riscv_print_operand): Print LMUL by enum vlmul
+	instead of machine mode.
+
+2022-12-19  Jiufu Guo  <guojiufu@linux.ibm.com>
+
+	PR target/106708
+	* config/rs6000/rs6000.cc (rs6000_emit_set_long_const): Add using
+	"li; x?oris" to build constant.
+
+2022-12-19  liuhongt  <hongtao.liu@intel.com>
+
+	PR target/55522
+	* config/i386/gnu-user-common.h (GNU_USER_TARGET_MATHFILE_SPEC):
+	Don't add crtfastmath.o for -shared.
+	* doc/invoke.texi (-shared): Add related documentation.
+
+2022-12-18  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
+
+	* config.gcc: Determine Solaris minor version.
+	Obsolete *-*-solaris2.11.[0-3]*.
+	* doc/install.texi (Specific, *-*-solaris2*): Document it.
+
+2022-12-17  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	* config/rs6000/rs6000-logue.cc (rs6000_output_function_epilogue):
+	Handle GNU Rust for the tbtab lang field.
+
 2022-12-16  John David Anglin  <danglin@gcc.gnu.org>
 
 	* config/pa/pa.cc (pa_option_override): Disable -fstack-protector.
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index ee0b666..142f05d 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20221217
+20221220
diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog
index 3670dcc..da43a25 100644
--- a/gcc/c-family/ChangeLog
+++ b/gcc/c-family/ChangeLog
@@ -1,3 +1,8 @@
+2022-12-19  Marek Polacek  <polacek@redhat.com>
+
+	PR c/98487
+	* c-format.cc (check_function_format): Use get_attribute_name.
+
 2022-12-16  Qing Zhao  <qing.zhao@oracle.com>
 
 	* c.opt (Wstrict-flex-arrays): New option.
diff --git a/gcc/c-family/c-format.cc b/gcc/c-family/c-format.cc
index 01adea4..08643c5 100644
--- a/gcc/c-family/c-format.cc
+++ b/gcc/c-family/c-format.cc
@@ -1215,7 +1215,7 @@ check_function_format (const_tree fn, tree attrs, int nargs,
 	      for (c = TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl));
 		   c;
 		   c = TREE_CHAIN (c))
-		if (is_attribute_p ("format", TREE_PURPOSE (c))
+		if (is_attribute_p ("format", get_attribute_name (c))
 		    && (decode_format_type (IDENTIFIER_POINTER
 					    (TREE_VALUE (TREE_VALUE (c))))
 			== info.format_type))
diff --git a/gcc/c/ChangeLog b/gcc/c/ChangeLog
index 20dbbe3..62e484f 100644
--- a/gcc/c/ChangeLog
+++ b/gcc/c/ChangeLog
@@ -1,3 +1,9 @@
+2022-12-19  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c/108043
+	* c-parser.cc (c_parser_postfix_expression_after_paren_type): Diagnose
+	compound literals with function type.
+
 2022-12-07  Joseph Myers  <joseph@codesourcery.com>
 
 	* c-decl.cc (declspecs_add_type, declspecs_add_scspec): Check for
diff --git a/gcc/c/c-parser.cc b/gcc/c/c-parser.cc
index 1bbb39f..7d6960f 100644
--- a/gcc/c/c-parser.cc
+++ b/gcc/c/c-parser.cc
@@ -10924,6 +10924,11 @@ c_parser_postfix_expression_after_paren_type (c_parser *parser,
       error_at (type_loc, "compound literal has variable size");
       type = error_mark_node;
     }
+  else if (TREE_CODE (type) == FUNCTION_TYPE)
+    {
+      error_at (type_loc, "compound literal has function type");
+      type = error_mark_node;
+    }
   if (constexpr_p && type != error_mark_node)
     {
       tree type_no_array = strip_array_types (type);
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 531592c..dba19e1 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -257,14 +257,25 @@ target_type_format_char='@'
 xm_file=
 md_file=
 
+# Determine Solaris minor version
+case ${target}:`uname -v` in
+  # Only do this on Solaris.  Illumos uses illumos-* instead.
+  *-*-solaris2.11*:11.*)
+    # Restrict to native configurations.
+    if test x$host = x$target; then
+      uname_version="`uname -v`"
+      # Prepend dot as needed below.
+      target_min=".`expr "$uname_version" : '11\.\([0-9]*\)'`"
+    fi
+    ;;
+esac
+
 # Obsolete configurations.
-case ${target} in
-  *)
-  ;;
-  obsoleted-target \
+case ${target}${target_min} in
+    *-*-solaris2.11.[0-3]*		\
  )
     if test "x$enable_obsolete" != xyes; then
-      echo "*** Configuration ${target} is obsolete." >&2
+      echo "*** Configuration ${target}${target_min} is obsolete." >&2
       echo "*** Specify --enable-obsolete to build it anyway." >&2
       echo "*** Support will be REMOVED in the next major release of GCC," >&2
       echo "*** unless a maintainer comes forward." >&2
@@ -529,7 +540,7 @@ pru-*-*)
 	;;
 riscv*)
 	cpu_type=riscv
-	extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o riscv-shorten-memrefs.o riscv-selftests.o riscv-v.o"
+	extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o riscv-shorten-memrefs.o riscv-selftests.o riscv-v.o riscv-vsetvl.o"
 	extra_objs="${extra_objs} riscv-vector-builtins.o riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
 	d_target_objs="riscv-d.o"
 	extra_headers="riscv_vector.h"
diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
index b533082..5c9f727 100644
--- a/gcc/config/aarch64/aarch64-builtins.cc
+++ b/gcc/config/aarch64/aarch64-builtins.cc
@@ -2648,7 +2648,7 @@ static rtx
 aarch64_expand_builtin_data_intrinsic (unsigned int fcode, tree exp, rtx target)
 {
   expand_operand ops[2];
-  machine_mode mode = GET_MODE (target);
+  machine_mode mode = TYPE_MODE (TREE_TYPE (exp));
   create_output_operand (&ops[0], target, mode);
   create_input_operand (&ops[1], expand_normal (CALL_EXPR_ARG (exp, 0)), mode);
   enum insn_code icode;
diff --git a/gcc/config/arm/arm-c.cc b/gcc/config/arm/arm-c.cc
index 86c56bf..202898f 100644
--- a/gcc/config/arm/arm-c.cc
+++ b/gcc/config/arm/arm-c.cc
@@ -238,8 +238,12 @@ arm_cpu_builtins (struct cpp_reader* pfile)
     builtin_define_with_int_value ("__ARM_FEATURE_LDREX",
 				   TARGET_ARM_FEATURE_LDREX);
 
+  /* ACLE says that __ARM_FEATURE_CLZ is defined if the hardware
+     supports it; it's also clear that this doesn't mean the current
+     ISA, so we define this even when compiling for Thumb1 if the
+     target supports CLZ in A32.  */
   def_or_undef_macro (pfile, "__ARM_FEATURE_CLZ",
-		      ((TARGET_ARM_ARCH >= 5 && !TARGET_THUMB)
+		      ((TARGET_ARM_ARCH >= 5 && arm_arch_notm)
 		       || TARGET_ARM_ARCH_ISA_THUMB >=2));
 
   def_or_undef_macro (pfile, "__ARM_FEATURE_NUMERIC_MAXMIN",
diff --git a/gcc/config/gnu-user.h b/gcc/config/gnu-user.h
index 857c0e0..edb3aa6 100644
--- a/gcc/config/gnu-user.h
+++ b/gcc/config/gnu-user.h
@@ -138,7 +138,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
   LD_STATIC_OPTION " --whole-archive -lasan --no-whole-archive " \
   LD_DYNAMIC_OPTION "}}%{!static-libasan:-lasan}"
 #undef LIBHWASAN_EARLY_SPEC
-#define LIBHWASAN_EARLY_SPEC "%{static-libhwasan:%{!shared:" \
+#define LIBHWASAN_EARLY_SPEC "%{!shared:libhwasan_preinit%O%s} " \
+  "%{static-libhwasan:%{!shared:" \
   LD_STATIC_OPTION " --whole-archive -lhwasan --no-whole-archive " \
   LD_DYNAMIC_OPTION "}}%{!static-libhwasan:-lhwasan}"
 #undef LIBTSAN_EARLY_SPEC
diff --git a/gcc/config/i386/gnu-user-common.h b/gcc/config/i386/gnu-user-common.h
index cab9be2..9910cd6 100644
--- a/gcc/config/i386/gnu-user-common.h
+++ b/gcc/config/i386/gnu-user-common.h
@@ -47,7 +47,7 @@ along with GCC; see the file COPYING3.  If not see
 
 /* Similar to standard GNU userspace, but adding -ffast-math support.  */
 #define GNU_USER_TARGET_MATHFILE_SPEC \
-  "%{Ofast|ffast-math|funsafe-math-optimizations:crtfastmath.o%s} \
+  "%{Ofast|ffast-math|funsafe-math-optimizations:%{!shared:crtfastmath.o%s}} \
    %{mpc32:crtprec32.o%s} \
    %{mpc64:crtprec64.o%s} \
    %{mpc80:crtprec80.o%s}"
diff --git a/gcc/config/riscv/riscv-passes.def b/gcc/config/riscv/riscv-passes.def
index 23ef8ac..d2d48f2 100644
--- a/gcc/config/riscv/riscv-passes.def
+++ b/gcc/config/riscv/riscv-passes.def
@@ -18,3 +18,4 @@
    <http://www.gnu.org/licenses/>.  */
 
 INSERT_PASS_AFTER (pass_rtl_store_motion, 1, pass_shorten_memrefs);
+INSERT_PASS_BEFORE (pass_sched2, 1, pass_vsetvl);
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index e17e003..cfd0f28 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -96,6 +96,7 @@ extern void riscv_parse_arch_string (const char *, struct gcc_options *, locatio
 extern bool riscv_hard_regno_rename_ok (unsigned, unsigned);
 
 rtl_opt_pass * make_pass_shorten_memrefs (gcc::context *ctxt);
+rtl_opt_pass * make_pass_vsetvl (gcc::context *ctxt);
 
 /* Information about one CPU we know about.  */
 struct riscv_cpu_info {
@@ -131,6 +132,12 @@ enum vlmul_type
   LMUL_F4 = 6,
   LMUL_F2 = 7,
 };
+
+enum avl_type
+{
+  NONVLMAX,
+  VLMAX,
+};
 /* Routines implemented in riscv-vector-builtins.cc.  */
 extern void init_builtins (void);
 extern const char *mangle_builtin_type (const_tree);
@@ -145,17 +152,25 @@ extern bool legitimize_move (rtx, rtx, machine_mode);
 extern void emit_pred_op (unsigned, rtx, rtx, machine_mode);
 extern enum vlmul_type get_vlmul (machine_mode);
 extern unsigned int get_ratio (machine_mode);
+extern int get_ta (rtx);
+extern int get_ma (rtx);
+extern int get_avl_type (rtx);
+extern unsigned int calculate_ratio (unsigned int, enum vlmul_type);
 enum tail_policy
 {
   TAIL_UNDISTURBED = 0,
   TAIL_AGNOSTIC = 1,
+  TAIL_ANY = 2,
 };
 
 enum mask_policy
 {
   MASK_UNDISTURBED = 0,
   MASK_AGNOSTIC = 1,
+  MASK_ANY = 2,
 };
+enum tail_policy get_prefer_tail_policy ();
+enum mask_policy get_prefer_mask_policy ();
 }
 
 /* We classify builtin types into two classes:
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 4992ff2..bae5e92 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -72,11 +72,16 @@ public:
   }
   void add_policy_operand (enum tail_policy vta, enum mask_policy vma)
   {
-    rtx tail_policy_rtx = vta == TAIL_UNDISTURBED ? const0_rtx : const1_rtx;
-    rtx mask_policy_rtx = vma == MASK_UNDISTURBED ? const0_rtx : const1_rtx;
+    rtx tail_policy_rtx = gen_int_mode (vta, Pmode);
+    rtx mask_policy_rtx = gen_int_mode (vma, Pmode);
     add_input_operand (tail_policy_rtx, Pmode);
     add_input_operand (mask_policy_rtx, Pmode);
   }
+  void add_avl_type_operand ()
+  {
+    rtx vlmax_rtx = gen_int_mode (avl_type::VLMAX, Pmode);
+    add_input_operand (vlmax_rtx, Pmode);
+  }
 
   void expand (enum insn_code icode, bool temporary_volatile_p = false)
   {
@@ -112,19 +117,58 @@ emit_vlmax_vsetvl (machine_mode vmode)
   unsigned int sew = GET_MODE_CLASS (vmode) == MODE_VECTOR_BOOL
 		       ? 8
 		       : GET_MODE_BITSIZE (GET_MODE_INNER (vmode));
+  enum vlmul_type vlmul = get_vlmul (vmode);
+  unsigned int ratio = calculate_ratio (sew, vlmul);
+
+  if (!optimize)
+    emit_insn (gen_vsetvl (Pmode, vl, RVV_VLMAX, gen_int_mode (sew, Pmode),
+			   gen_int_mode (get_vlmul (vmode), Pmode), const0_rtx,
+			   const0_rtx));
+  else
+    emit_insn (gen_vlmax_avl (Pmode, vl, gen_int_mode (ratio, Pmode)));
 
-  emit_insn (
-    gen_vsetvl_no_side_effects (Pmode, vl, RVV_VLMAX, gen_int_mode (sew, Pmode),
-				gen_int_mode ((unsigned int) vmode, Pmode),
-				const1_rtx, const1_rtx));
   return vl;
 }
 
+/* Calculate SEW/LMUL ratio.  */
+unsigned int
+calculate_ratio (unsigned int sew, enum vlmul_type vlmul)
+{
+  unsigned int ratio;
+  switch (vlmul)
+    {
+    case LMUL_1:
+      ratio = sew;
+      break;
+    case LMUL_2:
+      ratio = sew / 2;
+      break;
+    case LMUL_4:
+      ratio = sew / 4;
+      break;
+    case LMUL_8:
+      ratio = sew / 8;
+      break;
+    case LMUL_F8:
+      ratio = sew * 8;
+      break;
+    case LMUL_F4:
+      ratio = sew * 4;
+      break;
+    case LMUL_F2:
+      ratio = sew * 2;
+      break;
+    default:
+      gcc_unreachable ();
+    }
+  return ratio;
+}
+
 /* Emit an RVV unmask && vl mov from SRC to DEST.  */
 void
 emit_pred_op (unsigned icode, rtx dest, rtx src, machine_mode mask_mode)
 {
-  insn_expander<7> e;
+  insn_expander<8> e;
   machine_mode mode = GET_MODE (dest);
 
   e.add_output_operand (dest, mode);
@@ -137,7 +181,9 @@ emit_pred_op (unsigned icode, rtx dest, rtx src, machine_mode mask_mode)
   e.add_input_operand (vlmax, Pmode);
 
   if (GET_MODE_CLASS (mode) != MODE_VECTOR_BOOL)
-    e.add_policy_operand (TAIL_AGNOSTIC, MASK_AGNOSTIC);
+    e.add_policy_operand (get_prefer_tail_policy (), get_prefer_mask_policy ());
+
+  e.add_avl_type_operand ();
 
   e.expand ((enum insn_code) icode, MEM_P (dest) || MEM_P (src));
 }
@@ -256,4 +302,44 @@ get_ratio (machine_mode mode)
     return mode_vtype_infos.ratio_for_min_vlen64[mode];
 }
 
+/* Get ta according to operand[tail_op_idx].  */
+int
+get_ta (rtx ta)
+{
+  if (INTVAL (ta) == TAIL_ANY)
+    return INVALID_ATTRIBUTE;
+  return INTVAL (ta);
+}
+
+/* Get ma according to operand[mask_op_idx].  */
+int
+get_ma (rtx ma)
+{
+  if (INTVAL (ma) == MASK_ANY)
+    return INVALID_ATTRIBUTE;
+  return INTVAL (ma);
+}
+
+/* Get prefer tail policy.  */
+enum tail_policy
+get_prefer_tail_policy ()
+{
+  /* TODO: By default, we choose to use TAIL_ANY which allows
+     compiler pick up either agnostic or undisturbed. Maybe we
+     will have a compile option like -mprefer=agnostic to set
+     this value???.  */
+  return TAIL_ANY;
+}
+
+/* Get prefer mask policy.  */
+enum mask_policy
+get_prefer_mask_policy ()
+{
+  /* TODO: By default, we choose to use MASK_ANY which allows
+     compiler pick up either agnostic or undisturbed. Maybe we
+     will have a compile option like -mprefer=agnostic to set
+     this value???.  */
+  return MASK_ANY;
+}
+
 } // namespace riscv_vector
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 231b63a..ffeb1b2 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -73,7 +73,7 @@ public:
 			 gen_int_mode (GET_MODE_BITSIZE (inner_mode), Pmode));
 
     /* LMUL.  */
-    e.add_input_operand (Pmode, gen_int_mode ((unsigned int) mode, Pmode));
+    e.add_input_operand (Pmode, gen_int_mode (get_vlmul (mode), Pmode));
 
     /* TA.  */
     e.add_input_operand (Pmode, gen_int_mode (1, Pmode));
diff --git a/gcc/config/riscv/riscv-vector-switch.def b/gcc/config/riscv/riscv-vector-switch.def
index a51f45b..ec12be8 100644
--- a/gcc/config/riscv/riscv-vector-switch.def
+++ b/gcc/config/riscv/riscv-vector-switch.def
@@ -95,16 +95,16 @@ TODO: FP16 vector needs support of 'zvfh', we don't support it yet.  */
 #endif
 
 /* Mask modes. Disable VNx64BImode when TARGET_MIN_VLEN == 32.  */
-ENTRY (VNx64BI, TARGET_MIN_VLEN > 32, LMUL_F8, 64, LMUL_RESERVED, 0)
-ENTRY (VNx32BI, true, LMUL_F4, 32, LMUL_RESERVED, 0)
-ENTRY (VNx16BI, true, LMUL_F2, 16, LMUL_RESERVED, 0)
-ENTRY (VNx8BI, true, LMUL_1, 8, LMUL_RESERVED, 0)
-ENTRY (VNx4BI, true, LMUL_2, 4, LMUL_RESERVED, 0)
-ENTRY (VNx2BI, true, LMUL_4, 2, LMUL_RESERVED, 0)
-ENTRY (VNx1BI, true, LMUL_8, 1, LMUL_RESERVED, 0)
+ENTRY (VNx64BI, TARGET_MIN_VLEN > 32, LMUL_RESERVED, 0, LMUL_8, 1)
+ENTRY (VNx32BI, true, LMUL_8, 1, LMUL_4, 2)
+ENTRY (VNx16BI, true, LMUL_4, 2, LMUL_2, 4)
+ENTRY (VNx8BI, true, LMUL_2, 4, LMUL_1, 8)
+ENTRY (VNx4BI, true, LMUL_1, 8, LMUL_F2, 16)
+ENTRY (VNx2BI, true, LMUL_F2, 16, LMUL_F4, 32)
+ENTRY (VNx1BI, true, LMUL_F4, 32, LMUL_F8, 64)
 
 /* SEW = 8. Disable VNx64QImode when TARGET_MIN_VLEN == 32.  */
-ENTRY (VNx64QI, TARGET_MIN_VLEN > 32, LMUL_8, 1, LMUL_RESERVED, 0)
+ENTRY (VNx64QI, TARGET_MIN_VLEN > 32, LMUL_RESERVED, 0, LMUL_8, 1)
 ENTRY (VNx32QI, true, LMUL_8, 1, LMUL_4, 2)
 ENTRY (VNx16QI, true, LMUL_4, 2, LMUL_2, 4)
 ENTRY (VNx8QI, true, LMUL_2, 4, LMUL_1, 8)
@@ -113,7 +113,7 @@ ENTRY (VNx2QI, true, LMUL_F2, 16, LMUL_F4, 32)
 ENTRY (VNx1QI, true, LMUL_F4, 32, LMUL_F8, 64)
 
 /* SEW = 16. Disable VNx32HImode when TARGET_MIN_VLEN == 32.  */
-ENTRY (VNx32HI, TARGET_MIN_VLEN > 32, LMUL_8, 2, LMUL_RESERVED, 0)
+ENTRY (VNx32HI, TARGET_MIN_VLEN > 32, LMUL_RESERVED, 0, LMUL_8, 2)
 ENTRY (VNx16HI, true, LMUL_8, 2, LMUL_4, 4)
 ENTRY (VNx8HI, true, LMUL_4, 4, LMUL_2, 8)
 ENTRY (VNx4HI, true, LMUL_2, 8, LMUL_1, 16)
@@ -121,7 +121,7 @@ ENTRY (VNx2HI, true, LMUL_1, 16, LMUL_F2, 32)
 ENTRY (VNx1HI, true, LMUL_F2, 32, LMUL_F4, 64)
 
 /* TODO:Disable all FP16 vector, enable them when 'zvfh' is supported.  */
-ENTRY (VNx32HF, false, LMUL_8, 2, LMUL_RESERVED, 0)
+ENTRY (VNx32HF, false, LMUL_RESERVED, 0, LMUL_8, 2)
 ENTRY (VNx16HF, false, LMUL_8, 2, LMUL_4, 4)
 ENTRY (VNx8HF, false, LMUL_4, 4, LMUL_2, 8)
 ENTRY (VNx4HF, false, LMUL_2, 8, LMUL_1, 16)
@@ -131,18 +131,18 @@ ENTRY (VNx1HF, false, LMUL_F2, 32, LMUL_F4, 64)
 /* SEW = 32. Disable VNx16SImode when TARGET_MIN_VLEN == 32.
    For single-precision floating-point, we need TARGET_VECTOR_FP32 ==
    RVV_ENABLE.  */
-ENTRY (VNx16SI, TARGET_MIN_VLEN > 32, LMUL_8, 4, LMUL_RESERVED, 0)
+ENTRY (VNx16SI, TARGET_MIN_VLEN > 32, LMUL_RESERVED, 0, LMUL_8, 4)
 ENTRY (VNx8SI, true, LMUL_8, 4, LMUL_4, 8)
-ENTRY (VNx4SI, true, LMUL_4, 8, LMUL_2, 4)
-ENTRY (VNx2SI, true, LMUL_2, 16, LMUL_1, 2)
-ENTRY (VNx1SI, true, LMUL_1, 32, LMUL_F2, 1)
+ENTRY (VNx4SI, true, LMUL_4, 8, LMUL_2, 16)
+ENTRY (VNx2SI, true, LMUL_2, 16, LMUL_1, 32)
+ENTRY (VNx1SI, true, LMUL_1, 32, LMUL_F2, 64)
 
-ENTRY (VNx16SF, TARGET_VECTOR_FP32 && (TARGET_MIN_VLEN > 32), LMUL_8, 4,
-       LMUL_RESERVED, 0)
+ENTRY (VNx16SF, TARGET_VECTOR_FP32 && (TARGET_MIN_VLEN > 32), LMUL_RESERVED, 0,
+       LMUL_8, 4)
 ENTRY (VNx8SF, TARGET_VECTOR_FP32, LMUL_8, 4, LMUL_4, 8)
-ENTRY (VNx4SF, TARGET_VECTOR_FP32, LMUL_4, 8, LMUL_2, 4)
-ENTRY (VNx2SF, TARGET_VECTOR_FP32, LMUL_2, 16, LMUL_1, 2)
-ENTRY (VNx1SF, TARGET_VECTOR_FP32, LMUL_1, 32, LMUL_F2, 1)
+ENTRY (VNx4SF, TARGET_VECTOR_FP32, LMUL_4, 8, LMUL_2, 16)
+ENTRY (VNx2SF, TARGET_VECTOR_FP32, LMUL_2, 16, LMUL_1, 32)
+ENTRY (VNx1SF, TARGET_VECTOR_FP32, LMUL_1, 32, LMUL_F2, 64)
 
 /* SEW = 64. Enable when TARGET_MIN_VLEN > 32.
    For double-precision floating-point, we need TARGET_VECTOR_FP64 ==
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
new file mode 100644
index 0000000..3ca3fc1
--- /dev/null
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -0,0 +1,2509 @@
+/* VSETVL pass for RISC-V 'V' Extension for GNU compiler.
+   Copyright(C) 2022-2022 Free Software Foundation, Inc.
+   Contributed by Juzhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or(at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+<http://www.gnu.org/licenses/>.  */
+
+/*  This pass is to Set VL/VTYPE global status for RVV instructions
+    that depend on VL and VTYPE registers by Lazy code motion (LCM).
+
+    Strategy:
+
+    -  Backward demanded info fusion within block.
+
+    -  Lazy code motion (LCM) based demanded info backward propagation.
+
+    -  RTL_SSA framework for def-use, PHI analysis.
+
+    -  Lazy code motion (LCM) for global VL/VTYPE optimization.
+
+    Assumption:
+
+    -  Each avl operand is either an immediate (must be in range 0 ~ 31) or reg.
+
+    This pass consists of 5 phases:
+
+    -  Phase 1 - compute VL/VTYPE demanded information within each block
+       by backward data-flow analysis.
+
+    -  Phase 2 - Emit vsetvl instructions within each basic block according to
+       demand, compute and save ANTLOC && AVLOC of each block.
+
+    -  Phase 3 - Backward demanded info propagation and fusion across blocks.
+
+    -  Phase 4 - Lazy code motion including: compute local properties,
+       pre_edge_lcm and vsetvl insertion && delete edges for LCM results.
+
+    -  Phase 5 - Cleanup AVL operand of RVV instruction since it will not be
+       used any more and VL operand of VSETVL instruction if it is not used by
+       any non-debug instructions.
+
+    Implementation:
+
+    -  The subroutine of optimize == 0 is simple_vsetvl.
+       This function simplily vsetvl insertion for each RVV
+       instruction. No optimization.
+
+    -  The subroutine of optimize > 0 is lazy_vsetvl.
+       This function optimize vsetvl insertion process by
+       lazy code motion (LCM) layering on RTL_SSA.  */
+
+#define IN_TARGET_CODE 1
+#define INCLUDE_ALGORITHM
+#define INCLUDE_FUNCTIONAL
+
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+#include "backend.h"
+#include "rtl.h"
+#include "target.h"
+#include "tree-pass.h"
+#include "df.h"
+#include "rtl-ssa.h"
+#include "cfgcleanup.h"
+#include "insn-config.h"
+#include "insn-attr.h"
+#include "insn-opinit.h"
+#include "tm-constrs.h"
+#include "cfgrtl.h"
+#include "cfganal.h"
+#include "lcm.h"
+#include "predict.h"
+#include "profile-count.h"
+#include "riscv-vsetvl.h"
+
+using namespace rtl_ssa;
+using namespace riscv_vector;
+
+DEBUG_FUNCTION void
+debug (const vector_insn_info *info)
+{
+  info->dump (stderr);
+}
+
+DEBUG_FUNCTION void
+debug (const vector_infos_manager *info)
+{
+  info->dump (stderr);
+}
+
+static bool
+vlmax_avl_p (rtx x)
+{
+  return x && rtx_equal_p (x, RVV_VLMAX);
+}
+
+static bool
+vlmax_avl_insn_p (rtx_insn *rinsn)
+{
+  return INSN_CODE (rinsn) == CODE_FOR_vlmax_avlsi
+	 || INSN_CODE (rinsn) == CODE_FOR_vlmax_avldi;
+}
+
+static bool
+loop_basic_block_p (const basic_block cfg_bb)
+{
+  return JUMP_P (BB_END (cfg_bb)) && any_condjump_p (BB_END (cfg_bb));
+}
+
+/* Return true if it is an RVV instruction depends on VTYPE global
+   status register.  */
+static bool
+has_vtype_op (rtx_insn *rinsn)
+{
+  return recog_memoized (rinsn) >= 0 && get_attr_has_vtype_op (rinsn);
+}
+
+/* Return true if it is an RVV instruction depends on VL global
+   status register.  */
+static bool
+has_vl_op (rtx_insn *rinsn)
+{
+  return recog_memoized (rinsn) >= 0 && get_attr_has_vl_op (rinsn);
+}
+
+/* Is this a SEW value that can be encoded into the VTYPE format.  */
+static bool
+valid_sew_p (size_t sew)
+{
+  return exact_log2 (sew) && sew >= 8 && sew <= 64;
+}
+
+/* Return true if it is a vsetvl instruction.  */
+static bool
+vector_config_insn_p (rtx_insn *rinsn)
+{
+  return recog_memoized (rinsn) >= 0 && get_attr_type (rinsn) == TYPE_VSETVL;
+}
+
+/* Return true if it is vsetvldi or vsetvlsi.  */
+static bool
+vsetvl_insn_p (rtx_insn *rinsn)
+{
+  return INSN_CODE (rinsn) == CODE_FOR_vsetvldi
+	 || INSN_CODE (rinsn) == CODE_FOR_vsetvlsi;
+}
+
+/* Return true if INSN1 comes befeore INSN2 in the same block.  */
+static bool
+same_bb_and_before_p (const insn_info *insn1, const insn_info *insn2)
+{
+  return (insn1->bb ()->index () == insn2->bb ()->index ())
+	 && (*insn1 < *insn2);
+}
+
+/* Return true if INSN1 comes after or equal INSN2 in the same block.  */
+static bool
+same_bb_and_after_or_equal_p (const insn_info *insn1, const insn_info *insn2)
+{
+  return (insn1->bb ()->index () == insn2->bb ()->index ())
+	 && (*insn1 >= *insn2);
+}
+
+/* An "anticipatable occurrence" is one that is the first occurrence in the
+   basic block, the operands are not modified in the basic block prior
+   to the occurrence and the output is not used between the start of
+   the block and the occurrence.  */
+static bool
+anticipatable_occurrence_p (const insn_info *insn, const vector_insn_info dem)
+{
+  /* The only possible operand we care of VSETVL is AVL.  */
+  if (dem.has_avl_reg ())
+    {
+      /* The operands shoule not be modified in the basic block prior
+	 to the occurrence.  */
+      if (!vlmax_avl_p (dem.get_avl ()))
+	{
+	  set_info *set
+	    = find_access (insn->uses (), REGNO (dem.get_avl ()))->def ();
+	  /* If it's undefined, it's not anticipatable conservatively.  */
+	  if (!set)
+	    return false;
+	  if (same_bb_and_before_p (set->insn (), insn))
+	    return false;
+	}
+    }
+
+  /* The output should not be used between the start of the block
+     and the occurrence.  */
+  if (vsetvl_insn_p (insn->rtl ()))
+    {
+      rtx dest = SET_DEST (XVECEXP (PATTERN (insn->rtl ()), 0, 0));
+      for (insn_info *i = insn->prev_nondebug_insn (); i != nullptr;
+	   i = i->prev_nondebug_insn ())
+	if (find_access (i->uses (), REGNO (dest)))
+	  return false;
+    }
+
+  return true;
+}
+
+/* An "available occurrence" is one that is the last occurrence in the
+   basic block and the operands are not modified by following statements in
+   the basic block [including this insn].  */
+static bool
+available_occurrence_p (const insn_info *insn, const vector_insn_info dem)
+{
+  /* The only possible operand we care of VSETVL is AVL.  */
+  if (dem.has_avl_reg ())
+    {
+      /* The operands shoule not be modified in the basic block prior
+	 to the occurrence.
+	 e.g.
+	    bb:
+	      vsetvl hr3, hr2, ...
+	      ...
+	      vadd ... (vl=hr3)
+      */
+      if (!vlmax_avl_p (dem.get_avl ()))
+	{
+	  set_info *set
+	    = find_access (insn->uses (), REGNO (dem.get_avl ()))->def ();
+	  /* If it's undefined, it's not available conservatively.  */
+	  if (!set)
+	    return false;
+	  if (same_bb_and_after_or_equal_p (set->insn (), insn))
+	    return false;
+	}
+    }
+  return true;
+}
+
+/* Return true if the branch probability is dominate.  */
+static bool
+dominate_probability_p (edge e)
+{
+  /* TODO: We simpily pick dominate probability >= 50%.
+     However, it isn't always optimal. Consider cases
+     like this:
+       bb 0: 80% succs: bb 2, bb 3, bb 4, bb 5.
+       bb 1: 20%
+
+     Assume bb 1, bb 2, bb 3, bb 4, bb 5 are different
+     one another, and bb 2, bb 3, bb 4, bb 5 are incompatible.
+
+     ??? Maybe backward propagate bb 1 is better ???
+     May need to support an accurate and reliable COST model
+     in the future.  */
+  return e->probability >= profile_probability::even ();
+}
+
+/* Return true if the block is worthwhile backward propagation.  */
+static bool
+backward_propagate_worthwhile_p (const basic_block cfg_bb,
+				 const vector_block_info block_info)
+{
+  if (loop_basic_block_p (cfg_bb))
+    {
+      if (block_info.local_dem.compatible_p (block_info.reaching_out))
+	return true;
+
+      /* There is a obvious case that is not worthwhile and meaningless
+	 to propagate the demand information:
+			  local_dem
+			     __________
+			 ____|____     |
+			|        |     |
+			|________|     |
+			     |_________|
+			  reaching_out
+	  Header is incompatible with reaching_out and the block is loop itself,
+	  we don't backward propagete the local_dem since we can't avoid emit
+	  vsetvl for the local_dem.  */
+      edge e;
+      edge_iterator ei;
+      FOR_EACH_EDGE (e, ei, cfg_bb->succs)
+	if (e->dest->index == cfg_bb->index)
+	  return false;
+    }
+
+  return true;
+}
+
+/* Helper function to get VL operand.  */
+static rtx
+get_vl (rtx_insn *rinsn)
+{
+  if (has_vl_op (rinsn))
+    {
+      /* We only call get_vl for VLMAX use VTYPE instruction.
+	 It's used to get the VL operand to emit VLMAX VSETVL instruction:
+	 vsetvl a5,zero,e32,m1,ta,ma.  */
+      gcc_assert (get_attr_avl_type (rinsn) == VLMAX);
+      extract_insn_cached (rinsn);
+      return recog_data.operand[get_attr_vl_op_idx (rinsn)];
+    }
+  return SET_DEST (XVECEXP (PATTERN (rinsn), 0, 0));
+}
+
+/* Helper function to get AVL operand.  */
+static rtx
+get_avl (rtx_insn *rinsn)
+{
+  if (vsetvl_insn_p (rinsn))
+    return XVECEXP (SET_SRC (XVECEXP (PATTERN (rinsn), 0, 0)), 0, 0);
+
+  if (!has_vl_op (rinsn))
+    return NULL_RTX;
+  if (get_attr_avl_type (rinsn) == VLMAX)
+    return RVV_VLMAX;
+  extract_insn_cached (rinsn);
+  return recog_data.operand[get_attr_vl_op_idx (rinsn)];
+}
+
+static bool
+can_backward_propagate_p (const function_info *ssa, const basic_block cfg_bb,
+			  const vector_insn_info prop)
+{
+  insn_info *insn = prop.get_insn ();
+
+  /* TODO: We don't backward propagate the explict VSETVL here
+     since we will change vsetvl and vsetvlmax intrinsiscs into
+     no side effects which can be optimized into optimzal location
+     by GCC internal PASSes. We only need to support these backward
+     propagation if vsetvl instrinsics have side effects.  */
+  if (vsetvl_insn_p (insn->rtl ()))
+    return false;
+
+  gcc_assert (has_vtype_op (insn->rtl ()));
+  rtx reg = NULL_RTX;
+
+  /* Case 1: Don't need VL. Just let it backward propagate.  */
+  if (!has_vl_op (insn->rtl ()))
+    return true;
+  else
+    {
+      /* Case 2: CONST_INT AVL, we don't need to check def.  */
+      if (prop.has_avl_imm ())
+	return true;
+      else
+	{
+	  /* Case 3: REG AVL, we need to check the distance of def to make
+	     sure we won't backward propagate over the def.  */
+	  gcc_assert (prop.has_avl_reg ());
+	  if (vlmax_avl_p (prop.get_avl ()))
+	    /* Check VL operand for vsetvl vl,zero.  */
+	    reg = get_vl (insn->rtl ());
+	  else
+	    /* Check AVL operand for vsetvl zero,avl.  */
+	    reg = get_avl (insn->rtl ());
+	}
+    }
+
+  def_info *def = find_access (insn->uses (), REGNO (reg))->def ();
+
+  /* If the definition is in the current block, we can't propagate it
+     acrocss blocks.  */
+  if (def->bb ()->cfg_bb ()->index == insn->bb ()->cfg_bb ()->index)
+    {
+      set_info *set = safe_dyn_cast<set_info *> (def);
+
+      /* True if it is a degenerate PHI that can be backward propagated.  */
+      auto valid_degenerate_phi_p = [&] () {
+	if (!set)
+	  return false;
+
+	phi_info *phi = safe_dyn_cast<phi_info *> (set);
+	if (!phi)
+	  return false;
+
+	basic_block iter_bb;
+	set_info *ultimate_def = look_through_degenerate_phi (set);
+	const basic_block ultimate_bb = ultimate_def->bb ()->cfg_bb ();
+	FOR_BB_BETWEEN (iter_bb, ultimate_bb, def->bb ()->cfg_bb (), next_bb)
+	  if (iter_bb->index == cfg_bb->index)
+	    return true;
+
+	return false;
+      };
+
+      if (valid_degenerate_phi_p ())
+	return true;
+
+      /* TODO: Support non-degenerate PHI backward propagation later.  */
+      return false;
+    }
+
+  /* If the definition block is the current block that we iterate, we
+     can backward propagate it since we will insert or change VL/VTYPE
+     info at the end of the current block we iterate.  */
+  if (def->bb ()->cfg_bb ()->index == cfg_bb->index)
+    return true;
+
+  /* Make sure we don't backward propagete the VL/VTYPE info over the
+     definition blocks.  */
+  bool visited_p = false;
+  for (const bb_info *bb : ssa->reverse_bbs ())
+    {
+      if (bb->cfg_bb ()->index == cfg_bb->index && visited_p)
+	return false;
+      if (bb->cfg_bb ()->index == def->bb ()->cfg_bb ()->index)
+	visited_p = true;
+    }
+
+  return true;
+}
+
+/* Helper function to get SEW operand. We always have SEW value for
+   all RVV instructions that have VTYPE OP.  */
+static uint8_t
+get_sew (rtx_insn *rinsn)
+{
+  return get_attr_sew (rinsn);
+}
+
+/* Helper function to get VLMUL operand. We always have VLMUL value for
+   all RVV instructions that have VTYPE OP. */
+static enum vlmul_type
+get_vlmul (rtx_insn *rinsn)
+{
+  return (enum vlmul_type) get_attr_vlmul (rinsn);
+}
+
+/* Get default tail policy.  */
+static bool
+get_default_ta ()
+{
+  /* For the instruction that doesn't require TA, we still need a default value
+     to emit vsetvl. We pick up the default value according to prefer policy. */
+  return (bool) (get_prefer_tail_policy () & 0x1
+		 || (get_prefer_tail_policy () >> 1 & 0x1));
+}
+
+/* Get default mask policy.  */
+static bool
+get_default_ma ()
+{
+  /* For the instruction that doesn't require MA, we still need a default value
+     to emit vsetvl. We pick up the default value according to prefer policy. */
+  return (bool) (get_prefer_mask_policy () & 0x1
+		 || (get_prefer_mask_policy () >> 1 & 0x1));
+}
+
+/* Helper function to get TA operand.  */
+static bool
+tail_agnostic_p (rtx_insn *rinsn)
+{
+  /* If it doesn't have TA, we return agnostic by default.  */
+  extract_insn_cached (rinsn);
+  int ta = get_attr_ta (rinsn);
+  return ta == INVALID_ATTRIBUTE ? get_default_ta () : IS_AGNOSTIC (ta);
+}
+
+/* Helper function to get MA operand.  */
+static bool
+mask_agnostic_p (rtx_insn *rinsn)
+{
+  /* If it doesn't have MA, we return agnostic by default.  */
+  extract_insn_cached (rinsn);
+  int ma = get_attr_ma (rinsn);
+  return ma == INVALID_ATTRIBUTE ? get_default_ma () : IS_AGNOSTIC (ma);
+}
+
+/* Return true if FN has a vector instruction that use VL/VTYPE.  */
+static bool
+has_vector_insn (function *fn)
+{
+  basic_block cfg_bb;
+  rtx_insn *rinsn;
+  FOR_ALL_BB_FN (cfg_bb, fn)
+    FOR_BB_INSNS (cfg_bb, rinsn)
+      if (NONDEBUG_INSN_P (rinsn) && has_vtype_op (rinsn))
+	return true;
+  return false;
+}
+
+/* Emit vsetvl instruction.  */
+static rtx
+gen_vsetvl_pat (enum vsetvl_type insn_type, vl_vtype_info info, rtx vl)
+{
+  rtx avl = info.get_avl ();
+  rtx sew = gen_int_mode (info.get_sew (), Pmode);
+  rtx vlmul = gen_int_mode (info.get_vlmul (), Pmode);
+  rtx ta = gen_int_mode (info.get_ta (), Pmode);
+  rtx ma = gen_int_mode (info.get_ma (), Pmode);
+
+  if (insn_type == VSETVL_NORMAL)
+    {
+      gcc_assert (vl != NULL_RTX);
+      return gen_vsetvl (Pmode, vl, avl, sew, vlmul, ta, ma);
+    }
+  else if (insn_type == VSETVL_VTYPE_CHANGE_ONLY)
+    return gen_vsetvl_vtype_change_only (sew, vlmul, ta, ma);
+  else
+    return gen_vsetvl_discard_result (Pmode, avl, sew, vlmul, ta, ma);
+}
+
+static rtx
+gen_vsetvl_pat (rtx_insn *rinsn, const vector_insn_info info)
+{
+  rtx new_pat;
+  if (vsetvl_insn_p (rinsn) || vlmax_avl_p (info.get_avl ()))
+    {
+      rtx dest = get_vl (rinsn);
+      new_pat = gen_vsetvl_pat (VSETVL_NORMAL, info, dest);
+    }
+  else if (INSN_CODE (rinsn) == CODE_FOR_vsetvl_vtype_change_only)
+    new_pat = gen_vsetvl_pat (VSETVL_VTYPE_CHANGE_ONLY, info, NULL_RTX);
+  else
+    new_pat = gen_vsetvl_pat (VSETVL_DISCARD_RESULT, info, NULL_RTX);
+  return new_pat;
+}
+
+static void
+emit_vsetvl_insn (enum vsetvl_type insn_type, enum emit_type emit_type,
+		  vl_vtype_info info, rtx vl, rtx_insn *rinsn)
+{
+  rtx pat = gen_vsetvl_pat (insn_type, info, vl);
+  if (dump_file)
+    {
+      fprintf (dump_file, "\nInsert vsetvl insn PATTERN:\n");
+      print_rtl_single (dump_file, pat);
+    }
+
+  if (emit_type == EMIT_DIRECT)
+    emit_insn (pat);
+  else if (emit_type == EMIT_BEFORE)
+    emit_insn_before (pat, rinsn);
+  else
+    emit_insn_after (pat, rinsn);
+}
+
+static void
+eliminate_insn (rtx_insn *rinsn)
+{
+  if (dump_file)
+    {
+      fprintf (dump_file, "\nEliminate insn %d:\n", INSN_UID (rinsn));
+      print_rtl_single (dump_file, rinsn);
+    }
+  if (in_sequence_p ())
+    remove_insn (rinsn);
+  else
+    delete_insn (rinsn);
+}
+
+static void
+insert_vsetvl (enum emit_type emit_type, rtx_insn *rinsn,
+	       const vector_insn_info &info, const vector_insn_info &prev_info)
+{
+  /* Use X0, X0 form if the AVL is the same and the SEW+LMUL gives the same
+     VLMAX.  */
+  if (prev_info.valid_or_dirty_p () && !prev_info.unknown_p ()
+      && info.same_avl_p (prev_info) && info.same_vlmax_p (prev_info))
+    {
+      emit_vsetvl_insn (VSETVL_VTYPE_CHANGE_ONLY, emit_type, info, NULL_RTX,
+			rinsn);
+      return;
+    }
+
+  if (info.has_avl_imm ())
+    {
+      emit_vsetvl_insn (VSETVL_DISCARD_RESULT, emit_type, info, NULL_RTX,
+			rinsn);
+      return;
+    }
+
+  if (info.has_avl_no_reg ())
+    {
+      /* We can only use x0, x0 if there's no chance of the vtype change causing
+	 the previous vl to become invalid.  */
+      if (prev_info.valid_or_dirty_p () && !prev_info.unknown_p ()
+	  && info.same_vlmax_p (prev_info))
+	{
+	  emit_vsetvl_insn (VSETVL_VTYPE_CHANGE_ONLY, emit_type, info, NULL_RTX,
+			    rinsn);
+	  return;
+	}
+      /* Otherwise use an AVL of 0 to avoid depending on previous vl.  */
+      vl_vtype_info new_info = info;
+      new_info.set_avl_info (avl_info (const0_rtx, nullptr));
+      emit_vsetvl_insn (VSETVL_DISCARD_RESULT, emit_type, new_info, NULL_RTX,
+			rinsn);
+      return;
+    }
+
+  /* Use X0 as the DestReg unless AVLReg is X0. We also need to change the
+     opcode if the AVLReg is X0 as they have different register classes for
+     the AVL operand.  */
+  if (vlmax_avl_p (info.get_avl ()))
+    {
+      gcc_assert (has_vtype_op (rinsn) || vsetvl_insn_p (rinsn));
+      rtx vl_op = get_vl (rinsn);
+      gcc_assert (!vlmax_avl_p (vl_op));
+      emit_vsetvl_insn (VSETVL_NORMAL, emit_type, info, vl_op, rinsn);
+      return;
+    }
+
+  emit_vsetvl_insn (VSETVL_DISCARD_RESULT, emit_type, info, NULL_RTX, rinsn);
+
+  if (dump_file)
+    {
+      fprintf (dump_file, "Update VL/VTYPE info, previous info=");
+      prev_info.dump (dump_file);
+    }
+}
+
+/* If X contains any LABEL_REF's, add REG_LABEL_OPERAND notes for them
+   to INSN.  If such notes are added to an insn which references a
+   CODE_LABEL, the LABEL_NUSES count is incremented.  We have to add
+   that note, because the following loop optimization pass requires
+   them.  */
+
+/* ??? If there was a jump optimization pass after gcse and before loop,
+   then we would not need to do this here, because jump would add the
+   necessary REG_LABEL_OPERAND and REG_LABEL_TARGET notes.  */
+
+static void
+add_label_notes (rtx x, rtx_insn *insn)
+{
+  enum rtx_code code = GET_CODE (x);
+  int i, j;
+  const char *fmt;
+
+  if (code == LABEL_REF && !LABEL_REF_NONLOCAL_P (x))
+    {
+      /* This code used to ignore labels that referred to dispatch tables to
+	 avoid flow generating (slightly) worse code.
+
+	 We no longer ignore such label references (see LABEL_REF handling in
+	 mark_jump_label for additional information).  */
+
+      /* There's no reason for current users to emit jump-insns with
+	 such a LABEL_REF, so we don't have to handle REG_LABEL_TARGET
+	 notes.  */
+      gcc_assert (!JUMP_P (insn));
+      add_reg_note (insn, REG_LABEL_OPERAND, label_ref_label (x));
+
+      if (LABEL_P (label_ref_label (x)))
+	LABEL_NUSES (label_ref_label (x))++;
+
+      return;
+    }
+
+  for (i = GET_RTX_LENGTH (code) - 1, fmt = GET_RTX_FORMAT (code); i >= 0; i--)
+    {
+      if (fmt[i] == 'e')
+	add_label_notes (XEXP (x, i), insn);
+      else if (fmt[i] == 'E')
+	for (j = XVECLEN (x, i) - 1; j >= 0; j--)
+	  add_label_notes (XVECEXP (x, i, j), insn);
+    }
+}
+
+/* Add EXPR to the end of basic block BB.
+
+   This is used by both the PRE and code hoisting.  */
+
+static void
+insert_insn_end_basic_block (rtx_insn *rinsn, basic_block cfg_bb)
+{
+  rtx_insn *end_rinsn = BB_END (cfg_bb);
+  rtx_insn *new_insn;
+  rtx_insn *pat, *pat_end;
+
+  pat = rinsn;
+  gcc_assert (pat && INSN_P (pat));
+
+  pat_end = pat;
+  while (NEXT_INSN (pat_end) != NULL_RTX)
+    pat_end = NEXT_INSN (pat_end);
+
+  /* If the last end_rinsn is a jump, insert EXPR in front.  Similarly we need
+     to take care of trapping instructions in presence of non-call exceptions.
+   */
+
+  if (JUMP_P (end_rinsn)
+      || (NONJUMP_INSN_P (end_rinsn)
+	  && (!single_succ_p (cfg_bb)
+	      || single_succ_edge (cfg_bb)->flags & EDGE_ABNORMAL)))
+    {
+      /* FIXME: What if something in jump uses value set in new end_rinsn?  */
+      new_insn = emit_insn_before_noloc (pat, end_rinsn, cfg_bb);
+    }
+
+  /* Likewise if the last end_rinsn is a call, as will happen in the presence
+     of exception handling.  */
+  else if (CALL_P (end_rinsn)
+	   && (!single_succ_p (cfg_bb)
+	       || single_succ_edge (cfg_bb)->flags & EDGE_ABNORMAL))
+    {
+      /* Keeping in mind targets with small register classes and parameters
+	 in registers, we search backward and place the instructions before
+	 the first parameter is loaded.  Do this for everyone for consistency
+	 and a presumption that we'll get better code elsewhere as well.  */
+
+      /* Since different machines initialize their parameter registers
+	 in different orders, assume nothing.  Collect the set of all
+	 parameter registers.  */
+      end_rinsn = find_first_parameter_load (end_rinsn, BB_HEAD (cfg_bb));
+
+      /* If we found all the parameter loads, then we want to insert
+	 before the first parameter load.
+
+	 If we did not find all the parameter loads, then we might have
+	 stopped on the head of the block, which could be a CODE_LABEL.
+	 If we inserted before the CODE_LABEL, then we would be putting
+	 the end_rinsn in the wrong basic block.  In that case, put the
+	 end_rinsn after the CODE_LABEL.  Also, respect NOTE_INSN_BASIC_BLOCK.
+       */
+      while (LABEL_P (end_rinsn) || NOTE_INSN_BASIC_BLOCK_P (end_rinsn))
+	end_rinsn = NEXT_INSN (end_rinsn);
+
+      new_insn = emit_insn_before_noloc (pat, end_rinsn, cfg_bb);
+    }
+  else
+    new_insn = emit_insn_after_noloc (pat, end_rinsn, cfg_bb);
+
+  while (1)
+    {
+      if (INSN_P (pat))
+	add_label_notes (PATTERN (pat), new_insn);
+      if (pat == pat_end)
+	break;
+      pat = NEXT_INSN (pat);
+    }
+}
+
+/* Get VL/VTYPE information for INSN.  */
+static vl_vtype_info
+get_vl_vtype_info (const insn_info *insn)
+{
+  if (vector_config_insn_p (insn->rtl ()))
+    gcc_assert (vsetvl_insn_p (insn->rtl ())
+		&& "Can't handle X0, rs1 vsetvli yet");
+
+  set_info *set = nullptr;
+  rtx avl = ::get_avl (insn->rtl ());
+  if (avl && REG_P (avl) && !vlmax_avl_p (avl))
+    set = find_access (insn->uses (), REGNO (avl))->def ();
+
+  uint8_t sew = get_sew (insn->rtl ());
+  enum vlmul_type vlmul = get_vlmul (insn->rtl ());
+  uint8_t ratio = get_attr_ratio (insn->rtl ());
+  /* when get_attr_ratio is invalid, this kind of instructions
+     doesn't care about ratio. However, we still need this value
+     in demand info backward analysis.  */
+  if (ratio == INVALID_ATTRIBUTE)
+    ratio = calculate_ratio (sew, vlmul);
+  bool ta = tail_agnostic_p (insn->rtl ());
+  bool ma = mask_agnostic_p (insn->rtl ());
+
+  /* If merge operand is undef value, we prefer agnostic.  */
+  int merge_op_idx = get_attr_merge_op_idx (insn->rtl ());
+  if (merge_op_idx != INVALID_ATTRIBUTE
+      && satisfies_constraint_vu (recog_data.operand[merge_op_idx]))
+    {
+      ta = true;
+      ma = true;
+    }
+
+  vl_vtype_info info (avl_info (avl, set), sew, vlmul, ratio, ta, ma);
+  return info;
+}
+
+static void
+change_insn (rtx_insn *rinsn, rtx new_pat)
+{
+  /* We don't apply change on RTL_SSA here since it's possible a
+     new INSN we add in the PASS before which doesn't have RTL_SSA
+     info yet.*/
+  if (dump_file)
+    {
+      fprintf (dump_file, "\nChange PATTERN of insn %d from:\n",
+	       INSN_UID (rinsn));
+      print_rtl_single (dump_file, PATTERN (rinsn));
+    }
+
+  validate_change (rinsn, &PATTERN (rinsn), new_pat, true);
+
+  if (dump_file)
+    {
+      fprintf (dump_file, "\nto:\n");
+      print_rtl_single (dump_file, PATTERN (rinsn));
+    }
+}
+
+static bool
+change_insn (function_info *ssa, insn_change change, insn_info *insn,
+	     rtx new_pat)
+{
+  rtx_insn *rinsn = insn->rtl ();
+  auto attempt = ssa->new_change_attempt ();
+  if (!restrict_movement (change))
+    return false;
+
+  if (dump_file)
+    {
+      fprintf (dump_file, "\nChange PATTERN of insn %d from:\n",
+	       INSN_UID (rinsn));
+      print_rtl_single (dump_file, PATTERN (rinsn));
+      if (dump_flags & TDF_DETAILS)
+	{
+	  fprintf (dump_file, "RTL_SSA info:\n");
+	  pretty_printer pp;
+	  pp.buffer->stream = dump_file;
+	  insn->print_full (&pp);
+	  pp_printf (&pp, "\n");
+	  pp_flush (&pp);
+	}
+    }
+
+  insn_change_watermark watermark;
+  validate_change (rinsn, &PATTERN (rinsn), new_pat, true);
+
+  /* These routines report failures themselves.  */
+  if (!recog (attempt, change) || !change_is_worthwhile (change, false))
+    return false;
+  confirm_change_group ();
+  ssa->change_insn (change);
+
+  if (dump_file)
+    {
+      fprintf (dump_file, "\nto:\n");
+      print_rtl_single (dump_file, PATTERN (rinsn));
+      if (dump_flags & TDF_DETAILS)
+	{
+	  fprintf (dump_file, "RTL_SSA info:\n");
+	  pretty_printer pp;
+	  pp.buffer->stream = dump_file;
+	  insn->print_full (&pp);
+	  pp_printf (&pp, "\n");
+	  pp_flush (&pp);
+	}
+    }
+  return true;
+}
+
+avl_info::avl_info (rtx value_in, set_info *source_in)
+  : m_value (value_in), m_source (source_in)
+{}
+
+avl_info &
+avl_info::operator= (const avl_info &other)
+{
+  m_value = other.get_value ();
+  m_source = other.get_source ();
+  return *this;
+}
+
+bool
+avl_info::operator== (const avl_info &other) const
+{
+  if (!m_value)
+    return !other.get_value ();
+  if (!other.get_value ())
+    return false;
+
+  /* It's safe to consider they are equal if their RTX value are
+     strictly the same.  */
+  if (m_value == other.get_value ())
+    return true;
+
+  if (GET_CODE (m_value) != GET_CODE (other.get_value ()))
+    return false;
+
+  /* Handle CONST_INT AVL.  */
+  if (CONST_INT_P (m_value))
+    return INTVAL (m_value) == INTVAL (other.get_value ());
+
+  /* Handle VLMAX AVL.  */
+  if (vlmax_avl_p (m_value))
+    return vlmax_avl_p (other.get_value ());
+
+  /* TODO: So far we only support VLMAX (AVL=zero) comparison,
+     we will support non-VLMAX AVL in the future.  */
+  return false;
+}
+
+bool
+avl_info::operator!= (const avl_info &other) const
+{
+  return !(*this == other);
+}
+
+/* Initialize VL/VTYPE information.  */
+vl_vtype_info::vl_vtype_info (avl_info avl_in, uint8_t sew_in,
+			      enum vlmul_type vlmul_in, uint8_t ratio_in,
+			      bool ta_in, bool ma_in)
+  : m_avl (avl_in), m_sew (sew_in), m_vlmul (vlmul_in), m_ratio (ratio_in),
+    m_ta (ta_in), m_ma (ma_in)
+{
+  gcc_assert (valid_sew_p (m_sew) && "Unexpected SEW");
+}
+
+bool
+vl_vtype_info::operator== (const vl_vtype_info &other) const
+{
+  return m_avl == other.get_avl_info () && m_sew == other.get_sew ()
+	 && m_vlmul == other.get_vlmul () && m_ta == other.get_ta ()
+	 && m_ma == other.get_ma () && m_ratio == other.get_ratio ();
+}
+
+bool
+vl_vtype_info::operator!= (const vl_vtype_info &other) const
+{
+  return !(*this == other);
+}
+
+bool
+vl_vtype_info::has_non_zero_avl () const
+{
+  if (has_avl_imm ())
+    return INTVAL (get_avl ()) > 0;
+  if (has_avl_reg ())
+    return vlmax_avl_p (get_avl ());
+  return false;
+}
+
+bool
+vl_vtype_info::same_avl_p (const vl_vtype_info &other) const
+{
+  return get_avl_info () == other.get_avl_info ();
+}
+
+bool
+vl_vtype_info::same_vtype_p (const vl_vtype_info &other) const
+{
+  return get_sew () == other.get_sew () && get_vlmul () == other.get_vlmul ()
+	 && get_ta () == other.get_ta () && get_ma () == other.get_ma ();
+}
+
+bool
+vl_vtype_info::same_vlmax_p (const vl_vtype_info &other) const
+{
+  return get_ratio () == other.get_ratio ();
+}
+
+/* Compare the compatibility between Dem1 and Dem2.
+   If Dem1 > Dem2, Dem1 has bigger compatibility then Dem2
+   meaning Dem1 is easier be compatible with others than Dem2
+   or Dem2 is stricter than Dem1.
+   For example, Dem1 (demand SEW + LMUL) > Dem2 (demand RATIO).  */
+bool
+vector_insn_info::operator> (const vector_insn_info &other) const
+{
+  if (other.compatible_p (static_cast<const vl_vtype_info &> (*this))
+      && !this->compatible_p (static_cast<const vl_vtype_info &> (other)))
+    return true;
+  return false;
+}
+
+bool
+vector_insn_info::operator>= (const vector_insn_info &other) const
+{
+  if (*this > other)
+    return true;
+
+  if (*this == other)
+    return true;
+
+  if (!compatible_p (other))
+    return false;
+
+  if (!demand_p (DEMAND_AVL) && other.demand_p (DEMAND_AVL))
+    return false;
+
+  if (same_vlmax_p (other))
+    {
+      if (demand_p (DEMAND_RATIO) && !other.demand_p (DEMAND_RATIO)
+	  && (get_sew () != other.get_sew ()
+	      || get_vlmul () != other.get_vlmul ()))
+	return false;
+
+      if (get_sew () == other.get_sew () && get_vlmul () == other.get_vlmul ())
+	{
+	  if (demand_p (DEMAND_RATIO) && !other.demand_p (DEMAND_RATIO))
+	    return false;
+	}
+    }
+
+  if (demand_p (DEMAND_TAIL_POLICY) && !other.demand_p (DEMAND_TAIL_POLICY)
+      && get_ta () != other.get_ta ())
+    return false;
+
+  if (demand_p (DEMAND_MASK_POLICY) && !other.demand_p (DEMAND_MASK_POLICY)
+      && get_ma () != other.get_ma ())
+    return false;
+
+  return true;
+}
+
+bool
+vector_insn_info::operator== (const vector_insn_info &other) const
+{
+  gcc_assert (!uninit_p () && !other.uninit_p ()
+	      && "Uninitialization should not happen");
+
+  /* Empty is only equal to another Empty.  */
+  if (empty_p ())
+    return other.empty_p ();
+  if (other.empty_p ())
+    return empty_p ();
+
+  /* Unknown is only equal to another Unknown.  */
+  if (unknown_p ())
+    return other.unknown_p ();
+  if (other.unknown_p ())
+    return unknown_p ();
+
+  for (size_t i = 0; i < NUM_DEMAND; i++)
+    if (m_demands[i] != other.demand_p ((enum demand_type) i))
+      return false;
+
+  if (m_insn != other.get_insn ())
+    return false;
+  if (m_dirty_pat != other.get_dirty_pat ())
+    return false;
+
+  if (!same_avl_p (other))
+    return false;
+
+  /* If the full VTYPE is valid, check that it is the same.  */
+  return same_vtype_p (other);
+}
+
+void
+vector_insn_info::parse_insn (rtx_insn *rinsn)
+{
+  *this = vector_insn_info ();
+  if (!NONDEBUG_INSN_P (rinsn))
+    return;
+  if (!has_vtype_op (rinsn))
+    return;
+  m_state = VALID;
+  extract_insn_cached (rinsn);
+  const rtx avl = recog_data.operand[get_attr_vl_op_idx (rinsn)];
+  m_avl = avl_info (avl, nullptr);
+  m_sew = ::get_sew (rinsn);
+  m_vlmul = ::get_vlmul (rinsn);
+  m_ta = tail_agnostic_p (rinsn);
+  m_ma = mask_agnostic_p (rinsn);
+}
+
+void
+vector_insn_info::parse_insn (insn_info *insn)
+{
+  *this = vector_insn_info ();
+
+  /* Return if it is debug insn for the consistency with optimize == 0.  */
+  if (insn->is_debug_insn ())
+    return;
+
+  /* We set it as unknown since we don't what will happen in CALL or ASM.  */
+  if (insn->is_call () || insn->is_asm ())
+    {
+      set_unknown ();
+      return;
+    }
+
+  /* If this is something that updates VL/VTYPE that we don't know about, set
+     the state to unknown.  */
+  if (!vector_config_insn_p (insn->rtl ())
+      && (find_access (insn->defs (), VL_REGNUM)
+	  || find_access (insn->defs (), VTYPE_REGNUM)))
+    {
+      set_unknown ();
+      return;
+    }
+
+  if (!vector_config_insn_p (insn->rtl ()) && !has_vtype_op (insn->rtl ()))
+    return;
+
+  /* Warning: This function has to work on both the lowered (i.e. post
+     emit_local_forward_vsetvls) and pre-lowering forms.  The main implication
+     of this is that it can't use the value of a SEW, VL, or Policy operand as
+     they might be stale after lowering.  */
+  vl_vtype_info::operator= (get_vl_vtype_info (insn));
+  m_insn = insn;
+  m_state = VALID;
+  if (vector_config_insn_p (insn->rtl ()))
+    {
+      m_demands[DEMAND_AVL] = true;
+      m_demands[DEMAND_RATIO] = true;
+      return;
+    }
+
+  if (has_vl_op (insn->rtl ()))
+    m_demands[DEMAND_AVL] = true;
+
+  if (get_attr_ratio (insn->rtl ()) != INVALID_ATTRIBUTE)
+    m_demands[DEMAND_RATIO] = true;
+  else
+    {
+      /* TODO: By default, if it doesn't demand RATIO, we set it
+	 demand SEW && LMUL both. Some instructions may demand SEW
+	 only and ignore LMUL, will fix it later.  */
+      m_demands[DEMAND_SEW] = true;
+      m_demands[DEMAND_LMUL] = true;
+    }
+
+  if (get_attr_ta (insn->rtl ()) != INVALID_ATTRIBUTE)
+    m_demands[DEMAND_TAIL_POLICY] = true;
+  if (get_attr_ma (insn->rtl ()) != INVALID_ATTRIBUTE)
+    m_demands[DEMAND_MASK_POLICY] = true;
+}
+
+void
+vector_insn_info::demand_vl_vtype ()
+{
+  m_state = VALID;
+  m_demands[DEMAND_AVL] = true;
+  m_demands[DEMAND_SEW] = true;
+  m_demands[DEMAND_LMUL] = true;
+  m_demands[DEMAND_TAIL_POLICY] = true;
+  m_demands[DEMAND_MASK_POLICY] = true;
+}
+
+bool
+vector_insn_info::compatible_p (const vector_insn_info &other) const
+{
+  gcc_assert (valid_or_dirty_p () && other.valid_or_dirty_p ()
+	      && "Can't compare invalid demanded infos");
+
+  /* Check SEW.  */
+  if (demand_p (DEMAND_SEW) && other.demand_p (DEMAND_SEW)
+      && get_sew () != other.get_sew ())
+    return false;
+
+  /* Check LMUL.  */
+  if (demand_p (DEMAND_LMUL) && other.demand_p (DEMAND_LMUL)
+      && get_vlmul () != other.get_vlmul ())
+    return false;
+
+  /* Check RATIO.  */
+  if (demand_p (DEMAND_RATIO) && other.demand_p (DEMAND_RATIO)
+      && get_ratio () != other.get_ratio ())
+    return false;
+  if (demand_p (DEMAND_RATIO) && (other.get_sew () || other.get_vlmul ())
+      && get_ratio () != other.get_ratio ())
+    return false;
+  if (other.demand_p (DEMAND_RATIO) && (get_sew () || get_vlmul ())
+      && get_ratio () != other.get_ratio ())
+    return false;
+
+  if (demand_p (DEMAND_TAIL_POLICY) && other.demand_p (DEMAND_TAIL_POLICY)
+      && get_ta () != other.get_ta ())
+    return false;
+  if (demand_p (DEMAND_MASK_POLICY) && other.demand_p (DEMAND_MASK_POLICY)
+      && get_ma () != other.get_ma ())
+    return false;
+
+  if (demand_p (DEMAND_AVL) && other.demand_p (DEMAND_AVL))
+    return m_avl == other.get_avl_info ();
+
+  return true;
+}
+
+bool
+vector_insn_info::compatible_avl_p (const vl_vtype_info &other) const
+{
+  gcc_assert (valid_or_dirty_p () && "Can't compare invalid vl_vtype_info");
+  gcc_assert (!unknown_p () && "Can't compare AVL in unknown state");
+  if (!demand_p (DEMAND_AVL))
+    return true;
+  return get_avl_info () == other.get_avl_info ();
+}
+
+bool
+vector_insn_info::compatible_vtype_p (const vl_vtype_info &other) const
+{
+  gcc_assert (valid_or_dirty_p () && "Can't compare invalid vl_vtype_info");
+  gcc_assert (!unknown_p () && "Can't compare VTYPE in unknown state");
+  if (demand_p (DEMAND_SEW) && m_sew != other.get_sew ())
+    return false;
+  if (demand_p (DEMAND_LMUL) && m_vlmul != other.get_vlmul ())
+    return false;
+  if (demand_p (DEMAND_RATIO) && m_ratio != other.get_ratio ())
+    return false;
+  if (demand_p (DEMAND_TAIL_POLICY) && m_ta != other.get_ta ())
+    return false;
+  if (demand_p (DEMAND_MASK_POLICY) && m_ma != other.get_ma ())
+    return false;
+  return true;
+}
+
+/* Determine whether the vector instructions requirements represented by
+   Require are compatible with the previous vsetvli instruction represented
+   by this.  INSN is the instruction whose requirements we're considering.  */
+bool
+vector_insn_info::compatible_p (const vl_vtype_info &curr_info) const
+{
+  gcc_assert (!uninit_p () && "Can't handle uninitialized info");
+  if (empty_p ())
+    return false;
+
+  /* Nothing is compatible with Unknown.  */
+  if (unknown_p ())
+    return false;
+
+  /* If the instruction doesn't need an AVLReg and the SEW matches, consider
+     it compatible.  */
+  if (!demand_p (DEMAND_AVL))
+    if (m_sew == curr_info.get_sew ())
+      return true;
+
+  return compatible_avl_p (curr_info) && compatible_vtype_p (curr_info);
+}
+
+vector_insn_info
+vector_insn_info::merge (const vector_insn_info &merge_info,
+			 bool across_bb_p = false) const
+{
+  gcc_assert (this->compatible_p (merge_info)
+	      && "Can't merge incompatible demanded infos");
+
+  vector_insn_info new_info;
+  new_info.demand_vl_vtype ();
+
+  if (dirty_p ())
+    {
+      gcc_assert (across_bb_p);
+      if (demand_p (DEMAND_AVL))
+	new_info.set_insn (get_insn ());
+      else
+	new_info.set_insn (merge_info.get_insn ());
+    }
+  else
+    {
+      if (across_bb_p)
+	new_info.set_insn (get_insn ());
+      else
+	new_info.set_insn (merge_info.get_insn ());
+    }
+
+  new_info.set_dirty_pat (merge_info.get_dirty_pat ());
+
+  if (!demand_p (DEMAND_AVL) && !merge_info.demand_p (DEMAND_AVL))
+    new_info.undemand (DEMAND_AVL);
+  if (!demand_p (DEMAND_SEW) && !merge_info.demand_p (DEMAND_SEW))
+    new_info.undemand (DEMAND_SEW);
+  if (!demand_p (DEMAND_LMUL) && !merge_info.demand_p (DEMAND_LMUL))
+    new_info.undemand (DEMAND_LMUL);
+
+  if (!demand_p (DEMAND_TAIL_POLICY)
+      && !merge_info.demand_p (DEMAND_TAIL_POLICY))
+    new_info.undemand (DEMAND_TAIL_POLICY);
+  if (!demand_p (DEMAND_MASK_POLICY)
+      && !merge_info.demand_p (DEMAND_MASK_POLICY))
+    new_info.undemand (DEMAND_MASK_POLICY);
+
+  if (merge_info.demand_p (DEMAND_AVL))
+    new_info.set_avl_info (merge_info.get_avl_info ());
+  else if (demand_p (DEMAND_AVL))
+    new_info.set_avl_info (get_avl_info ());
+
+  if (merge_info.demand_p (DEMAND_SEW))
+    new_info.set_sew (merge_info.get_sew ());
+  else if (demand_p (DEMAND_SEW))
+    new_info.set_sew (get_sew ());
+
+  if (merge_info.demand_p (DEMAND_LMUL))
+    new_info.set_vlmul (merge_info.get_vlmul ());
+  else if (demand_p (DEMAND_LMUL))
+    new_info.set_vlmul (get_vlmul ());
+
+  if (!new_info.demand_p (DEMAND_SEW) && !new_info.demand_p (DEMAND_LMUL))
+    {
+      if (demand_p (DEMAND_RATIO) || merge_info.demand_p (DEMAND_RATIO))
+	new_info.demand (DEMAND_RATIO);
+      /* Even though we don't demand_p SEW && VLMUL in this case, we still
+       * need them.  */
+      if (merge_info.demand_p (DEMAND_RATIO))
+	{
+	  new_info.set_sew (merge_info.get_sew ());
+	  new_info.set_vlmul (merge_info.get_vlmul ());
+	  new_info.set_ratio (merge_info.get_ratio ());
+	}
+      else if (demand_p (DEMAND_RATIO))
+	{
+	  new_info.set_sew (get_sew ());
+	  new_info.set_vlmul (get_vlmul ());
+	  new_info.set_ratio (get_ratio ());
+	}
+    }
+  else
+    {
+      /* when get_attr_ratio is invalid, this kind of instructions
+	 doesn't care about ratio. However, we still need this value
+	 in demand_p info backward analysis.  */
+      new_info.set_ratio (
+	calculate_ratio (new_info.get_sew (), new_info.get_vlmul ()));
+    }
+
+  if (merge_info.demand_p (DEMAND_TAIL_POLICY))
+    new_info.set_ta (merge_info.get_ta ());
+  else if (demand_p (DEMAND_TAIL_POLICY))
+    new_info.set_ta (get_ta ());
+  else
+    new_info.set_ta (get_default_ta ());
+
+  if (merge_info.demand_p (DEMAND_MASK_POLICY))
+    new_info.set_ma (merge_info.get_ma ());
+  else if (demand_p (DEMAND_MASK_POLICY))
+    new_info.set_ma (get_ma ());
+  else
+    new_info.set_ma (get_default_ma ());
+
+  return new_info;
+}
+
+void
+vector_insn_info::dump (FILE *file) const
+{
+  fprintf (file, "[");
+  if (uninit_p ())
+    fprintf (file, "UNINITIALIZED,");
+  else if (valid_p ())
+    fprintf (file, "VALID,");
+  else if (unknown_p ())
+    fprintf (file, "UNKNOWN,");
+  else if (empty_p ())
+    fprintf (file, "EMPTY,");
+  else
+    fprintf (file, "DIRTY,");
+
+  fprintf (file, "Demand field={%d(VL),", demand_p (DEMAND_AVL));
+  fprintf (file, "%d(SEW),", demand_p (DEMAND_SEW));
+  fprintf (file, "%d(LMUL),", demand_p (DEMAND_LMUL));
+  fprintf (file, "%d(RATIO),", demand_p (DEMAND_RATIO));
+  fprintf (file, "%d(TAIL_POLICY),", demand_p (DEMAND_TAIL_POLICY));
+  fprintf (file, "%d(MASK_POLICY)}\n", demand_p (DEMAND_MASK_POLICY));
+
+  fprintf (file, "AVL=");
+  print_rtl_single (file, get_avl ());
+  fprintf (file, "SEW=%d,", get_sew ());
+  fprintf (file, "VLMUL=%d,", get_vlmul ());
+  fprintf (file, "RATIO=%d,", get_ratio ());
+  fprintf (file, "TAIL_POLICY=%d,", get_ta ());
+  fprintf (file, "MASK_POLICY=%d", get_ma ());
+  fprintf (file, "]\n");
+
+  if (valid_p ())
+    {
+      if (get_insn ())
+	{
+	  fprintf (file, "RTL_SSA insn_info=");
+	  pretty_printer pp;
+	  pp.buffer->stream = file;
+	  get_insn ()->print_full (&pp);
+	  pp_printf (&pp, "\n");
+	  pp_flush (&pp);
+	}
+      if (get_dirty_pat ())
+	{
+	  fprintf (file, "Dirty RTL Pattern=");
+	  print_rtl_single (file, get_dirty_pat ());
+	}
+    }
+}
+
+vector_infos_manager::vector_infos_manager ()
+{
+  vector_edge_list = nullptr;
+  vector_kill = nullptr;
+  vector_del = nullptr;
+  vector_insert = nullptr;
+  vector_antic = nullptr;
+  vector_transp = nullptr;
+  vector_comp = nullptr;
+  vector_avin = nullptr;
+  vector_avout = nullptr;
+  vector_insn_infos.safe_grow (get_max_uid ());
+  vector_block_infos.safe_grow (last_basic_block_for_fn (cfun));
+  if (!optimize)
+    {
+      basic_block cfg_bb;
+      rtx_insn *rinsn;
+      FOR_ALL_BB_FN (cfg_bb, cfun)
+	{
+	  vector_block_infos[cfg_bb->index].local_dem = vector_insn_info ();
+	  vector_block_infos[cfg_bb->index].reaching_out = vector_insn_info ();
+	  FOR_BB_INSNS (cfg_bb, rinsn)
+	    vector_insn_infos[INSN_UID (rinsn)].parse_insn (rinsn);
+	}
+    }
+  else
+    {
+      for (const bb_info *bb : crtl->ssa->bbs ())
+	{
+	  vector_block_infos[bb->index ()].local_dem = vector_insn_info ();
+	  vector_block_infos[bb->index ()].reaching_out = vector_insn_info ();
+	  for (insn_info *insn : bb->real_insns ())
+	    vector_insn_infos[insn->uid ()].parse_insn (insn);
+	}
+    }
+}
+
+void
+vector_infos_manager::create_expr (vector_insn_info &info)
+{
+  for (size_t i = 0; i < vector_exprs.length (); i++)
+    if (*vector_exprs[i] == info)
+      return;
+  vector_exprs.safe_push (&info);
+}
+
+size_t
+vector_infos_manager::get_expr_id (const vector_insn_info &info) const
+{
+  for (size_t i = 0; i < vector_exprs.length (); i++)
+    if (*vector_exprs[i] == info)
+      return i;
+  gcc_unreachable ();
+}
+
+auto_vec<size_t>
+vector_infos_manager::get_all_available_exprs (
+  const vector_insn_info &info) const
+{
+  auto_vec<size_t> available_list;
+  for (size_t i = 0; i < vector_exprs.length (); i++)
+    if (info >= *vector_exprs[i])
+      available_list.safe_push (i);
+  return available_list;
+}
+
+bool
+vector_infos_manager::all_same_ratio_p (sbitmap bitdata) const
+{
+  if (bitmap_empty_p (bitdata))
+    return false;
+
+  int ratio = -1;
+  unsigned int bb_index;
+  sbitmap_iterator sbi;
+
+  EXECUTE_IF_SET_IN_BITMAP (bitdata, 0, bb_index, sbi)
+  {
+    if (ratio == -1)
+      ratio = vector_exprs[bb_index]->get_ratio ();
+    else if (vector_exprs[bb_index]->get_ratio () != ratio)
+      return false;
+  }
+  return true;
+}
+
+size_t
+vector_infos_manager::expr_set_num (sbitmap bitdata) const
+{
+  size_t count = 0;
+  for (size_t i = 0; i < vector_exprs.length (); i++)
+    if (bitmap_bit_p (bitdata, i))
+      count++;
+  return count;
+}
+
+void
+vector_infos_manager::release (void)
+{
+  if (!vector_insn_infos.is_empty ())
+    vector_insn_infos.release ();
+  if (!vector_block_infos.is_empty ())
+    vector_block_infos.release ();
+  if (!vector_exprs.is_empty ())
+    vector_exprs.release ();
+
+  if (optimize > 0)
+    {
+      /* Finished. Free up all the things we've allocated.  */
+      free_edge_list (vector_edge_list);
+      sbitmap_vector_free (vector_del);
+      sbitmap_vector_free (vector_insert);
+      sbitmap_vector_free (vector_kill);
+      sbitmap_vector_free (vector_antic);
+      sbitmap_vector_free (vector_transp);
+      sbitmap_vector_free (vector_comp);
+      sbitmap_vector_free (vector_avin);
+      sbitmap_vector_free (vector_avout);
+    }
+}
+
+void
+vector_infos_manager::dump (FILE *file) const
+{
+  basic_block cfg_bb;
+  rtx_insn *rinsn;
+
+  fprintf (file, "\n");
+  FOR_ALL_BB_FN (cfg_bb, cfun)
+    {
+      fprintf (file, "Local vector info of <bb %d>:\n", cfg_bb->index);
+      fprintf (file, "<HEADER>=");
+      vector_block_infos[cfg_bb->index].local_dem.dump (file);
+      FOR_BB_INSNS (cfg_bb, rinsn)
+	{
+	  if (!NONDEBUG_INSN_P (rinsn) || !has_vtype_op (rinsn))
+	    continue;
+	  fprintf (file, "<insn %d>=", INSN_UID (rinsn));
+	  const auto &info = vector_insn_infos[INSN_UID (rinsn)];
+	  info.dump (file);
+	}
+      fprintf (file, "<FOOTER>=");
+      vector_block_infos[cfg_bb->index].reaching_out.dump (file);
+      fprintf (file, "\n\n");
+    }
+
+  fprintf (file, "\n");
+  FOR_ALL_BB_FN (cfg_bb, cfun)
+    {
+      fprintf (file, "Local properties of <bb %d>:\n", cfg_bb->index);
+
+      fprintf (file, "<ANTLOC>=");
+      if (vector_antic == nullptr)
+	fprintf (file, "(nil)\n");
+      else
+	dump_bitmap_file (file, vector_antic[cfg_bb->index]);
+
+      fprintf (file, "<AVLOC>=");
+      if (vector_comp == nullptr)
+	fprintf (file, "(nil)\n");
+      else
+	dump_bitmap_file (file, vector_comp[cfg_bb->index]);
+
+      fprintf (file, "<TRANSP>=");
+      if (vector_transp == nullptr)
+	fprintf (file, "(nil)\n");
+      else
+	dump_bitmap_file (file, vector_transp[cfg_bb->index]);
+
+      fprintf (file, "<KILL>=");
+      if (vector_kill == nullptr)
+	fprintf (file, "(nil)\n");
+      else
+	dump_bitmap_file (file, vector_kill[cfg_bb->index]);
+    }
+
+  fprintf (file, "\n");
+  FOR_ALL_BB_FN (cfg_bb, cfun)
+    {
+      fprintf (file, "Global LCM (Lazy code motion) result of <bb %d>:\n",
+	       cfg_bb->index);
+
+      fprintf (file, "<AVIN>=");
+      if (vector_avin == nullptr)
+	fprintf (file, "(nil)\n");
+      else
+	dump_bitmap_file (file, vector_avin[cfg_bb->index]);
+
+      fprintf (file, "<AVOUT>=");
+      if (vector_avout == nullptr)
+	fprintf (file, "(nil)\n");
+      else
+	dump_bitmap_file (file, vector_avout[cfg_bb->index]);
+
+      fprintf (file, "<DELETE>=");
+      if (vector_del == nullptr)
+	fprintf (file, "(nil)\n");
+      else
+	dump_bitmap_file (file, vector_del[cfg_bb->index]);
+    }
+
+  fprintf (file, "\nGlobal LCM (Lazy code motion) INSERT info:\n");
+  for (size_t i = 0; i < vector_exprs.length (); i++)
+    {
+      for (int ed = 0; ed < NUM_EDGES (vector_edge_list); ed++)
+	{
+	  edge eg = INDEX_EDGE (vector_edge_list, ed);
+	  if (bitmap_bit_p (vector_insert[ed], i))
+	    fprintf (dump_file,
+		     "INSERT edge %d from bb %d to bb %d for VSETVL "
+		     "expr[%ld]\n",
+		     ed, eg->src->index, eg->dest->index, i);
+	}
+    }
+}
+
+const pass_data pass_data_vsetvl = {
+  RTL_PASS,	 /* type */
+  "vsetvl",	 /* name */
+  OPTGROUP_NONE, /* optinfo_flags */
+  TV_NONE,	 /* tv_id */
+  0,		 /* properties_required */
+  0,		 /* properties_provided */
+  0,		 /* properties_destroyed */
+  0,		 /* todo_flags_start */
+  0,		 /* todo_flags_finish */
+};
+
+class pass_vsetvl : public rtl_opt_pass
+{
+private:
+  class vector_infos_manager *m_vector_manager;
+
+  void simple_vsetvl (void) const;
+  void lazy_vsetvl (void);
+
+  /* Phase 1.  */
+  void compute_local_backward_infos (const bb_info *);
+
+  /* Phase 2.  */
+  bool need_vsetvl (const vector_insn_info &, const vector_insn_info &) const;
+  void transfer_before (vector_insn_info &, insn_info *) const;
+  void transfer_after (vector_insn_info &, insn_info *) const;
+  void emit_local_forward_vsetvls (const bb_info *);
+
+  /* Phase 3.  */
+  void merge_successors (const basic_block, const basic_block);
+  void compute_global_backward_infos (void);
+
+  /* Phase 4.  */
+  void prune_expressions (void);
+  void compute_local_properties (void);
+  bool can_refine_vsetvl_p (const basic_block, uint8_t) const;
+  void refine_vsetvls (void) const;
+  void cleanup_vsetvls (void);
+  bool commit_vsetvls (void);
+  void pre_vsetvl (void);
+
+  /* Phase 5.  */
+  void cleanup_insns (void) const;
+
+  void init (void);
+  void done (void);
+
+public:
+  pass_vsetvl (gcc::context *ctxt) : rtl_opt_pass (pass_data_vsetvl, ctxt) {}
+
+  /* opt_pass methods: */
+  virtual bool gate (function *) final override { return TARGET_VECTOR; }
+  virtual unsigned int execute (function *) final override;
+}; // class pass_vsetvl
+
+/* Simple m_vsetvl_insert vsetvl for optimize == 0.  */
+void
+pass_vsetvl::simple_vsetvl (void) const
+{
+  if (dump_file)
+    fprintf (dump_file,
+	     "\nEntering Simple VSETVL PASS and Handling %d basic blocks for "
+	     "function:%s\n",
+	     n_basic_blocks_for_fn (cfun), function_name (cfun));
+
+  basic_block cfg_bb;
+  rtx_insn *rinsn;
+  FOR_ALL_BB_FN (cfg_bb, cfun)
+    {
+      FOR_BB_INSNS (cfg_bb, rinsn)
+	{
+	  if (!NONDEBUG_INSN_P (rinsn))
+	    continue;
+	  if (has_vtype_op (rinsn))
+	    {
+	      const auto info
+		= m_vector_manager->vector_insn_infos[INSN_UID (rinsn)];
+	      emit_vsetvl_insn (VSETVL_DISCARD_RESULT, EMIT_BEFORE, info,
+				NULL_RTX, rinsn);
+	    }
+	}
+    }
+}
+
+/* Compute demanded information by backward data-flow analysis.  */
+void
+pass_vsetvl::compute_local_backward_infos (const bb_info *bb)
+{
+  vector_insn_info change;
+  change.set_empty ();
+
+  auto &block_info = m_vector_manager->vector_block_infos[bb->index ()];
+  block_info.reaching_out = change;
+
+  for (insn_info *insn : bb->reverse_real_nondebug_insns ())
+    {
+      auto &info = m_vector_manager->vector_insn_infos[insn->uid ()];
+
+      if (info.uninit_p ())
+	/* If it is uninitialized, propagate it directly.  */
+	info = change;
+      else if (info.unknown_p ())
+	change = info;
+      else
+	{
+	  gcc_assert (info.valid_p () && "Unexpected Invalid demanded info");
+	  if (change.valid_p () && change.compatible_p (info))
+	    info = change.merge (info);
+	  change = info;
+	}
+    }
+
+  block_info.local_dem = change;
+  if (block_info.local_dem.empty_p ())
+    block_info.reaching_out = block_info.local_dem;
+}
+
+/* Return true if a dem_info is required to transition from curr_info to
+   require before INSN.  */
+bool
+pass_vsetvl::need_vsetvl (const vector_insn_info &require,
+			  const vector_insn_info &curr_info) const
+{
+  if (!curr_info.valid_p () || curr_info.unknown_p () || curr_info.uninit_p ())
+    return true;
+
+  if (require.compatible_p (curr_info))
+    return false;
+
+  return true;
+}
+
+/* Given an incoming state reaching INSN, modifies that state so that it is
+   minimally compatible with INSN.  The resulting state is guaranteed to be
+   semantically legal for INSN, but may not be the state requested by INSN.  */
+void
+pass_vsetvl::transfer_before (vector_insn_info &info, insn_info *insn) const
+{
+  if (!has_vtype_op (insn->rtl ()))
+    return;
+
+  const vector_insn_info require
+    = m_vector_manager->vector_insn_infos[insn->uid ()];
+  if (info.valid_p () && !need_vsetvl (require, info))
+    return;
+  info = require;
+}
+
+/* Given a state with which we evaluated insn (see transfer_before above for why
+   this might be different that the state insn requested), modify the state to
+   reflect the changes insn might make.  */
+void
+pass_vsetvl::transfer_after (vector_insn_info &info, insn_info *insn) const
+{
+  if (vector_config_insn_p (insn->rtl ()))
+    {
+      info = m_vector_manager->vector_insn_infos[insn->uid ()];
+      return;
+    }
+
+  /* TODO: Support fault first load info update VL in the future.  */
+
+  /* If this is something that updates VL/VTYPE that we don't know about, set
+     the state to unknown.  */
+  if (insn->is_call () || insn->is_asm ()
+      || find_access (insn->defs (), VL_REGNUM)
+      || find_access (insn->defs (), VTYPE_REGNUM))
+    info = vector_insn_info::get_unknown ();
+}
+
+/* Emit vsetvl within each block by forward data-flow analysis.  */
+void
+pass_vsetvl::emit_local_forward_vsetvls (const bb_info *bb)
+{
+  auto &block_info = m_vector_manager->vector_block_infos[bb->index ()];
+  if (block_info.local_dem.empty_p ())
+    return;
+
+  vector_insn_info curr_info;
+  for (insn_info *insn : bb->real_nondebug_insns ())
+    {
+      const vector_insn_info prev_info = curr_info;
+      transfer_before (curr_info, insn);
+
+      if (has_vtype_op (insn->rtl ()))
+	{
+	  if (static_cast<const vl_vtype_info &> (prev_info)
+	      != static_cast<const vl_vtype_info &> (curr_info))
+	    {
+	      const auto require
+		= m_vector_manager->vector_insn_infos[insn->uid ()];
+	      if (!require.compatible_p (
+		    static_cast<const vl_vtype_info &> (prev_info)))
+		insert_vsetvl (EMIT_BEFORE, insn->rtl (), require, prev_info);
+	    }
+	}
+
+      transfer_after (curr_info, insn);
+    }
+
+  block_info.reaching_out = curr_info;
+}
+
+/* Merge all successors of Father except child node.  */
+void
+pass_vsetvl::merge_successors (const basic_block father,
+			       const basic_block child)
+{
+  edge e;
+  edge_iterator ei;
+  auto &father_info = m_vector_manager->vector_block_infos[father->index];
+  gcc_assert (father_info.local_dem.dirty_p ()
+	      || father_info.local_dem.empty_p ());
+  gcc_assert (father_info.reaching_out.dirty_p ()
+	      || father_info.reaching_out.empty_p ());
+
+  FOR_EACH_EDGE (e, ei, father->succs)
+    {
+      const basic_block succ = e->dest;
+      if (succ->index == child->index)
+	continue;
+
+      const auto succ_info
+	= m_vector_manager->vector_block_infos[succ->index].local_dem;
+
+      if (!succ_info.valid_p ())
+	continue;
+
+      vector_insn_info new_info;
+      if (father_info.reaching_out.dirty_p ())
+	{
+	  if (!father_info.reaching_out.compatible_p (succ_info))
+	    continue;
+
+	  new_info = succ_info.merge (father_info.reaching_out, true);
+	}
+      else
+	new_info = succ_info;
+
+      new_info.set_dirty ();
+      rtx new_pat = gen_vsetvl_pat (new_info.get_insn ()->rtl (), new_info);
+      new_info.set_dirty_pat (new_pat);
+
+      father_info.local_dem = new_info;
+      father_info.reaching_out = new_info;
+    }
+}
+
+/* Compute global backward demanded info.  */
+void
+pass_vsetvl::compute_global_backward_infos (void)
+{
+  /* We compute global infos by backward propagation.
+     We want to have better performance in these following cases:
+
+	1. for (size_t i = 0; i < n; i++) {
+	     if (i != cond) {
+	       vint8mf8_t v = *(vint8mf8_t*)(in + i + 100);
+	       *(vint8mf8_t*)(out + i + 100) = v;
+	     } else {
+	       vbool1_t v = *(vbool1_t*)(in + i + 400);
+	       *(vbool1_t*)(out + i + 400) = v;
+	     }
+	   }
+
+	   Since we don't have any RVV instruction in the BEFORE blocks,
+	   LCM fails to optimize such case. We want to backward propagate
+	   them into empty blocks so that we could have better performance
+	   in LCM.
+
+	2. bb 0:
+	     vsetvl e8,mf8 (demand RATIO)
+	   bb 1:
+	     vsetvl e32,mf2 (demand SEW and LMUL)
+	   We backward propagate the first VSETVL into e32,mf2 so that we
+	   could be able to eliminate the second VSETVL in LCM.  */
+
+  for (const bb_info *bb : crtl->ssa->reverse_bbs ())
+    {
+      basic_block cfg_bb = bb->cfg_bb ();
+      const auto &prop
+	= m_vector_manager->vector_block_infos[cfg_bb->index].local_dem;
+
+      /* If there is nothing to propagate, just skip it.  */
+      if (!prop.valid_or_dirty_p ())
+	continue;
+
+      if (!backward_propagate_worthwhile_p (
+	    cfg_bb, m_vector_manager->vector_block_infos[cfg_bb->index]))
+	continue;
+
+      edge e;
+      edge_iterator ei;
+      /* Backward propagate to each predecessor.  */
+      FOR_EACH_EDGE (e, ei, cfg_bb->preds)
+	{
+	  rtx new_pat;
+	  auto &block_info
+	    = m_vector_manager->vector_block_infos[e->src->index];
+
+	  /* We don't propagate through critical edges.  */
+	  if (e->flags & EDGE_COMPLEX)
+	    continue;
+	  if (e->src->index == ENTRY_BLOCK_PTR_FOR_FN (cfun)->index)
+	    continue;
+
+	  if (block_info.reaching_out.unknown_p ())
+	    continue;
+	  else if (block_info.reaching_out.empty_p ())
+	    {
+	      if (!can_backward_propagate_p (crtl->ssa, e->src, prop))
+		continue;
+
+	      if (dominate_probability_p (e))
+		{
+		  rtx new_pat = gen_vsetvl_pat (prop.get_insn ()->rtl (), prop);
+
+		  block_info.reaching_out = prop;
+		  block_info.reaching_out.set_dirty ();
+		  block_info.reaching_out.set_dirty_pat (new_pat);
+		  block_info.local_dem = block_info.reaching_out;
+		}
+
+	      merge_successors (e->src, cfg_bb);
+	    }
+	  else if (block_info.reaching_out.dirty_p ())
+	    {
+	      /* DIRTY -> DIRTY or VALID -> DIRTY.  */
+	      vector_insn_info new_info;
+
+	      if (block_info.reaching_out.compatible_p (prop))
+		{
+		  if (block_info.reaching_out >= prop)
+		    continue;
+		  new_info = block_info.reaching_out.merge (prop, true);
+		}
+	      else
+		{
+		  if (dominate_probability_p (e))
+		    new_info = prop;
+		  else
+		    continue;
+		}
+
+	      rtx new_pat
+		= gen_vsetvl_pat (new_info.get_insn ()->rtl (), new_info);
+	      new_info.set_dirty ();
+	      new_info.set_dirty_pat (new_pat);
+	      block_info.local_dem = new_info;
+	      block_info.reaching_out = new_info;
+	    }
+	  else
+	    {
+	      /* We not only change the info during backward propagation,
+		 but also change the VSETVL instruction.  */
+	      gcc_assert (block_info.reaching_out.valid_p ());
+	      if (!block_info.reaching_out.compatible_p (prop))
+		continue;
+	      if (block_info.reaching_out >= prop)
+		continue;
+
+	      vector_insn_info be_merged = block_info.reaching_out;
+	      if (block_info.local_dem == block_info.reaching_out)
+		be_merged = block_info.local_dem;
+	      vector_insn_info new_info = be_merged.merge (prop, true);
+
+	      rtx_insn *rinsn;
+	      if (vector_config_insn_p (new_info.get_insn ()->rtl ()))
+		{
+		  rinsn = new_info.get_insn ()->rtl ();
+		  gcc_assert (vsetvl_insn_p (rinsn)
+			      && "Can't handle X0, rs1 vsetvli yet");
+		}
+	      else
+		{
+		  gcc_assert (has_vtype_op (new_info.get_insn ()->rtl ()));
+		  rinsn = PREV_INSN (new_info.get_insn ()->rtl ());
+		  gcc_assert (vector_config_insn_p (rinsn));
+		}
+	      new_pat = gen_vsetvl_pat (rinsn, new_info);
+	      change_insn (rinsn, new_pat);
+	      if (block_info.local_dem == block_info.reaching_out)
+		block_info.local_dem = new_info;
+	      block_info.reaching_out = new_info;
+	    }
+	}
+    }
+
+  if (dump_file)
+    {
+      fprintf (dump_file, "\n\nDirty blocks list: ");
+      for (size_t i = 0; i < m_vector_manager->vector_block_infos.length ();
+	   i++)
+	{
+	  if (m_vector_manager->vector_block_infos[i].reaching_out.dirty_p ())
+	    fprintf (dump_file, "%ld ", i);
+	}
+      fprintf (dump_file, "\n\n");
+    }
+}
+
+/* Assemble the candidates expressions for LCM.  */
+void
+pass_vsetvl::prune_expressions (void)
+{
+  for (size_t i = 0; i < m_vector_manager->vector_block_infos.length (); i++)
+    {
+      if (m_vector_manager->vector_block_infos[i].local_dem.valid_or_dirty_p ())
+	m_vector_manager->create_expr (
+	  m_vector_manager->vector_block_infos[i].local_dem);
+      if (m_vector_manager->vector_block_infos[i]
+	    .reaching_out.valid_or_dirty_p ())
+	m_vector_manager->create_expr (
+	  m_vector_manager->vector_block_infos[i].reaching_out);
+    }
+
+  if (dump_file)
+    {
+      fprintf (dump_file, "\nThe total VSETVL expression num = %d\n",
+	       m_vector_manager->vector_exprs.length ());
+      fprintf (dump_file, "Expression List:\n");
+      for (size_t i = 0; i < m_vector_manager->vector_exprs.length (); i++)
+	{
+	  fprintf (dump_file, "Expr[%ld]:\n", i);
+	  m_vector_manager->vector_exprs[i]->dump (dump_file);
+	  fprintf (dump_file, "\n");
+	}
+    }
+}
+
+void
+pass_vsetvl::compute_local_properties (void)
+{
+  /* -  If T is locally available at the end of a block, then T' must be
+	available at the end of the same block. Since some optimization has
+	occurred earlier, T' might not be locally available, however, it must
+	have been previously computed on all paths. As a formula, T at AVLOC(B)
+	implies that T' at AVOUT(B).
+	An "available occurrence" is one that is the last occurrence in the
+	basic block and the operands are not modified by following statements in
+	the basic block [including this insn].
+
+     -  If T is locally anticipated at the beginning of a block, then either
+	T', is locally anticipated or it is already available from previous
+	blocks. As a formula, this means that T at ANTLOC(B) implies that T' at
+	ANTLOC(B) at AVIN(B).
+	An "anticipatable occurrence" is one that is the first occurrence in the
+	basic block, the operands are not modified in the basic block prior
+	to the occurrence and the output is not used between the start of
+	the block and the occurrence.  */
+
+  basic_block cfg_bb;
+  FOR_EACH_BB_FN (cfg_bb, cfun)
+    {
+      int curr_bb_idx = cfg_bb->index;
+      const auto local_dem
+	= m_vector_manager->vector_block_infos[curr_bb_idx].local_dem;
+      const auto reaching_out
+	= m_vector_manager->vector_block_infos[curr_bb_idx].reaching_out;
+
+      if (!local_dem.empty_p ())
+	{
+	  for (size_t i = 0; i < m_vector_manager->vector_exprs.length (); i++)
+	    bitmap_clear_bit (m_vector_manager->vector_transp[curr_bb_idx], i);
+	}
+
+      if (local_dem.valid_or_dirty_p ())
+	{
+	  const insn_info *header_insn = local_dem.get_insn ();
+	  size_t header_index = m_vector_manager->get_expr_id (local_dem);
+	  if (anticipatable_occurrence_p (header_insn, local_dem))
+	    bitmap_set_bit (m_vector_manager->vector_antic[curr_bb_idx],
+			    header_index);
+	}
+
+      if (reaching_out.valid_or_dirty_p ())
+	{
+	  const insn_info *footer_insn = reaching_out.get_insn ();
+	  size_t footer_index = m_vector_manager->get_expr_id (reaching_out);
+	  if (available_occurrence_p (footer_insn, reaching_out))
+	    bitmap_set_bit (m_vector_manager->vector_comp[curr_bb_idx],
+			    footer_index);
+	  auto_vec<size_t> available_list
+	    = m_vector_manager->get_all_available_exprs (reaching_out);
+	  for (size_t i = 0; i < available_list.length (); i++)
+	    bitmap_set_bit (m_vector_manager->vector_comp[curr_bb_idx],
+			    available_list[i]);
+	}
+    }
+
+  /* Compute kill for each basic block using:
+
+     ~(TRANSP | COMP)
+  */
+
+  FOR_EACH_BB_FN (cfg_bb, cfun)
+    {
+      bitmap_ior (m_vector_manager->vector_kill[cfg_bb->index],
+		  m_vector_manager->vector_transp[cfg_bb->index],
+		  m_vector_manager->vector_comp[cfg_bb->index]);
+      bitmap_not (m_vector_manager->vector_kill[cfg_bb->index],
+		  m_vector_manager->vector_kill[cfg_bb->index]);
+    }
+
+  FOR_EACH_BB_FN (cfg_bb, cfun)
+    {
+      edge e;
+      edge_iterator ei;
+
+      /* If the current block is the destination of an abnormal edge, we
+	 kill all trapping (for PRE) and memory (for hoist) expressions
+	 because we won't be able to properly place the instruction on
+	 the edge.  So make them neither anticipatable nor transparent.
+	 This is fairly conservative.
+
+	 ??? For hoisting it may be necessary to check for set-and-jump
+	 instructions here, not just for abnormal edges.  The general problem
+	 is that when an expression cannot not be placed right at the end of
+	 a basic block we should account for any side-effects of a subsequent
+	 jump instructions that could clobber the expression.  It would
+	 be best to implement this check along the lines of
+	 should_hoist_expr_to_dom where the target block is already known
+	 and, hence, there's no need to conservatively prune expressions on
+	 "intermediate" set-and-jump instructions.  */
+      FOR_EACH_EDGE (e, ei, cfg_bb->preds)
+	if (e->flags & EDGE_COMPLEX)
+	  {
+	    bitmap_clear (m_vector_manager->vector_antic[cfg_bb->index]);
+	    bitmap_clear (m_vector_manager->vector_transp[cfg_bb->index]);
+	  }
+    }
+}
+
+/* Return true if VSETVL in the block can be refined as vsetvl zero,zero.  */
+bool
+pass_vsetvl::can_refine_vsetvl_p (const basic_block cfg_bb, uint8_t ratio) const
+{
+  if (!m_vector_manager->all_same_ratio_p (
+	m_vector_manager->vector_avin[cfg_bb->index]))
+    return false;
+
+  size_t expr_id
+    = bitmap_first_set_bit (m_vector_manager->vector_avin[cfg_bb->index]);
+  if (m_vector_manager->vector_exprs[expr_id]->get_ratio () != ratio)
+    return false;
+
+  edge e;
+  edge_iterator ei;
+  bool all_valid_p = true;
+  FOR_EACH_EDGE (e, ei, cfg_bb->preds)
+    {
+      if (bitmap_empty_p (m_vector_manager->vector_avout[e->src->index]))
+	{
+	  all_valid_p = false;
+	  break;
+	}
+    }
+
+  if (!all_valid_p)
+    return false;
+  return true;
+}
+
+/* Optimize athe case like this:
+
+      bb 0:
+	vsetvl 0 a5,zero,e8,mf8
+	insn 0 (demand SEW + LMUL)
+      bb 1:
+	vsetvl 1 a5,zero,e16,mf4
+	insn 1 (demand SEW + LMUL)
+
+   In this case, we should be able to refine
+   vsetvl 1 into vsetvl zero, zero according AVIN.  */
+void
+pass_vsetvl::refine_vsetvls (void) const
+{
+  basic_block cfg_bb;
+  FOR_EACH_BB_FN (cfg_bb, cfun)
+    {
+      auto info = m_vector_manager->vector_block_infos[cfg_bb->index].local_dem;
+      insn_info *insn = info.get_insn ();
+      if (!info.valid_p ())
+	continue;
+
+      rtx_insn *rinsn = insn->rtl ();
+      if (!can_refine_vsetvl_p (cfg_bb, info.get_ratio ()))
+	continue;
+
+      if (!vector_config_insn_p (rinsn))
+	rinsn = PREV_INSN (rinsn);
+      rtx new_pat = gen_vsetvl_pat (VSETVL_VTYPE_CHANGE_ONLY, info, NULL_RTX);
+      change_insn (rinsn, new_pat);
+    }
+}
+
+void
+pass_vsetvl::cleanup_vsetvls ()
+{
+  basic_block cfg_bb;
+  FOR_EACH_BB_FN (cfg_bb, cfun)
+    {
+      auto &info
+	= m_vector_manager->vector_block_infos[cfg_bb->index].reaching_out;
+      gcc_assert (m_vector_manager->expr_set_num (
+		    m_vector_manager->vector_del[cfg_bb->index])
+		  <= 1);
+      for (size_t i = 0; i < m_vector_manager->vector_exprs.length (); i++)
+	{
+	  if (bitmap_bit_p (m_vector_manager->vector_del[cfg_bb->index], i))
+	    {
+	      if (info.dirty_p ())
+		info.set_unknown ();
+	      else
+		{
+		  insn_info *insn
+		    = m_vector_manager->vector_exprs[i]->get_insn ();
+		  gcc_assert (insn && insn->rtl ());
+		  rtx_insn *rinsn;
+		  if (vector_config_insn_p (insn->rtl ()))
+		    rinsn = insn->rtl ();
+		  else
+		    {
+		      gcc_assert (has_vtype_op (insn->rtl ()));
+		      rinsn = PREV_INSN (insn->rtl ());
+		      gcc_assert (
+			vector_config_insn_p (PREV_INSN (insn->rtl ())));
+		    }
+		  eliminate_insn (rinsn);
+		}
+	    }
+	}
+    }
+}
+
+bool
+pass_vsetvl::commit_vsetvls (void)
+{
+  bool need_commit = false;
+
+  for (int ed = 0; ed < NUM_EDGES (m_vector_manager->vector_edge_list); ed++)
+    {
+      for (size_t i = 0; i < m_vector_manager->vector_exprs.length (); i++)
+	{
+	  edge eg = INDEX_EDGE (m_vector_manager->vector_edge_list, ed);
+	  if (bitmap_bit_p (m_vector_manager->vector_insert[ed], i))
+	    {
+	      const vector_insn_info *require
+		= m_vector_manager->vector_exprs[i];
+	      gcc_assert (require->valid_or_dirty_p ());
+	      rtl_profile_for_edge (eg);
+	      start_sequence ();
+
+	      insn_info *insn = require->get_insn ();
+	      vector_insn_info prev_info = vector_insn_info ();
+	      if (m_vector_manager->all_same_ratio_p (
+		    m_vector_manager->vector_avout[eg->src->index]))
+		{
+		  size_t first = bitmap_first_set_bit (
+		    m_vector_manager->vector_avout[eg->src->index]);
+		  prev_info = *m_vector_manager->vector_exprs[first];
+		}
+
+	      insert_vsetvl (EMIT_DIRECT, insn->rtl (), *require, prev_info);
+	      rtx_insn *rinsn = get_insns ();
+	      end_sequence ();
+	      default_rtl_profile ();
+
+	      /* We should not get an abnormal edge here.  */
+	      gcc_assert (!(eg->flags & EDGE_ABNORMAL));
+	      need_commit = true;
+	      insert_insn_on_edge (rinsn, eg);
+	    }
+	}
+    }
+
+  basic_block cfg_bb;
+  FOR_EACH_BB_FN (cfg_bb, cfun)
+    {
+      const auto reaching_out
+	= m_vector_manager->vector_block_infos[cfg_bb->index].reaching_out;
+      if (!reaching_out.dirty_p ())
+	continue;
+
+      rtx new_pat = reaching_out.get_dirty_pat ();
+      if (can_refine_vsetvl_p (cfg_bb, reaching_out.get_ratio ()))
+	new_pat
+	  = gen_vsetvl_pat (VSETVL_VTYPE_CHANGE_ONLY, reaching_out, NULL_RTX);
+
+      start_sequence ();
+      emit_insn (new_pat);
+      rtx_insn *rinsn = get_insns ();
+      end_sequence ();
+      insert_insn_end_basic_block (rinsn, cfg_bb);
+      if (dump_file)
+	{
+	  fprintf (dump_file,
+		   "\nInsert vsetvl insn %d at the end of <bb %d>:\n",
+		   INSN_UID (rinsn), cfg_bb->index);
+	  print_rtl_single (dump_file, rinsn);
+	}
+    }
+
+  return need_commit;
+}
+
+void
+pass_vsetvl::pre_vsetvl (void)
+{
+  /* Compute entity list.  */
+  prune_expressions ();
+
+  /* Create the bitmap vectors.  */
+  m_vector_manager->vector_antic
+    = sbitmap_vector_alloc (last_basic_block_for_fn (cfun),
+			    m_vector_manager->vector_exprs.length ());
+  m_vector_manager->vector_transp
+    = sbitmap_vector_alloc (last_basic_block_for_fn (cfun),
+			    m_vector_manager->vector_exprs.length ());
+  m_vector_manager->vector_comp
+    = sbitmap_vector_alloc (last_basic_block_for_fn (cfun),
+			    m_vector_manager->vector_exprs.length ());
+  m_vector_manager->vector_avin
+    = sbitmap_vector_alloc (last_basic_block_for_fn (cfun),
+			    m_vector_manager->vector_exprs.length ());
+  m_vector_manager->vector_avout
+    = sbitmap_vector_alloc (last_basic_block_for_fn (cfun),
+			    m_vector_manager->vector_exprs.length ());
+  m_vector_manager->vector_kill
+    = sbitmap_vector_alloc (last_basic_block_for_fn (cfun),
+			    m_vector_manager->vector_exprs.length ());
+
+  bitmap_vector_ones (m_vector_manager->vector_transp,
+		      last_basic_block_for_fn (cfun));
+  bitmap_vector_clear (m_vector_manager->vector_antic,
+		       last_basic_block_for_fn (cfun));
+  bitmap_vector_clear (m_vector_manager->vector_comp,
+		       last_basic_block_for_fn (cfun));
+  compute_local_properties ();
+  m_vector_manager->vector_edge_list = pre_edge_lcm_avs (
+    m_vector_manager->vector_exprs.length (), m_vector_manager->vector_transp,
+    m_vector_manager->vector_comp, m_vector_manager->vector_antic,
+    m_vector_manager->vector_kill, m_vector_manager->vector_avin,
+    m_vector_manager->vector_avout, &m_vector_manager->vector_insert,
+    &m_vector_manager->vector_del);
+
+  /* We should dump the information before CFG is changed. Otherwise it will
+     produce ICE (internal compiler error).  */
+  if (dump_file)
+    m_vector_manager->dump (dump_file);
+
+  refine_vsetvls ();
+  cleanup_vsetvls ();
+  bool need_commit = commit_vsetvls ();
+  if (need_commit)
+    commit_edge_insertions ();
+}
+
+void
+pass_vsetvl::cleanup_insns (void) const
+{
+  for (const bb_info *bb : crtl->ssa->bbs ())
+    {
+      for (insn_info *insn : bb->real_nondebug_insns ())
+	{
+	  rtx_insn *rinsn = insn->rtl ();
+
+	  if (vlmax_avl_insn_p (rinsn))
+	    {
+	      eliminate_insn (rinsn);
+	      continue;
+	    }
+
+	  /* Erase the AVL operand from the instruction.  */
+	  if (!has_vl_op (rinsn) || !REG_P (get_vl (rinsn)))
+	    continue;
+	  rtx avl = get_vl (rinsn);
+	  if (count_occurrences (PATTERN (rinsn), avl, true) == 1)
+	    {
+	      /* Get the list of uses for the new instruction.  */
+	      auto attempt = crtl->ssa->new_change_attempt ();
+	      insn_change change (insn);
+	      /* Remove the use of the substituted value.  */
+	      access_array_builder uses_builder (attempt);
+	      uses_builder.reserve (insn->num_uses () - 1);
+	      for (use_info *use : insn->uses ())
+		if (use != find_access (insn->uses (), REGNO (avl)))
+		  uses_builder.quick_push (use);
+	      use_array new_uses = use_array (uses_builder.finish ());
+	      change.new_uses = new_uses;
+	      change.move_range = insn->ebb ()->insn_range ();
+	      rtx pat = simplify_replace_rtx (PATTERN (rinsn), avl, const0_rtx);
+	      gcc_assert (change_insn (crtl->ssa, change, insn, pat));
+	    }
+	}
+    }
+}
+
+void
+pass_vsetvl::init (void)
+{
+  if (optimize > 0)
+    {
+      /* Initialization of RTL_SSA.  */
+      calculate_dominance_info (CDI_DOMINATORS);
+      df_analyze ();
+      crtl->ssa = new function_info (cfun);
+    }
+
+  m_vector_manager = new vector_infos_manager ();
+
+  if (dump_file)
+    {
+      fprintf (dump_file, "\nPrologue: Initialize vector infos\n");
+      m_vector_manager->dump (dump_file);
+    }
+}
+
+void
+pass_vsetvl::done (void)
+{
+  if (optimize > 0)
+    {
+      /* Finalization of RTL_SSA.  */
+      free_dominance_info (CDI_DOMINATORS);
+      if (crtl->ssa->perform_pending_updates ())
+	cleanup_cfg (0);
+      delete crtl->ssa;
+      crtl->ssa = nullptr;
+    }
+  m_vector_manager->release ();
+  delete m_vector_manager;
+  m_vector_manager = nullptr;
+}
+
+/* Lazy vsetvl insertion for optimize > 0. */
+void
+pass_vsetvl::lazy_vsetvl (void)
+{
+  if (dump_file)
+    fprintf (dump_file,
+	     "\nEntering Lazy VSETVL PASS and Handling %d basic blocks for "
+	     "function:%s\n",
+	     n_basic_blocks_for_fn (cfun), function_name (cfun));
+
+  /* Phase 1 - Compute the local dems within each block.
+     The data-flow analysis within each block is backward analysis.  */
+  if (dump_file)
+    fprintf (dump_file, "\nPhase 1: Compute local backward vector infos\n");
+  for (const bb_info *bb : crtl->ssa->bbs ())
+    compute_local_backward_infos (bb);
+  if (dump_file)
+    m_vector_manager->dump (dump_file);
+
+  /* Phase 2 - Emit vsetvl instructions within each basic block according to
+     demand, compute and save ANTLOC && AVLOC of each block.  */
+  if (dump_file)
+    fprintf (dump_file,
+	     "\nPhase 2: Emit vsetvl instruction within each block\n");
+  for (const bb_info *bb : crtl->ssa->bbs ())
+    emit_local_forward_vsetvls (bb);
+  if (dump_file)
+    m_vector_manager->dump (dump_file);
+
+  /* Phase 3 - Propagate demanded info across blocks.  */
+  if (dump_file)
+    fprintf (dump_file, "\nPhase 3: Demands propagation across blocks\n");
+  compute_global_backward_infos ();
+  if (dump_file)
+    m_vector_manager->dump (dump_file);
+
+  /* Phase 4 - Lazy code motion.  */
+  if (dump_file)
+    fprintf (dump_file, "\nPhase 4: PRE vsetvl by Lazy code motion (LCM)\n");
+  pre_vsetvl ();
+
+  /* Phase 5 - Cleanup AVL && VL operand of RVV instruction.  */
+  if (dump_file)
+    fprintf (dump_file, "\nPhase 5: Cleanup AVL and VL operands\n");
+  cleanup_insns ();
+}
+
+/* Main entry point for this pass.  */
+unsigned int
+pass_vsetvl::execute (function *)
+{
+  if (n_basic_blocks_for_fn (cfun) <= 0)
+    return 0;
+
+  /* The reason we have this since we didn't finish splitting yet
+     when optimize == 0. In this case, we should conservatively
+     split all instructions here to make sure we don't miss any
+     RVV instruction.  */
+  if (!optimize)
+    split_all_insns ();
+
+  /* Early return for there is no vector instructions.  */
+  if (!has_vector_insn (cfun))
+    return 0;
+
+  init ();
+
+  if (!optimize)
+    simple_vsetvl ();
+  else
+    lazy_vsetvl ();
+
+  done ();
+  return 0;
+}
+
+rtl_opt_pass *
+make_pass_vsetvl (gcc::context *ctxt)
+{
+  return new pass_vsetvl (ctxt);
+}
diff --git a/gcc/config/riscv/riscv-vsetvl.h b/gcc/config/riscv/riscv-vsetvl.h
new file mode 100644
index 0000000..ad9bb27
--- /dev/null
+++ b/gcc/config/riscv/riscv-vsetvl.h
@@ -0,0 +1,344 @@
+/* VSETVL pass header for RISC-V 'V' Extension for GNU compiler.
+   Copyright(C) 2022-2022 Free Software Foundation, Inc.
+   Contributed by Juzhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or(at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+<http://www.gnu.org/licenses/>.  */
+
+#ifndef GCC_RISCV_VSETVL_H
+#define GCC_RISCV_VSETVL_H
+
+#define IS_AGNOSTIC(VALUE) (bool) (VALUE & 0x1 || (VALUE >> 1 & 0x1))
+
+namespace riscv_vector {
+
+/* Classification of vsetvl instruction.  */
+enum vsetvl_type
+{
+  VSETVL_NORMAL,
+  VSETVL_VTYPE_CHANGE_ONLY,
+  VSETVL_DISCARD_RESULT,
+};
+
+enum emit_type
+{
+  /* emit_insn directly.  */
+  EMIT_DIRECT,
+  EMIT_BEFORE,
+  EMIT_AFTER,
+};
+
+enum demand_type
+{
+  DEMAND_AVL,
+  DEMAND_SEW,
+  DEMAND_LMUL,
+  DEMAND_RATIO,
+  DEMAND_TAIL_POLICY,
+  DEMAND_MASK_POLICY,
+  NUM_DEMAND
+};
+
+/* AVL info for RVV instruction. Most RVV instructions have AVL operand in
+   implicit dependency. The AVL comparison between 2 RVV instructions is
+   very important since it affects our decision whether we should insert
+   a vsetvl instruction in this situation. AVL operand of all RVV instructions
+   can only be either a const_int value with < 32 or a reg value which can be
+   define by either a real RTL instruction or a PHI instruction. So we need a
+   standalone method to define AVL comparison and we can not simpily use
+   operator "==" to compare 2 RTX value since it's to strict which will make
+   use miss a lot of optimization opportunities. This method handle these
+   following cases:
+
+     -  Background:
+	  Insert-vsetvl PASS is working after RA.
+
+     -  Terminology:
+	  - pr: Pseudo-register.
+	  - hr: Hardware-register.
+
+     -  Case 1:
+
+	Before RA:
+	  li pr138,13
+	  insn1 (implicit depend on pr138).
+	  li pr138,14
+	  insn2 (implicit depend on pr139).
+
+	After RA:
+	  li hr5,13
+	  insn1 (implicit depend on hr5).
+	  li hr5,14
+	  insn2 (implicit depend on hr5).
+
+	Correct IR after vsetvl PASS:
+	  li hr5,13
+	  vsetvl1 zero,hr5....
+	  insn1 (implicit depend on hr5).
+	  li hr5,14
+	  vsetvl2 zero,hr5....
+	  insn2 (implicit depend on hr5).
+
+     In this case, both insn1 and insn2 are using hr5 as the same AVL.
+     If we use "rtx_equal_p" or "REGNO (AVL1) == REGNO (AVL)", we will end
+     up with missing the vsetvl2 instruction which creates wrong result.
+
+     Note: Using "==" operator to compare 2 AVL RTX strictly can fix this
+     issue. However, it is a too strict comparison method since not all member
+     variables in RTX data structure are not neccessary to be the same. It will
+     make us miss a lot of optimization opportunities.
+
+     -  Case 2:
+
+	After RA:
+	bb 0:
+	  li hr5,13
+	bb 1:
+	  li hr5,14
+	bb2:
+	  insn1 (implicit depend on hr5).
+	  insn2 (implicit depend on hr5).
+
+     In this case, we may end up with different AVL RTX and produce redundant
+     vsetvl instruction.
+
+     VALUE is the implicit dependency in each RVV instruction.
+     SOURCE is the source definition information of AVL operand.  */
+class avl_info
+{
+private:
+  rtx m_value;
+  rtl_ssa::set_info *m_source;
+
+public:
+  avl_info () : m_value (NULL_RTX), m_source (nullptr) {}
+  avl_info (rtx, rtl_ssa::set_info *);
+  rtx get_value () const { return m_value; }
+  rtl_ssa::set_info *get_source () const { return m_source; }
+  avl_info &operator= (const avl_info &);
+  bool operator== (const avl_info &) const;
+  bool operator!= (const avl_info &) const;
+};
+
+/* Basic structure to save VL/VTYPE information.  */
+struct vl_vtype_info
+{
+protected:
+  /* AVL can be either register or const_int.  */
+  avl_info m_avl;
+  /* Fields from VTYPE. The VTYPE checking depend on the flag
+     dem_* before.  */
+  uint8_t m_sew;
+  riscv_vector::vlmul_type m_vlmul;
+  uint8_t m_ratio;
+  bool m_ta;
+  bool m_ma;
+
+public:
+  void set_sew (uint8_t sew) { m_sew = sew; }
+  void set_vlmul (riscv_vector::vlmul_type vlmul) { m_vlmul = vlmul; }
+  void set_ratio (uint8_t ratio) { m_ratio = ratio; }
+  void set_ta (bool ta) { m_ta = ta; }
+  void set_ma (bool ma) { m_ma = ma; }
+
+  vl_vtype_info ()
+    : m_avl (avl_info ()), m_sew (0), m_vlmul (riscv_vector::LMUL_RESERVED),
+      m_ratio (0), m_ta (0), m_ma (0)
+  {}
+  vl_vtype_info (const vl_vtype_info &) = default;
+  vl_vtype_info &operator= (const vl_vtype_info &) = default;
+  vl_vtype_info (avl_info, uint8_t, riscv_vector::vlmul_type, uint8_t, bool,
+		 bool);
+
+  bool operator== (const vl_vtype_info &) const;
+  bool operator!= (const vl_vtype_info &) const;
+
+  bool has_avl_imm () const { return get_avl () && CONST_INT_P (get_avl ()); }
+  bool has_avl_reg () const { return get_avl () && REG_P (get_avl ()); }
+  bool has_avl_no_reg () const { return !get_avl (); }
+  bool has_non_zero_avl () const;
+
+  rtx get_avl () const { return m_avl.get_value (); }
+  avl_info get_avl_info () const { return m_avl; }
+  void set_avl_info (const avl_info &avl) { m_avl = avl; }
+  uint8_t get_sew () const { return m_sew; }
+  riscv_vector::vlmul_type get_vlmul () const { return m_vlmul; }
+  uint8_t get_ratio () const { return m_ratio; }
+  bool get_ta () const { return m_ta; }
+  bool get_ma () const { return m_ma; }
+
+  bool same_avl_p (const vl_vtype_info &) const;
+  bool same_vtype_p (const vl_vtype_info &) const;
+  bool same_vlmax_p (const vl_vtype_info &) const;
+};
+
+class vector_insn_info : public vl_vtype_info
+{
+private:
+  enum state_type
+  {
+    UNINITIALIZED,
+    VALID,
+    UNKNOWN,
+    EMPTY,
+
+    /* The block is polluted as containing VSETVL instruction during dem
+       backward propagation to gain better LCM optimization even though
+       such VSETVL instruction is not really emit yet during this time.  */
+    DIRTY
+  };
+
+  enum state_type m_state;
+
+  bool m_demands[NUM_DEMAND];
+
+  /* TODO: Assume INSN1 = INSN holding of definition of AVL.
+		  INSN2 = INSN that is inserted a vsetvl insn before.
+     We may need to add a new member to save INSN of holding AVL.
+     m_insn is holding the INSN that is inserted a vsetvl insn before in
+     Phase 2. Ideally, most of the time INSN1 == INSN2. However, considering
+     such case:
+
+	vmv.x.s (INSN2)
+	vle8.v (INSN1)
+
+     If these 2 instructions are compatible, we should only issue a vsetvl INSN
+     (with AVL included) before vmv.x.s, but vmv.x.s is not the INSN holding the
+     definition of AVL.  */
+  rtl_ssa::insn_info *m_insn;
+  /* Save instruction pattern for Dirty block.
+     Since empty block may be polluted as a dirty block during dem backward
+     propagation (phase 3) which is intending to cheat LCM there is a VSETVL
+     instruction here to gain better LCM optimization. Such instruction is not
+     emit yet, we save this here and then emit it in the 4th phase if it is
+     necessary.  */
+  rtx m_dirty_pat;
+
+  /* Parse the instruction to get VL/VTYPE information and demanding
+   * information.  */
+  /* This is only called by simple_vsetvl subroutine when optimize == 0.
+     Since RTL_SSA can not be enabled when optimize == 0, we don't initialize
+     the m_insn.  */
+  void parse_insn (rtx_insn *);
+  /* This is only called by lazy_vsetvl subroutine when optimize > 0.
+     We use RTL_SSA framework to initialize the insn_info.  */
+  void parse_insn (rtl_ssa::insn_info *);
+
+  friend class vector_infos_manager;
+
+public:
+  vector_insn_info ()
+    : vl_vtype_info (), m_state (UNINITIALIZED), m_demands{false},
+      m_insn (nullptr), m_dirty_pat (NULL_RTX)
+  {}
+
+  bool operator> (const vector_insn_info &) const;
+  bool operator>= (const vector_insn_info &) const;
+  bool operator== (const vector_insn_info &) const;
+
+  bool uninit_p () const { return m_state == UNINITIALIZED; }
+  bool valid_p () const { return m_state == VALID; }
+  bool unknown_p () const { return m_state == UNKNOWN; }
+  bool empty_p () const { return m_state == EMPTY; }
+  bool dirty_p () const { return m_state == DIRTY; }
+  bool valid_or_dirty_p () const
+  {
+    return m_state == VALID || m_state == DIRTY;
+  }
+
+  static vector_insn_info get_unknown ()
+  {
+    vector_insn_info info;
+    info.set_unknown ();
+    return info;
+  }
+
+  void set_valid () { m_state = VALID; }
+  void set_unknown () { m_state = UNKNOWN; }
+  void set_empty () { m_state = EMPTY; }
+  void set_dirty () { m_state = DIRTY; }
+  void set_dirty_pat (rtx pat) { m_dirty_pat = pat; }
+  void set_insn (rtl_ssa::insn_info *insn) { m_insn = insn; }
+
+  bool demand_p (enum demand_type type) const { return m_demands[type]; }
+  void demand (enum demand_type type) { m_demands[type] = true; }
+  void demand_vl_vtype ();
+  void undemand (enum demand_type type) { m_demands[type] = false; }
+
+  bool compatible_p (const vector_insn_info &) const;
+  bool compatible_avl_p (const vl_vtype_info &) const;
+  bool compatible_vtype_p (const vl_vtype_info &) const;
+  bool compatible_p (const vl_vtype_info &) const;
+  vector_insn_info merge (const vector_insn_info &, bool) const;
+
+  rtl_ssa::insn_info *get_insn () const { return m_insn; }
+  rtx get_dirty_pat () const { return m_dirty_pat; }
+
+  void dump (FILE *) const;
+};
+
+struct vector_block_info
+{
+  /* The local_dem vector insn_info of the block.  */
+  vector_insn_info local_dem;
+
+  /* The reaching_out vector insn_info of the block.  */
+  vector_insn_info reaching_out;
+
+  vector_block_info () = default;
+};
+
+class vector_infos_manager
+{
+public:
+  auto_vec<vector_insn_info> vector_insn_infos;
+  auto_vec<vector_block_info> vector_block_infos;
+  auto_vec<vector_insn_info *> vector_exprs;
+
+  struct edge_list *vector_edge_list;
+  sbitmap *vector_kill;
+  sbitmap *vector_del;
+  sbitmap *vector_insert;
+  sbitmap *vector_antic;
+  sbitmap *vector_transp;
+  sbitmap *vector_comp;
+  sbitmap *vector_avin;
+  sbitmap *vector_avout;
+
+  vector_infos_manager ();
+
+  /* Create a new expr in expr list if it is not exist.  */
+  void create_expr (vector_insn_info &);
+
+  /* Get the expr id of the pair of expr.  */
+  size_t get_expr_id (const vector_insn_info &) const;
+
+  /* Return the number of expr that is set in the bitmap.  */
+  size_t expr_set_num (sbitmap) const;
+
+  /* Get all relaxer expression id for corresponding vector info.  */
+  auto_vec<size_t> get_all_available_exprs (const vector_insn_info &) const;
+
+  /* Return true if all expression set in bitmap are same ratio.  */
+  bool all_same_ratio_p (sbitmap) const;
+
+  void release (void);
+
+  void dump (FILE *) const;
+};
+
+} // namespace riscv_vector
+#endif
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 6dd2ab2..83e0187 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4256,30 +4256,34 @@ riscv_print_operand (FILE *file, rtx op, int letter)
 	  }
 	else if (code == CONST_INT)
 	  {
-	    /* The value in the operand is the unsigned int value
-	       converted from (enum machine_mode).
-	       This RTX is generated as follows:
-
-	       machine_mode mode = XXXmode;
-	       operand = gen_int_mode ((unsigned int)mode, Pmode);
-
-	       So we convert it back into machine_mode and then calculate
-	       the LMUL according to GET_MODE_SIZE.  */
-
-	    machine_mode rvv_mode = (machine_mode) UINTVAL (op);
-	    /* For rvv mask modes, we can not calculate LMUL simpily according
-	       to BYTES_PER_RISCV_VECTOR. When rvv_mode = VNx4BImode.
-	       Set SEW = 8, LMUL = 1 by default if TARGET_MIN_VLEN == 32.
-	       Set SEW = 8, LMUL = 1 / 2 by default if TARGET_MIN_VLEN > 32.  */
-	    bool bool_p = GET_MODE_CLASS (rvv_mode) == MODE_VECTOR_BOOL;
-	    poly_int64 m1_size = BYTES_PER_RISCV_VECTOR;
-	    poly_int64 rvv_size
-	      = bool_p ? GET_MODE_NUNITS (rvv_mode) : GET_MODE_SIZE (rvv_mode);
-	    bool fractional_p = known_lt (rvv_size, BYTES_PER_RISCV_VECTOR);
-	    unsigned int factor
-	      = fractional_p ? exact_div (m1_size, rvv_size).to_constant ()
-			     : exact_div (rvv_size, m1_size).to_constant ();
-	    asm_fprintf (file, "%s%d", fractional_p ? "mf" : "m", factor);
+	    /* If it is a const_int value, it denotes the VLMUL field enum.  */
+	    unsigned int vlmul = UINTVAL (op);
+	    switch (vlmul)
+	      {
+	      case riscv_vector::LMUL_1:
+		asm_fprintf (file, "%s", "m1");
+		break;
+	      case riscv_vector::LMUL_2:
+		asm_fprintf (file, "%s", "m2");
+		break;
+	      case riscv_vector::LMUL_4:
+		asm_fprintf (file, "%s", "m4");
+		break;
+	      case riscv_vector::LMUL_8:
+		asm_fprintf (file, "%s", "m8");
+		break;
+	      case riscv_vector::LMUL_F8:
+		asm_fprintf (file, "%s", "mf8");
+		break;
+	      case riscv_vector::LMUL_F4:
+		asm_fprintf (file, "%s", "mf4");
+		break;
+	      case riscv_vector::LMUL_F2:
+		asm_fprintf (file, "%s", "mf2");
+		break;
+	      default:
+		gcc_unreachable ();
+	      }
 	  }
 	else
 	  output_operand_lossage ("invalid vector constant");
diff --git a/gcc/config/riscv/t-riscv b/gcc/config/riscv/t-riscv
index 7997db3..7af9f54 100644
--- a/gcc/config/riscv/t-riscv
+++ b/gcc/config/riscv/t-riscv
@@ -51,6 +51,14 @@ riscv-c.o: $(srcdir)/config/riscv/riscv-c.cc $(CONFIG_H) $(SYSTEM_H) \
 	$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
 		$(srcdir)/config/riscv/riscv-c.cc
 
+riscv-vsetvl.o: $(srcdir)/config/riscv/riscv-vsetvl.cc \
+  $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(RTL_H) $(REGS_H) \
+  $(TARGET_H) tree-pass.h df.h rtl-ssa.h cfgcleanup.h insn-config.h \
+  insn-attr.h insn-opinit.h tm-constrs.h cfgrtl.h cfganal.h lcm.h \
+  predict.h profile-count.h $(srcdir)/config/riscv/riscv-vsetvl.h
+	$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
+		$(srcdir)/config/riscv/riscv-vsetvl.cc
+
 riscv-d.o: $(srcdir)/config/riscv/riscv-d.cc
 	$(COMPILE) $<
 	$(POSTCOMPILE)
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 1b82218..52ca6b3 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -32,6 +32,7 @@
   UNSPEC_VSETVL
   UNSPEC_VUNDEF
   UNSPEC_VPREDICATE
+  UNSPEC_VLMAX
 ])
 
 (define_constants [
@@ -94,7 +95,13 @@
 	 (const_int 32)
 	 (eq_attr "mode" "VNx1DI,VNx2DI,VNx4DI,VNx8DI,\
 			  VNx1DF,VNx2DF,VNx4DF,VNx8DF")
-	 (const_int 64)]
+	 (const_int 64)
+
+	 (eq_attr "type" "vsetvl")
+	 (if_then_else (eq_attr "INSN_CODE (curr_insn) == CODE_FOR_vsetvldi
+				 || INSN_CODE (curr_insn) == CODE_FOR_vsetvlsi")
+		       (symbol_ref "INTVAL (operands[2])")
+		       (const_int INVALID_ATTRIBUTE))]
 	(const_int INVALID_ATTRIBUTE)))
 
 ;; Ditto to LMUL.
@@ -142,7 +149,12 @@
 	 (eq_attr "mode" "VNx4DI,VNx4DF")
 	   (symbol_ref "riscv_vector::get_vlmul(E_VNx4DImode)")
 	 (eq_attr "mode" "VNx8DI,VNx8DF")
-	   (symbol_ref "riscv_vector::get_vlmul(E_VNx8DImode)")]
+	   (symbol_ref "riscv_vector::get_vlmul(E_VNx8DImode)")
+	 (eq_attr "type" "vsetvl")
+	 (if_then_else (eq_attr "INSN_CODE (curr_insn) == CODE_FOR_vsetvldi
+				 || INSN_CODE (curr_insn) == CODE_FOR_vsetvlsi")
+		       (symbol_ref "INTVAL (operands[3])")
+		       (const_int INVALID_ATTRIBUTE))]
 	(const_int INVALID_ATTRIBUTE)))
 
 ;; It is valid for instruction that require sew/lmul ratio.
@@ -219,6 +231,34 @@
 	 (const_int 6)]
 	(const_int INVALID_ATTRIBUTE)))
 
+;; The index of operand[] to get the mask policy op.
+(define_attr "avl_type_op_idx" ""
+  (cond [(eq_attr "type" "vlde,vlde,vste,vimov,vimov,vimov,vfmov,vlds,vlds")
+	 (const_int 7)
+	 (eq_attr "type" "vldm,vstm,vimov,vmalu,vmalu")
+	 (const_int 5)]
+	(const_int INVALID_ATTRIBUTE)))
+
+;; The tail policy op value.
+(define_attr "ta" ""
+  (cond [(eq_attr "type" "vlde,vimov,vfmov,vlds")
+	   (symbol_ref "riscv_vector::get_ta(operands[5])")]
+	(const_int INVALID_ATTRIBUTE)))
+
+;; The mask policy op value.
+(define_attr "ma" ""
+  (cond [(eq_attr "type" "vlde,vlds")
+	   (symbol_ref "riscv_vector::get_ma(operands[6])")]
+	(const_int INVALID_ATTRIBUTE)))
+
+;; The avl type value.
+(define_attr "avl_type" ""
+  (cond [(eq_attr "type" "vlde,vlde,vste,vimov,vimov,vimov,vfmov,vlds,vlds")
+	   (symbol_ref "INTVAL (operands[7])")
+	 (eq_attr "type" "vldm,vstm,vimov,vmalu,vmalu")
+	   (symbol_ref "INTVAL (operands[5])")]
+	(const_int INVALID_ATTRIBUTE)))
+
 ;; -----------------------------------------------------------------
 ;; ---- Miscellaneous Operations
 ;; -----------------------------------------------------------------
@@ -229,6 +269,37 @@
   "TARGET_VECTOR"
   "")
 
+;; This pattern is used to hold the AVL operand for
+;; RVV instructions that implicity use VLMAX AVL.
+;; RVV instruction implicitly use GPR that is ultimately
+;; defined by this pattern is safe for VSETVL pass emit
+;; a vsetvl instruction modify this register after RA.
+;; Case 1:
+;;   vlmax_avl a5
+;;   ... (across many blocks)
+;;   vadd (implicit use a5)  ====> emit: vsetvl a5,zero
+;; Case 2:
+;;   vlmax_avl a5
+;;   ... (across many blocks)
+;;   mv a6,a5
+;;   ... (across many blocks)
+;;   vadd (implicit use a6)  ====> emit: vsetvl a6,zero
+;; Case 3:
+;;   vlmax_avl a5
+;;   ... (across many blocks)
+;;   store mem,a5 (spill)
+;;   ... (across many blocks)
+;;   load a7,mem (spill)
+;;   ... (across many blocks)
+;;   vadd (implicit use a7)  ====> emit: vsetvl a7,zero
+;; Such cases are all safe for VSETVL PASS to emit a vsetvl
+;; instruction that modifies the AVL operand.
+(define_insn "@vlmax_avl<mode>"
+  [(set (match_operand:P 0 "register_operand" "=r")
+	(unspec:P [(match_operand:P 1 "const_int_operand" "i")] UNSPEC_VLMAX))]
+  "TARGET_VECTOR"
+  "")
+
 ;; -----------------------------------------------------------------
 ;; ---- Moves Operations
 ;; -----------------------------------------------------------------
@@ -482,32 +553,35 @@
   [(set_attr "type" "vsetvl")
    (set_attr "mode" "<MODE>")])
 
-;; We keep it as no side effects before reload_completed.
-;; In this case, we can gain benefits from different GCC
-;; internal PASS such as cprop, fwprop, combine,...etc.
-
-;; Then recover it for "insert-vsetvl" and "sched2" PASS
-;; in order to get correct codegen.
-(define_insn_and_split "@vsetvl<mode>_no_side_effects"
-  [(set (match_operand:P 0 "register_operand" "=r")
-	(unspec:P [(match_operand:P 1 "csr_operand" "rK")
-		   (match_operand 2 "const_int_operand" "i")
-		   (match_operand 3 "const_int_operand" "i")
-		   (match_operand 4 "const_int_operand" "i")
-		   (match_operand 5 "const_int_operand" "i")] UNSPEC_VSETVL))]
+;; vsetvl zero,zero,vtype instruction.
+;; This pattern has no side effects and does not set X0 register.
+(define_insn "vsetvl_vtype_change_only"
+  [(set (reg:SI VTYPE_REGNUM)
+	(unspec:SI
+	  [(match_operand 0 "const_int_operand" "i")
+	   (match_operand 1 "const_int_operand" "i")
+	   (match_operand 2 "const_int_operand" "i")
+	   (match_operand 3 "const_int_operand" "i")] UNSPEC_VSETVL))]
   "TARGET_VECTOR"
-  "#"
-  "&& reload_completed"
-  [(parallel
-    [(set (match_dup 0)
-	  (unspec:P [(match_dup 1) (match_dup 2) (match_dup 3)
-		     (match_dup 4) (match_dup 5)] UNSPEC_VSETVL))
-     (set (reg:SI VL_REGNUM)
-	  (unspec:SI [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_VSETVL))
-     (set (reg:SI VTYPE_REGNUM)
-	  (unspec:SI [(match_dup 2) (match_dup 3) (match_dup 4)
-		      (match_dup 5)] UNSPEC_VSETVL))])]
-  ""
+  "vsetvli\tzero,zero,e%0,%m1,t%p2,m%p3"
+  [(set_attr "type" "vsetvl")
+   (set_attr "mode" "SI")])
+
+;; vsetvl zero,rs1,vtype instruction.
+;; The reason we need this pattern since we should avoid setting X0 register
+;; in vsetvl instruction pattern.
+(define_insn "@vsetvl_discard_result<mode>"
+  [(set (reg:SI VL_REGNUM)
+	(unspec:SI [(match_operand:P 0 "csr_operand" "rK")
+		    (match_operand 1 "const_int_operand" "i")
+		    (match_operand 2 "const_int_operand" "i")] UNSPEC_VSETVL))
+   (set (reg:SI VTYPE_REGNUM)
+	(unspec:SI [(match_dup 1)
+		    (match_dup 2)
+		    (match_operand 3 "const_int_operand" "i")
+		    (match_operand 4 "const_int_operand" "i")] UNSPEC_VSETVL))]
+  "TARGET_VECTOR"
+  "vsetvli\tzero,%0,e%1,%m2,t%p3,m%p4"
   [(set_attr "type" "vsetvl")
    (set_attr "mode" "<MODE>")])
 
@@ -563,6 +637,7 @@
 	     (match_operand 4 "vector_length_operand"    " rK,  rK,    rK,    rK,    rK")
 	     (match_operand 5 "const_int_operand"        "  i,   i,     i,     i,     i")
 	     (match_operand 6 "const_int_operand"        "  i,   i,     i,     i,     i")
+	     (match_operand 7 "const_int_operand"        "  i,   i,     i,     i,     i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (match_operand:V 3 "vector_move_operand"       "  m,   m,    vr,    vr, viWc0")
@@ -593,6 +668,7 @@
 	  (unspec:VB
 	    [(match_operand:VB 1 "vector_mask_operand"   "Wc1, Wc1, Wc1, Wc1, Wc1")
 	     (match_operand 4 "vector_length_operand"    " rK,  rK,  rK,  rK,  rK")
+	     (match_operand 5 "const_int_operand"        "  i,   i,   i,   i,   i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (match_operand:VB 3 "vector_move_operand"      "  m,  vr,  vr, Wc0, Wc1")
@@ -628,6 +704,7 @@
 	     (match_operand 4 "vector_length_operand"         " rK,  rK,  rK,  rK")
 	     (match_operand 5 "const_int_operand"             "  i,   i,   i,   i")
 	     (match_operand 6 "const_int_operand"             "  i,   i,   i,   i")
+	     (match_operand 7 "const_int_operand"             "  i,   i,   i,   i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (vec_duplicate:V
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index d0d8932..8355621 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -35,6 +35,9 @@ extern bool xxspltib_constant_p (rtx, machine_mode, int *, int *);
 extern int vspltis_shifted (rtx);
 extern HOST_WIDE_INT const_vector_elt_as_int (rtx, unsigned int);
 extern bool macho_lo_sum_memory_operand (rtx, machine_mode);
+extern bool can_be_rotated_to_lowbits (unsigned HOST_WIDE_INT, int, int *);
+extern bool can_be_rotated_to_positive_16bits (HOST_WIDE_INT);
+extern bool can_be_rotated_to_negative_15bits (HOST_WIDE_INT);
 extern int num_insns_constant (rtx, machine_mode);
 extern int small_data_operand (rtx, machine_mode);
 extern bool mem_operand_gpr (rtx, machine_mode);
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index b3a609f..e074e8f 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -10251,17 +10251,42 @@ rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c)
       if (ud1 != 0)
 	emit_move_insn (dest, gen_rtx_IOR (DImode, temp, GEN_INT (ud1)));
     }
+  else if (ud4 == 0xffff && ud3 == 0xffff && (ud1 & 0x8000))
+    {
+      /* li; xoris */
+      temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
+      emit_move_insn (temp, GEN_INT (sext_hwi (ud1, 16)));
+      emit_move_insn (dest, gen_rtx_XOR (DImode, temp,
+					 GEN_INT ((ud2 ^ 0xffff) << 16)));
+    }
   else if (ud3 == 0 && ud4 == 0)
     {
       temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
 
       gcc_assert (ud2 & 0x8000);
-      emit_move_insn (temp, GEN_INT (sext_hwi (ud2 << 16, 32)));
-      if (ud1 != 0)
-	emit_move_insn (temp, gen_rtx_IOR (DImode, temp, GEN_INT (ud1)));
-      emit_move_insn (dest,
-		      gen_rtx_ZERO_EXTEND (DImode,
-					   gen_lowpart (SImode,temp)));
+
+      if (ud1 == 0)
+	{
+	  /* lis; rldicl */
+	  emit_move_insn (temp, GEN_INT (sext_hwi (ud2 << 16, 32)));
+	  emit_move_insn (dest,
+			  gen_rtx_AND (DImode, temp, GEN_INT (0xffffffff)));
+	}
+      else if (!(ud1 & 0x8000))
+	{
+	  /* li; oris */
+	  emit_move_insn (temp, GEN_INT (ud1));
+	  emit_move_insn (dest,
+			  gen_rtx_IOR (DImode, temp, GEN_INT (ud2 << 16)));
+	}
+      else
+	{
+	  /* lis; ori; rldicl */
+	  emit_move_insn (temp, GEN_INT (sext_hwi (ud2 << 16, 32)));
+	  emit_move_insn (temp, gen_rtx_IOR (DImode, temp, GEN_INT (ud1)));
+	  emit_move_insn (dest,
+			  gen_rtx_AND (DImode, temp, GEN_INT (0xffffffff)));
+	}
     }
   else if (ud1 == ud3 && ud2 == ud4)
     {
@@ -14925,6 +14950,71 @@ rs6000_reverse_condition (machine_mode mode, enum rtx_code code)
     return reverse_condition (code);
 }
 
+/* Check if C (as 64bit integer) can be rotated to a constant which constains
+   nonzero bits at the LOWBITS low bits only.
+
+   Return true if C can be rotated to such constant.  If so, *ROT is written
+   to the number by which C is rotated.
+   Return false otherwise.  */
+
+bool
+can_be_rotated_to_lowbits (unsigned HOST_WIDE_INT c, int lowbits, int *rot)
+{
+  int clz = HOST_BITS_PER_WIDE_INT - lowbits;
+
+  /* case a. 0..0xxx: already at least clz zeros.  */
+  int lz = clz_hwi (c);
+  if (lz >= clz)
+    {
+      *rot = 0;
+      return true;
+    }
+
+  /* case b. 0..0xxx0..0: at least clz zeros.  */
+  int tz = ctz_hwi (c);
+  if (lz + tz >= clz)
+    {
+      *rot = HOST_BITS_PER_WIDE_INT - tz;
+      return true;
+    }
+
+  /* case c. xx10.....0xx: rotate 'clz - 1' bits first, then check case b.
+	       ^bit -> Vbit, , then zeros are at head or tail.
+	     00...00xxx100, 'clz - 1' >= 'bits of xxxx'.  */
+  const int rot_bits = lowbits + 1;
+  unsigned HOST_WIDE_INT rc = (c >> rot_bits) | (c << (clz - 1));
+  tz = ctz_hwi (rc);
+  if (clz_hwi (rc) + tz >= clz)
+    {
+      *rot = HOST_BITS_PER_WIDE_INT - (tz + rot_bits);
+      return true;
+    }
+
+  return false;
+}
+
+/* Check if C (as 64bit integer) can be rotated to a positive 16bits constant
+   which contains 48bits leading zeros and 16bits of any value.  */
+
+bool
+can_be_rotated_to_positive_16bits (HOST_WIDE_INT c)
+{
+  int rot = 0;
+  bool res = can_be_rotated_to_lowbits (c, 16, &rot);
+  return res && rot > 0;
+}
+
+/* Check if C (as 64bit integer) can be rotated to a negative 15bits constant
+   which contains 49bits leading ones and 15bits of any value.  */
+
+bool
+can_be_rotated_to_negative_15bits (HOST_WIDE_INT c)
+{
+  int rot = 0;
+  bool res = can_be_rotated_to_lowbits (~c, 15, &rot);
+  return res && rot > 0;
+}
+
 /* Generate a compare for CODE.  Return a brand-new rtx that
    represents the result of the compare.  */
 
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 6011f5b..3cae64a 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -7765,6 +7765,71 @@
   "xscvdpsp %x0,%x1"
   [(set_attr "type" "fp")])
 
+
+(define_code_iterator eqne [eq ne])
+
+;; "i == C" ==> "rotl(i,N) == rotl(C,N)"
+(define_insn_and_split "*rotate_on_cmpdi"
+  [(set (pc)
+	(if_then_else (eqne (match_operand:DI 1 "gpc_reg_operand" "r")
+			    (match_operand:DI 2 "const_int_operand" "n"))
+		      (label_ref (match_operand 0 ""))
+		      (pc)))
+  (clobber (match_scratch:DI 3 "=r"))
+  (clobber (match_scratch:CCUNS 4 "=y"))]
+  "TARGET_POWERPC64 && num_insns_constant (operands[2], DImode) > 1
+   && (can_be_rotated_to_positive_16bits (INTVAL (operands[2]))
+       || can_be_rotated_to_negative_15bits (INTVAL (operands[2])))"
+   "#"
+   "&& 1"
+  [(pc)]
+{
+  bool sgn = false;
+  unsigned HOST_WIDE_INT C = INTVAL (operands[2]);
+  int rot;
+
+  /* cmpldi */
+  if (!can_be_rotated_to_lowbits (C, 16, &rot))
+    {
+      /* cmpdi */
+      sgn = true;
+      bool res = can_be_rotated_to_lowbits (~C, 15, &rot);
+      gcc_assert (res);
+    }
+
+  rtx n = GEN_INT (rot);
+
+  /* i' = rotl (i, n) */
+  rtx op0 = can_create_pseudo_p () ? gen_reg_rtx (DImode) : operands[3];
+  emit_insn (gen_rtx_SET (op0, gen_rtx_ROTATE (DImode, operands[1], n)));
+
+  /* C' = rotl (C, n) */
+  rtx op1 = GEN_INT ((C << rot) | (C >> (HOST_BITS_PER_WIDE_INT - rot)));
+
+  /* i' ==  C' */
+  machine_mode comp_mode = sgn ? CCmode : CCUNSmode;
+  rtx cc = can_create_pseudo_p () ? gen_reg_rtx (comp_mode) : operands[4];
+  PUT_MODE (cc, comp_mode);
+  emit_insn (gen_rtx_SET (cc, gen_rtx_COMPARE (comp_mode, op0, op1)));
+  rtx cmp = gen_rtx_<eqne:CODE> (CCmode, cc, const0_rtx);
+  rtx loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands[0]);
+  emit_jump_insn (gen_rtx_SET (pc_rtx,
+			       gen_rtx_IF_THEN_ELSE (VOIDmode, cmp,
+						     loc_ref, pc_rtx)));
+
+  /* Keep the probability info for the prediction of the branch insn.  */
+  rtx note = find_reg_note (curr_insn, REG_BR_PROB, 0);
+  if (note)
+    {
+      profile_probability prob
+	= profile_probability::from_reg_br_prob_note (XINT (note, 0));
+
+      add_reg_br_prob_note (get_last_insn (), prob);
+    }
+
+  DONE;
+})
+
 ;; Split a load of a large constant into the appropriate two-insn
 ;; sequence.
 
@@ -13463,7 +13528,6 @@
 ;; rs6000_legitimate_combined_insn prevents combine creating any of
 ;; the ctr<mode> insns.
 
-(define_code_iterator eqne [eq ne])
 (define_code_attr bd [(eq "bdz") (ne "bdnz")])
 (define_code_attr bd_neg [(eq "bdnz") (ne "bdz")])
 
diff --git a/gcc/configure b/gcc/configure
index e702a5c..7f06bf22 100755
--- a/gcc/configure
+++ b/gcc/configure
@@ -7218,7 +7218,7 @@ ac_compiler_gnu=$ac_cv_cxx_compiler_gnu
 
 strict_warn=
 save_CXXFLAGS="$CXXFLAGS"
-for real_option in -Wmissing-format-attribute -Woverloaded-virtual; do
+for real_option in -Wmissing-format-attribute -Wconditionally-supported -Woverloaded-virtual; do
   # Do the check with the no- prefix removed since gcc silently
   # accepts any -Wno-* option on purpose
   case $real_option in
diff --git a/gcc/configure.ac b/gcc/configure.ac
index 5c6f247..275263d 100644
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -580,7 +580,7 @@ ACX_PROG_CC_WARNING_OPTS(
 	m4_quote(m4_do([-Wstrict-prototypes -Wmissing-prototypes ],
 		       [])), [c_loose_warn])
 ACX_PROG_CXX_WARNING_OPTS(
-	m4_quote(m4_do([-Wmissing-format-attribute ],
+	m4_quote(m4_do([-Wmissing-format-attribute ], [-Wconditionally-supported ],
 		       [-Woverloaded-virtual])), [strict_warn])
 ACX_PROG_CC_WARNING_OPTS(
 	m4_quote(m4_do([-Wold-style-definition -Wc++-compat])), [c_strict_warn])
diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index d52b03f..73f1c54d 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,44 @@
+2022-12-19  Patrick Palka  <ppalka@redhat.com>
+
+	PR c++/100881
+	* constexpr.cc (cxx_eval_builtin_function_call): Adjust calls
+	to fold_builtin_source_location.
+	* cp-gimplify.cc (cp_gimplify_expr): Likewise.
+	(cp_fold): Likewise.
+	(get_source_location_impl_type): Remove location_t parameter and
+	adjust accordingly.  No longer static.
+	(fold_builtin_source_location): Take a CALL_EXPR tree instead of a
+	location and obtain the impl type from its return type.
+	* cp-tree.h (enum cp_tree_index): Remove CPTI_SOURCE_LOCATION_IMPL
+	enumerator.
+	(source_location_impl): Remove.
+	(fold_builtin_source_location): Adjust parameter type.
+	(get_source_location_impl_type): Declare.
+	* decl.cc (cxx_init_decl_processing): Declare
+	__builtin_source_location with auto return type instead of
+	const void*.
+	(require_deduced_type): Update the return type of
+	__builtin_source_location.
+
+2022-12-19  Patrick Palka  <ppalka@redhat.com>
+
+	PR c++/101886
+	* pt.cc (extract_autos_r): Recompute TYPE_CANONICAL after
+	adjusting the template type parameter's index.  Simplify
+	by using TEMPLATE_TYPE_IDX.  Add some sanity checks.
+
+2022-12-19  Arsen Arsenović  <arsen@aarsen.me>
+
+	* contracts.cc: Rename references to
+	contract_violation_continuation_mode constants to be lowercase.
+
+2022-12-17  Patrick Palka  <ppalka@redhat.com>
+
+	PR c++/107437
+	PR c++/87765
+	* pt.cc (convert_nontype_argument): Relax is_nondep_const_expr
+	test to !inst_dep_expr_p.
+
 2022-12-16  Andrew Pinski  <pinskia@gmail.com>
 	    Iain Sandoe  <iain@sandoe.co.uk>
 
diff --git a/gcc/cp/constexpr.cc b/gcc/cp/constexpr.cc
index e43d928..d99c49b 100644
--- a/gcc/cp/constexpr.cc
+++ b/gcc/cp/constexpr.cc
@@ -1492,7 +1492,7 @@ cxx_eval_builtin_function_call (const constexpr_ctx *ctx, tree t, tree fun,
       temp_override<tree> ovr (current_function_decl);
       if (ctx->call && ctx->call->fundef)
 	current_function_decl = ctx->call->fundef->decl;
-      return fold_builtin_source_location (EXPR_LOCATION (t));
+      return fold_builtin_source_location (t);
     }
 
   int strops = 0;
diff --git a/gcc/cp/contracts.cc b/gcc/cp/contracts.cc
index 45f52b2..2631637 100644
--- a/gcc/cp/contracts.cc
+++ b/gcc/cp/contracts.cc
@@ -41,9 +41,9 @@ along with GCC; see the file COPYING3.  If not see
 	 "v > 0", // comment,
 	 "default", // assertion_level,
 	 "default", // assertion_role,
-	 MAYBE_CONTINUE, // continuation_mode
+	 maybe_continue, // continuation_mode
        });
-       terminate (); // if NEVER_CONTINUE
+       terminate (); // if never_continue
      }
 
    We use an internal type with the same layout as contract_violation rather
diff --git a/gcc/cp/cp-gimplify.cc b/gcc/cp/cp-gimplify.cc
index 983f2a5..1e0b4f8 100644
--- a/gcc/cp/cp-gimplify.cc
+++ b/gcc/cp/cp-gimplify.cc
@@ -722,7 +722,7 @@ cp_gimplify_expr (tree *expr_p, gimple_seq *pre_p, gimple_seq *post_p)
 		break;
 	      case CP_BUILT_IN_SOURCE_LOCATION:
 		*expr_p
-		  = fold_builtin_source_location (EXPR_LOCATION (*expr_p));
+		  = fold_builtin_source_location (*expr_p);
 		break;
 	      case CP_BUILT_IN_IS_CORRESPONDING_MEMBER:
 		*expr_p
@@ -2850,7 +2850,7 @@ cp_fold (tree x)
 	      case CP_BUILT_IN_IS_CONSTANT_EVALUATED:
 		break;
 	      case CP_BUILT_IN_SOURCE_LOCATION:
-		x = fold_builtin_source_location (EXPR_LOCATION (x));
+		x = fold_builtin_source_location (x);
 		break;
 	      case CP_BUILT_IN_IS_CORRESPONDING_MEMBER:
 	        x = fold_builtin_is_corresponding_member
@@ -2872,7 +2872,7 @@ cp_fold (tree x)
 	    && fndecl_built_in_p (callee, CP_BUILT_IN_SOURCE_LOCATION,
 				  BUILT_IN_FRONTEND))
 	  {
-	    x = fold_builtin_source_location (EXPR_LOCATION (x));
+	    x = fold_builtin_source_location (x);
 	    break;
 	  }
 
@@ -3171,12 +3171,11 @@ process_stmt_assume_attribute (tree std_attrs, tree statement,
   return remove_attribute ("gnu", "assume", std_attrs);
 }
 
-/* Helper of fold_builtin_source_location, return the
-   std::source_location::__impl type after performing verification
-   on it.  LOC is used for reporting any errors.  */
+/* Return the type std::source_location::__impl after performing
+   verification on it.  */
 
-static tree
-get_source_location_impl_type (location_t loc)
+tree
+get_source_location_impl_type ()
 {
   tree name = get_identifier ("source_location");
   tree decl = lookup_qualified_name (std_node, name);
@@ -3184,9 +3183,9 @@ get_source_location_impl_type (location_t loc)
     {
       auto_diagnostic_group d;
       if (decl == error_mark_node || TREE_CODE (decl) == TREE_LIST)
-	qualified_name_lookup_error (std_node, name, decl, loc);
+	qualified_name_lookup_error (std_node, name, decl, input_location);
       else
-	error_at (loc, "%qD is not a type", decl);
+	error ("%qD is not a type", decl);
       return error_mark_node;
     }
   name = get_identifier ("__impl");
@@ -3196,15 +3195,15 @@ get_source_location_impl_type (location_t loc)
     {
       auto_diagnostic_group d;
       if (decl == error_mark_node || TREE_CODE (decl) == TREE_LIST)
-	qualified_name_lookup_error (type, name, decl, loc);
+	qualified_name_lookup_error (type, name, decl, input_location);
       else
-	error_at (loc, "%qD is not a type", decl);
+	error ("%qD is not a type", decl);
       return error_mark_node;
     }
   type = TREE_TYPE (decl);
   if (TREE_CODE (type) != RECORD_TYPE)
     {
-      error_at (loc, "%qD is not a class type", decl);
+      error ("%qD is not a class type", decl);
       return error_mark_node;
     }
 
@@ -3221,8 +3220,7 @@ get_source_location_impl_type (location_t loc)
 	    {
 	      if (TREE_TYPE (field) != const_string_type_node)
 		{
-		  error_at (loc, "%qD does not have %<const char *%> type",
-			    field);
+		  error ("%qD does not have %<const char *%> type", field);
 		  return error_mark_node;
 		}
 	      cnt++;
@@ -3232,7 +3230,7 @@ get_source_location_impl_type (location_t loc)
 	    {
 	      if (TREE_CODE (TREE_TYPE (field)) != INTEGER_TYPE)
 		{
-		  error_at (loc, "%qD does not have integral type", field);
+		  error ("%qD does not have integral type", field);
 		  return error_mark_node;
 		}
 	      cnt++;
@@ -3244,9 +3242,9 @@ get_source_location_impl_type (location_t loc)
     }
   if (cnt != 4)
     {
-      error_at (loc, "%<std::source_location::__impl%> does not contain only "
-		     "non-static data members %<_M_file_name%>, "
-		     "%<_M_function_name%>, %<_M_line%> and %<_M_column%>");
+      error ("%<std::source_location::__impl%> does not contain only "
+	     "non-static data members %<_M_file_name%>, "
+	     "%<_M_function_name%>, %<_M_line%> and %<_M_column%>");
       return error_mark_node;
     }
   return build_qualified_type (type, TYPE_QUAL_CONST);
@@ -3337,21 +3335,20 @@ static GTY(()) hash_table <source_location_table_entry_hash>
   *source_location_table;
 static GTY(()) unsigned int source_location_id;
 
-/* Fold __builtin_source_location () call.  LOC is the location
-   of the call.  */
+/* Fold the __builtin_source_location () call T.  */
 
 tree
-fold_builtin_source_location (location_t loc)
+fold_builtin_source_location (const_tree t)
 {
-  if (source_location_impl == NULL_TREE)
-    {
-      auto_diagnostic_group d;
-      source_location_impl = get_source_location_impl_type (loc);
-      if (source_location_impl == error_mark_node)
-	inform (loc, "evaluating %qs", "__builtin_source_location");
-    }
+  gcc_assert (TREE_CODE (t) == CALL_EXPR);
+  /* TREE_TYPE (t) is const std::source_location::__impl*  */
+  tree source_location_impl = TREE_TYPE (TREE_TYPE (t));
   if (source_location_impl == error_mark_node)
     return build_zero_cst (const_ptr_type_node);
+  gcc_assert (CLASS_TYPE_P (source_location_impl)
+	      && id_equal (TYPE_IDENTIFIER (source_location_impl), "__impl"));
+
+  location_t loc = EXPR_LOCATION (t);
   if (source_location_table == NULL)
     source_location_table
       = hash_table <source_location_table_entry_hash>::create_ggc (64);
@@ -3427,7 +3424,7 @@ fold_builtin_source_location (location_t loc)
       entryp->var = var;
     }
 
-  return build_fold_addr_expr_with_type_loc (loc, var, const_ptr_type_node);
+  return build_fold_addr_expr_with_type_loc (loc, var, TREE_TYPE (t));
 }
 
 #include "gt-cp-cp-gimplify.h"
diff --git a/gcc/cp/cp-tree.h b/gcc/cp/cp-tree.h
index 0d6c234..541d760 100644
--- a/gcc/cp/cp-tree.h
+++ b/gcc/cp/cp-tree.h
@@ -235,8 +235,6 @@ enum cp_tree_index
 
     CPTI_PSEUDO_CONTRACT_VIOLATION,
 
-    CPTI_SOURCE_LOCATION_IMPL,
-
     CPTI_FALLBACK_DFLOAT32_TYPE,
     CPTI_FALLBACK_DFLOAT64_TYPE,
     CPTI_FALLBACK_DFLOAT128_TYPE,
@@ -395,9 +393,6 @@ extern GTY(()) tree cp_global_trees[CPTI_MAX];
 /* A node which matches any template argument.  */
 #define any_targ_node			cp_global_trees[CPTI_ANY_TARG]
 
-/* std::source_location::__impl class.  */
-#define source_location_impl		cp_global_trees[CPTI_SOURCE_LOCATION_IMPL]
-
 /* Node to indicate default access. This must be distinct from the
    access nodes in tree.h.  */
 
@@ -8296,7 +8291,8 @@ extern tree process_stmt_hotness_attribute	(tree, location_t);
 extern tree build_assume_call			(location_t, tree);
 extern tree process_stmt_assume_attribute	(tree, tree, location_t);
 extern bool simple_empty_class_p		(tree, tree, tree_code);
-extern tree fold_builtin_source_location	(location_t);
+extern tree fold_builtin_source_location	(const_tree);
+extern tree get_source_location_impl_type	();
 
 /* in name-lookup.cc */
 extern tree strip_using_decl                    (tree);
diff --git a/gcc/cp/decl.cc b/gcc/cp/decl.cc
index 5081563..df74d88 100644
--- a/gcc/cp/decl.cc
+++ b/gcc/cp/decl.cc
@@ -4670,9 +4670,13 @@ cxx_init_decl_processing (void)
 			    BUILT_IN_FRONTEND, NULL, NULL_TREE);
   set_call_expr_flags (decl, ECF_CONST | ECF_NOTHROW | ECF_LEAF);
 
-  tree cptr_ftype = build_function_type_list (const_ptr_type_node, NULL_TREE);
+  /* The concrete return type of __builtin_source_location is
+     const std::source_location::__impl*, but we can't form the type
+     at this point.  So we initially declare it with an auto return
+     type which we then "deduce" from require_deduced_type upon first use.  */
+  tree auto_ftype = build_function_type_list (make_auto (), NULL_TREE);
   decl = add_builtin_function ("__builtin_source_location",
-			       cptr_ftype, CP_BUILT_IN_SOURCE_LOCATION,
+			       auto_ftype, CP_BUILT_IN_SOURCE_LOCATION,
 			       BUILT_IN_FRONTEND, NULL, NULL_TREE);
   set_call_expr_flags (decl, ECF_CONST | ECF_NOTHROW | ECF_LEAF);
 
@@ -18752,6 +18756,23 @@ require_deduced_type (tree decl, tsubst_flags_t complain)
 {
   if (undeduced_auto_decl (decl))
     {
+      if (TREE_CODE (decl) == FUNCTION_DECL
+	  && fndecl_built_in_p (decl, BUILT_IN_FRONTEND)
+	  && DECL_FE_FUNCTION_CODE (decl) == CP_BUILT_IN_SOURCE_LOCATION)
+	{
+	  /* Set the return type of __builtin_source_location.  */
+	  tree type = get_source_location_impl_type ();
+	  if (type == error_mark_node)
+	    {
+	      inform (input_location, "using %qs", "__builtin_source_location");
+	      return false;
+	    }
+	  type = cp_build_qualified_type (type, TYPE_QUAL_CONST);
+	  type = build_pointer_type (type);
+	  apply_deduced_return_type (decl, type);
+	  return true;
+	}
+
       if (warning_suppressed_p (decl) && seen_error ())
 	/* We probably already complained about deduction failure.  */;
       else if (complain & tf_error)
diff --git a/gcc/cp/pt.cc b/gcc/cp/pt.cc
index 2516cca..2b7b375 100644
--- a/gcc/cp/pt.cc
+++ b/gcc/cp/pt.cc
@@ -29243,18 +29243,24 @@ extract_autos_r (tree t, void *data)
     {
       /* All the autos were built with index 0; fix that up now.  */
       tree *p = hash.find_slot (t, INSERT);
-      unsigned idx;
+      int idx;
       if (*p)
 	/* If this is a repeated constrained-type-specifier, use the index we
 	   chose before.  */
-	idx = TEMPLATE_PARM_IDX (TEMPLATE_TYPE_PARM_INDEX (*p));
+	idx = TEMPLATE_TYPE_IDX (*p);
       else
 	{
 	  /* Otherwise this is new, so use the current count.  */
 	  *p = t;
 	  idx = hash.elements () - 1;
 	}
-      TEMPLATE_PARM_IDX (TEMPLATE_TYPE_PARM_INDEX (t)) = idx;
+      if (idx != TEMPLATE_TYPE_IDX (t))
+	{
+	  gcc_checking_assert (TEMPLATE_TYPE_IDX (t) == 0);
+	  gcc_checking_assert (TYPE_CANONICAL (t) != t);
+	  TEMPLATE_TYPE_IDX (t) = idx;
+	  TYPE_CANONICAL (t) = canonical_type_parameter (t);
+	}
     }
 
   /* Always keep walking.  */
diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
index 6884a74..ec31f0a 100644
--- a/gcc/doc/install.texi
+++ b/gcc/doc/install.texi
@@ -4867,6 +4867,8 @@ supported as cross-compilation target only.
 @c alone is too unspecific and must be avoided.
 @anchor{x-x-solaris2}
 @heading *-*-solaris2*
+Support for Solaris 11.3 and earlier has been obsoleted in GCC 13, but
+can still be enabled by configuring with @option{--enable-obsolete}.
 Support for Solaris 10 has been removed in GCC 10.  Support for Solaris
 9 has been removed in GCC 5.  Support for Solaris 8 has been removed in
 GCC 4.8.  Support for Solaris 7 has been removed in GCC 4.6.
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index c7e88e4..d8a2079 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -17693,7 +17693,8 @@ needs to build supplementary stub code for constructors to work.  On
 multi-libbed systems, @samp{gcc -shared} must select the correct support
 libraries to link against.  Failing to supply the correct flags may lead
 to subtle defects.  Supplying them in cases where they are not necessary
-is innocuous.}
+is innocuous. For x86, crtfastmath.o will not be added when
+@option{-shared} is specified. }
 
 @item -shared-libgcc
 @itemx -static-libgcc
diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index ed728eb..8ca9af2 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,8 @@
+2022-12-18  Steve Kargl  <kargl@gcc.gnu.org>
+
+	PR fortran/107397
+	* decl.cc (add_init_expr_to_sym): Add check with new error message.
+
 2022-12-14  Julian Brown  <julian@codesourcery.com>
 
 	PR fortran/107214
diff --git a/gcc/fortran/decl.cc b/gcc/fortran/decl.cc
index 0f9b2ce..1562dc2 100644
--- a/gcc/fortran/decl.cc
+++ b/gcc/fortran/decl.cc
@@ -2221,6 +2221,14 @@ add_init_expr_to_sym (const char *name, gfc_expr **initp, locus *var_locus)
 	    sym->ts.f90_type = init->ts.f90_type;
 	}
 
+      /* Catch the case:  type(t), parameter :: x = z'1'.  */
+      if (sym->ts.type == BT_DERIVED && init->ts.type == BT_BOZ)
+	{
+	  gfc_error ("Entity %qs at %L is incompatible with a BOZ "
+		     "literal constant", name, &sym->declared_at);
+	  return false;
+	}
+
       /* Add initializer.  Make sure we keep the ranks sane.  */
       if (sym->attr.dimension && init->rank == 0)
 	{
diff --git a/gcc/m2/ChangeLog b/gcc/m2/ChangeLog
index c23beec..6ed8eb6 100644
--- a/gcc/m2/ChangeLog
+++ b/gcc/m2/ChangeLog
@@ -1,3 +1,25 @@
+2022-12-19  Jakub Jelinek  <jakub@redhat.com>
+
+	* gm2-gcc/m2linemap.cc (m2linemap_ErrorAt, m2linemap_ErrorAtf,
+	m2linemap_WarningAtf, m2linemap_NoteAtf, m2linemap_internal_error):
+	Call functions with "%s", message rather than just message, so that
+	% chars in message aren't treated as format specifiers.
+
+2022-12-19  Jakub Jelinek  <jakub@redhat.com>
+
+	PR modula2/108147
+	* gm2-gcc/m2linemap.def (ErrorAtf, WarningAtf, NoteAtf):
+	Comment out prototypes with varargs.
+	* gm2-gcc/m2linemap.h (m2linemap_ErrorAtf, m2linemap_WarningAtf,
+	m2linemap_NoteAtf): No longer varargs.
+	* gm2-gcc/m2linemap.cc (m2linemap_ErrorAtf): Turned into a
+	non-varargs wrapper around ...
+	(m2linemap_ErrorAtf_1): ... this.  New static function.
+	(m2linemap_WarningAtf): Turned into a non-varargs wrapper around ...
+	(m2linemap_WarningAtf_1): ... this.  New static function.
+	(m2linemap_NoteAtf): Turned into a non-varargs wrapper around ...
+	(m2linemap_NoteAtf_1): ... this.  New static function.
+
 2022-12-15  Gaius Mulley  <gaiusmod2@gmail.com>
 
 	* configure.ac: Stop probing for realpath.
diff --git a/gcc/m2/gm2-gcc/m2linemap.cc b/gcc/m2/gm2-gcc/m2linemap.cc
index c1c6e2b..ba09c0b 100644
--- a/gcc/m2/gm2-gcc/m2linemap.cc
+++ b/gcc/m2/gm2-gcc/m2linemap.cc
@@ -177,13 +177,13 @@ EXTERN
 void
 m2linemap_ErrorAt (location_t location, char *message)
 {
-  error_at (location, message);
+  error_at (location, "%s", message);
 }
 
 /* m2linemap_ErrorAtf - wraps up an error message.  */
 
-void
-m2linemap_ErrorAtf (location_t location, const char *message, ...)
+static void
+m2linemap_ErrorAtf_1 (location_t location, const char *message, ...)
 {
   diagnostic_info diagnostic;
   va_list ap;
@@ -195,10 +195,16 @@ m2linemap_ErrorAtf (location_t location, const char *message, ...)
   va_end (ap);
 }
 
+void
+m2linemap_ErrorAtf (location_t location, const char *message)
+{
+  m2linemap_ErrorAtf_1 (location, "%s", message);
+}
+
 /* m2linemap_WarningAtf - wraps up a warning message.  */
 
-void
-m2linemap_WarningAtf (location_t location, const char *message, ...)
+static void
+m2linemap_WarningAtf_1 (location_t location, const char *message, ...)
 {
   diagnostic_info diagnostic;
   va_list ap;
@@ -210,10 +216,16 @@ m2linemap_WarningAtf (location_t location, const char *message, ...)
   va_end (ap);
 }
 
+void
+m2linemap_WarningAtf (location_t location, const char *message)
+{
+  m2linemap_WarningAtf_1 (location, "%s", message);
+}
+
 /* m2linemap_NoteAtf - wraps up a note message.  */
 
-void
-m2linemap_NoteAtf (location_t location, const char *message, ...)
+static void
+m2linemap_NoteAtf_1 (location_t location, const char *message, ...)
 {
   diagnostic_info diagnostic;
   va_list ap;
@@ -225,12 +237,18 @@ m2linemap_NoteAtf (location_t location, const char *message, ...)
   va_end (ap);
 }
 
+void
+m2linemap_NoteAtf (location_t location, const char *message)
+{
+  m2linemap_NoteAtf_1 (location, "%s", message);
+}
+
 /* m2linemap_internal_error - allow Modula-2 to use the GCC internal error.  */
 
 void
 m2linemap_internal_error (const char *message)
 {
-  internal_error (message);
+  internal_error ("%s", message);
 }
 
 /* UnknownLocation - return the predefined location representing an
diff --git a/gcc/m2/gm2-gcc/m2linemap.def b/gcc/m2/gm2-gcc/m2linemap.def
index 2c5d11d..689dcb4 100644
--- a/gcc/m2/gm2-gcc/m2linemap.def
+++ b/gcc/m2/gm2-gcc/m2linemap.def
@@ -47,11 +47,6 @@ PROCEDURE GetLineNoFromLocation (location: location_t) : INTEGER ;
 PROCEDURE GetColumnNoFromLocation (location: location_t) : INTEGER ;
 PROCEDURE GetFilenameFromLocation (location: location_t) : ADDRESS ;
 PROCEDURE ErrorAt (location: location_t; message: ADDRESS) ;
-(*
-PROCEDURE ErrorAtf (location: location_t; message: ADDRESS; ...) ;
-PROCEDURE WarningAtf (location: location_t; message: ADDRESS; ...) ;
-PROCEDURE NoteAtf (location: location_t; message: ADDRESS; ...) ;
-*)
 PROCEDURE ErrorAtf (location: location_t; message: ADDRESS) ;
 PROCEDURE WarningAtf (location: location_t; message: ADDRESS) ;
 PROCEDURE NoteAtf (location: location_t; message: ADDRESS) ;
diff --git a/gcc/m2/gm2-gcc/m2linemap.h b/gcc/m2/gm2-gcc/m2linemap.h
index 5de5c26..6941983 100644
--- a/gcc/m2/gm2-gcc/m2linemap.h
+++ b/gcc/m2/gm2-gcc/m2linemap.h
@@ -55,9 +55,9 @@ EXTERN int m2linemap_GetLineNoFromLocation (location_t location);
 EXTERN int m2linemap_GetColumnNoFromLocation (location_t location);
 EXTERN const char *m2linemap_GetFilenameFromLocation (location_t location);
 EXTERN void m2linemap_ErrorAt (location_t location, char *message);
-EXTERN void m2linemap_ErrorAtf (location_t location, const char *message, ...);
-EXTERN void m2linemap_WarningAtf (location_t location, const char *message, ...);
-EXTERN void m2linemap_NoteAtf (location_t location, const char *message, ...);
+EXTERN void m2linemap_ErrorAtf (location_t location, const char *message);
+EXTERN void m2linemap_WarningAtf (location_t location, const char *message);
+EXTERN void m2linemap_NoteAtf (location_t location, const char *message);
 EXTERN void m2linemap_internal_error (const char *message);
 
 
diff --git a/gcc/sort.cc b/gcc/sort.cc
index 87f8268..eeddfcf 100644
--- a/gcc/sort.cc
+++ b/gcc/sort.cc
@@ -237,6 +237,10 @@ do {                                            \
 }
 
 #if CHECKING_P
+  /* Don't complain about cast from void* to function pointer.  */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wconditionally-supported"
+
 /* Adapter for using two-argument comparators in functions expecting the
    three-argument sort_r_cmp_fn type.  */
 static int
@@ -266,6 +270,7 @@ gcc_qsort (void *vbase, size_t n, size_t size, cmp_fn *cmp)
     free (buf);
 #if CHECKING_P
   qsort_chk (vbase, n, size, cmp2to3, (void*)cmp);
+#pragma GCC diagnostic pop
 #endif
 }
 
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 24c4756..fdb864b 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,338 @@
+2022-12-19  Patrick Palka  <ppalka@redhat.com>
+
+	PR c++/100881
+	* g++.dg/cpp2a/srcloc3.C: Adjust expected note s/evaluating/using.
+	* g++.dg/cpp2a/srcloc4.C: Likewise.
+	* g++.dg/cpp2a/srcloc5.C: Likewise.
+	* g++.dg/cpp2a/srcloc6.C: Likewise.
+	* g++.dg/cpp2a/srcloc7.C: Likewise.
+	* g++.dg/cpp2a/srcloc8.C: Likewise.
+	* g++.dg/cpp2a/srcloc9.C: Likewise.
+	* g++.dg/cpp2a/srcloc10.C: Likewise.
+	* g++.dg/cpp2a/srcloc11.C: Likewise.
+	* g++.dg/cpp2a/srcloc12.C: Likewise.
+	* g++.dg/cpp2a/srcloc13.C: Likewise.
+	* g++.dg/modules/pr100881_a.C: New test.
+	* g++.dg/modules/pr100881_b.C: New test.
+
+2022-12-19  Patrick Palka  <ppalka@redhat.com>
+
+	PR c++/101886
+	* g++.dg/concepts/auto5.C: New test.
+
+2022-12-19  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c/108043
+	* gcc.dg/pr108043.c: New test.
+	* gcc.dg/c99-complit-2.c (foo): Adjust expected diagnostics for
+	complit with function type.
+
+2022-12-19  Marek Polacek  <polacek@redhat.com>
+
+	PR c/98487
+	* c-c++-common/Wsuggest-attribute-1.c: New test.
+
+2022-12-19  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/108164
+	* gcc.dg/pr108164.c: New testcase.
+
+2022-12-19  Ju-Zhe Zhong  <juzhe.zhong@rivai.ai>
+
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c: New test.
+
+2022-12-19  Ju-Zhe Zhong  <juzhe.zhong@rivai.ai>
+
+	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_call-4.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c: New test.
+
+2022-12-19  Ju-Zhe Zhong  <juzhe.zhong@rivai.ai>
+
+	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c: New test.
+
+2022-12-19  Ju-Zhe Zhong  <juzhe.zhong@rivai.ai>
+
+	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c: New test.
+
+2022-12-19  Ju-Zhe Zhong  <juzhe.zhong@rivai.ai>
+
+	* gcc.target/riscv/rvv/rvv.exp: Adjust to enable tests for VSETVL PASS.
+	* gcc.target/riscv/rvv/vsetvl/dump-1.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c: New test.
+	* gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c: New test.
+
+2022-12-19  Kito Cheng  <kito.cheng@sifive.com>
+
+	* gcc.target/riscv/rvv/base/mov-1.c: Simplify operand check.
+	* gcc.target/riscv/rvv/base/mov-10.c: Ditto.
+	* gcc.target/riscv/rvv/base/mov-11.c: Ditto.
+	* gcc.target/riscv/rvv/base/mov-12.c: Ditto.
+	* gcc.target/riscv/rvv/base/mov-2.c: Ditto.
+	* gcc.target/riscv/rvv/base/mov-3.c: Ditto.
+	* gcc.target/riscv/rvv/base/mov-4.c: Ditto.
+	* gcc.target/riscv/rvv/base/mov-5.c: Ditto.
+	* gcc.target/riscv/rvv/base/mov-6.c: Ditto.
+	* gcc.target/riscv/rvv/base/mov-8.c: Ditto.
+	* gcc.target/riscv/rvv/base/mov-9.c: Ditto.
+	* gcc.target/riscv/rvv/base/vread_csr.c: Ditto.
+	* gcc.target/riscv/rvv/base/vsetvl-1.c: Ditto.
+	* gcc.target/riscv/rvv/base/vwrite_csr.c: Ditto.
+
+2022-12-19  Jakub Jelinek  <jakub@redhat.com>
+
+	PR testsuite/108151
+	* gcc.dg/pr64536.c (bar): Cast long to __INTPTR_TYPE__
+	before casting to long *.
+
+2022-12-19  Jakub Jelinek  <jakub@redhat.com>
+
+	PR testsuite/108151
+	* gcc.dg/pr64536.c (bar): Use casts to __INTPTR_TYPE__ rather than
+	long when casting pointer to integral type.
+
+2022-12-19  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/108140
+	* gcc.target/aarch64/acle/pr108140.c: New test.
+
+2022-12-19  Jakub Jelinek  <jakub@redhat.com>
+
+	PR fortran/107397
+	* gfortran.dg/pr107397.f90: Adjust expected diagnostic wording and
+	add space between dg-error string and closing }.
+
+2022-12-19  Kito Cheng  <kito.cheng@sifive.com>
+
+	* gcc.target/riscv/rvv/base/vread_csr.c: Use specific option
+	instead.
+	* gcc.target/riscv/rvv/base/vwrite_csr.c: Ditto.
+
+2022-12-19  Jiufu Guo  <guojiufu@linux.ibm.com>
+
+	PR target/106708
+	* gcc.target/powerpc/pr106708.c: New test.
+
+2022-12-19  Kito Cheng  <kito.cheng@sifive.com>
+
+	* gcc.target/riscv/rvv/base/mov-1.c: Use double quotes to
+	include riscv_vector.h rather than angle brackets.
+	* gcc.target/riscv/rvv/base/mov-10.c: Ditto.
+	* gcc.target/riscv/rvv/base/mov-11.c: Ditto.
+	* gcc.target/riscv/rvv/base/mov-12.c: Ditto.
+	* gcc.target/riscv/rvv/base/mov-13.c: Ditto.
+	* gcc.target/riscv/rvv/base/mov-2.c: Ditto.
+	* gcc.target/riscv/rvv/base/mov-3.c: Ditto.
+	* gcc.target/riscv/rvv/base/mov-4.c: Ditto.
+	* gcc.target/riscv/rvv/base/mov-5.c: Ditto.
+	* gcc.target/riscv/rvv/base/mov-6.c: Ditto.
+	* gcc.target/riscv/rvv/base/mov-7.c: Ditto.
+	* gcc.target/riscv/rvv/base/mov-8.c: Ditto.
+	* gcc.target/riscv/rvv/base/mov-9.c: Ditto.
+	* gcc.target/riscv/rvv/base/vread_csr.c: Ditto.
+	* gcc.target/riscv/rvv/base/vsetvl-1.c: Ditto.
+	* gcc.target/riscv/rvv/base/vwrite_csr.c: Ditto.
+
+2022-12-18  Gaius Mulley  <gaiusmod2@gmail.com>
+
+	* gm2/pimcoroutines/run/pass/testtime.mod: Reduce sleep times in
+	the test by a factor of 25.
+
+2022-12-18  Steve Kargl  <kargl@gcc.gnu.org>
+
+	PR fortran/107397
+	* gfortran.dg/pr107397.f90: New test.
+
+2022-12-17  Patrick Palka  <ppalka@redhat.com>
+
+	PR c++/107437
+	PR c++/87765
+	* g++.dg/cpp1y/lambda-generic-107437.C: New test.
+	* g++.dg/cpp1z/constexpr-lambda26.C: Remove dg-ice.
+
 2022-12-16  John David Anglin  <danglin@gcc.gnu.org>
 
 	* lib/target-supports.exp (check_effective_target_static): Return 0
diff --git a/gcc/testsuite/c-c++-common/Wsuggest-attribute-1.c b/gcc/testsuite/c-c++-common/Wsuggest-attribute-1.c
new file mode 100644
index 0000000..8b5b398
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/Wsuggest-attribute-1.c
@@ -0,0 +1,36 @@
+/* PR c/98487 */
+/* { dg-do compile { target { c || c++11 } } } */
+/* { dg-options "-Wsuggest-attribute=format" } */
+
+#include <stdarg.h>
+
+[[gnu::__format__(__printf__, 1, 2)]]
+void
+do_printf(const char * const a0, ...)
+{
+  va_list ap;
+  va_start(ap, a0);
+  __builtin_vprintf(a0, ap);
+  va_end(ap);
+}
+
+[[gnu::__format__(__scanf__, 1, 2)]]
+void
+do_scanf(const char * const a0, ...)
+{
+  va_list ap;
+  va_start(ap, a0);
+  __builtin_vscanf(a0, ap);
+  va_end(ap);
+}
+
+struct tm;
+
+[[gnu::__format__(__strftime__, 1, 0)]]
+void
+do_strftime(const char * const a0, struct tm * a1)
+{
+  char buff[256];
+  __builtin_strftime(buff, sizeof(buff), a0, a1);
+  __builtin_puts(buff);
+}
diff --git a/gcc/testsuite/g++.dg/concepts/auto5.C b/gcc/testsuite/g++.dg/concepts/auto5.C
new file mode 100644
index 0000000..f1d653e
--- /dev/null
+++ b/gcc/testsuite/g++.dg/concepts/auto5.C
@@ -0,0 +1,9 @@
+// PR c++/101886
+// { dg-do compile { target c++17_only } }
+// { dg-options "-fconcepts-ts" }
+
+template<typename...> struct A { };
+
+A<int, int> a;
+A<auto, auto> b1 = a;
+A<auto, auto> b2 = a;
diff --git a/gcc/testsuite/g++.dg/cpp2a/srcloc10.C b/gcc/testsuite/g++.dg/cpp2a/srcloc10.C
index 1be78d9..aa8cf98 100644
--- a/gcc/testsuite/g++.dg/cpp2a/srcloc10.C
+++ b/gcc/testsuite/g++.dg/cpp2a/srcloc10.C
@@ -10,4 +10,4 @@ namespace std {
 }
 
 auto x = __builtin_source_location ();	// { dg-error "'std::source_location::__impl' does not contain only non-static data members '_M_file_name', '_M_function_name', '_M_line' and '_M_column'" }
-// { dg-message "evaluating '__builtin_source_location'" "" { target *-*-* } .-1 }
+// { dg-message "using '__builtin_source_location'" "" { target *-*-* } .-1 }
diff --git a/gcc/testsuite/g++.dg/cpp2a/srcloc11.C b/gcc/testsuite/g++.dg/cpp2a/srcloc11.C
index abc850f..07281ca 100644
--- a/gcc/testsuite/g++.dg/cpp2a/srcloc11.C
+++ b/gcc/testsuite/g++.dg/cpp2a/srcloc11.C
@@ -10,4 +10,4 @@ namespace std {
 }
 
 auto x = __builtin_source_location ();	// { dg-error "'std::source_location::__impl' does not contain only non-static data members '_M_file_name', '_M_function_name', '_M_line' and '_M_column'" }
-// { dg-message "evaluating '__builtin_source_location'" "" { target *-*-* } .-1 }
+// { dg-message "using '__builtin_source_location'" "" { target *-*-* } .-1 }
diff --git a/gcc/testsuite/g++.dg/cpp2a/srcloc12.C b/gcc/testsuite/g++.dg/cpp2a/srcloc12.C
index 49a7e56..445c4a1 100644
--- a/gcc/testsuite/g++.dg/cpp2a/srcloc12.C
+++ b/gcc/testsuite/g++.dg/cpp2a/srcloc12.C
@@ -11,4 +11,4 @@ namespace std {
 }
 
 auto x = __builtin_source_location ();	// { dg-error "'std::source_location::__impl::_M_file_name' does not have 'const char \\*' type" }
-// { dg-message "evaluating '__builtin_source_location'" "" { target *-*-* } .-1 }
+// { dg-message "using '__builtin_source_location'" "" { target *-*-* } .-1 }
diff --git a/gcc/testsuite/g++.dg/cpp2a/srcloc13.C b/gcc/testsuite/g++.dg/cpp2a/srcloc13.C
index ee7b124..d63f6c7 100644
--- a/gcc/testsuite/g++.dg/cpp2a/srcloc13.C
+++ b/gcc/testsuite/g++.dg/cpp2a/srcloc13.C
@@ -12,4 +12,4 @@ namespace std {
 }
 
 auto x = __builtin_source_location ();	// { dg-error "'std::source_location::__impl::_M_line' does not have integral type" }
-// { dg-message "evaluating '__builtin_source_location'" "" { target *-*-* } .-1 }
+// { dg-message "using '__builtin_source_location'" "" { target *-*-* } .-1 }
diff --git a/gcc/testsuite/g++.dg/cpp2a/srcloc3.C b/gcc/testsuite/g++.dg/cpp2a/srcloc3.C
index 29587e4..324e03c 100644
--- a/gcc/testsuite/g++.dg/cpp2a/srcloc3.C
+++ b/gcc/testsuite/g++.dg/cpp2a/srcloc3.C
@@ -2,4 +2,4 @@
 
 auto x = __builtin_source_location ();	// { dg-error "'source_location' is not a member of 'std'" }
 // { dg-message "std::source_location' is defined in header '<source_location>'; did you forget to '#include <source_location>'" "" { target *-*-* } .-1 }
-// { dg-message "evaluating '__builtin_source_location'" "" { target *-*-* } .-2 }
+// { dg-message "using '__builtin_source_location'" "" { target *-*-* } .-2 }
diff --git a/gcc/testsuite/g++.dg/cpp2a/srcloc4.C b/gcc/testsuite/g++.dg/cpp2a/srcloc4.C
index c10f64b..9e92c44 100644
--- a/gcc/testsuite/g++.dg/cpp2a/srcloc4.C
+++ b/gcc/testsuite/g++.dg/cpp2a/srcloc4.C
@@ -5,4 +5,4 @@ namespace std {
 }
 
 auto x = __builtin_source_location ();	// { dg-error "'void std::source_location\\(\\)' is not a type" }
-// { dg-message "evaluating '__builtin_source_location'" "" { target *-*-* } .-1 }
+// { dg-message "using '__builtin_source_location'" "" { target *-*-* } .-1 }
diff --git a/gcc/testsuite/g++.dg/cpp2a/srcloc5.C b/gcc/testsuite/g++.dg/cpp2a/srcloc5.C
index ce7170b..ed4b935 100644
--- a/gcc/testsuite/g++.dg/cpp2a/srcloc5.C
+++ b/gcc/testsuite/g++.dg/cpp2a/srcloc5.C
@@ -6,4 +6,4 @@ namespace std {
 
 auto x = __builtin_source_location ();	// { dg-error "'std::source_location'\[^\n\r]*is not a class type" }
 // { dg-error "'__impl' is not a member of 'std::source_location'" "" { target *-*-* } .-1 }
-// { dg-message "evaluating '__builtin_source_location'" "" { target *-*-* } .-2 }
+// { dg-message "using '__builtin_source_location'" "" { target *-*-* } .-2 }
diff --git a/gcc/testsuite/g++.dg/cpp2a/srcloc6.C b/gcc/testsuite/g++.dg/cpp2a/srcloc6.C
index 89c6887..bec51e2 100644
--- a/gcc/testsuite/g++.dg/cpp2a/srcloc6.C
+++ b/gcc/testsuite/g++.dg/cpp2a/srcloc6.C
@@ -6,4 +6,4 @@ namespace std {
 }
 
 auto x = __builtin_source_location ();	// { dg-error "'__impl' is not a member of 'std::source_location'" }
-// { dg-message "evaluating '__builtin_source_location'" "" { target *-*-* } .-1 }
+// { dg-message "using '__builtin_source_location'" "" { target *-*-* } .-1 }
diff --git a/gcc/testsuite/g++.dg/cpp2a/srcloc7.C b/gcc/testsuite/g++.dg/cpp2a/srcloc7.C
index ef56edf..c81fa63 100644
--- a/gcc/testsuite/g++.dg/cpp2a/srcloc7.C
+++ b/gcc/testsuite/g++.dg/cpp2a/srcloc7.C
@@ -7,4 +7,4 @@ namespace std {
 }
 
 auto x = __builtin_source_location ();	// { dg-error "'std::source_location::__impl\\(\\)' is not a type" }
-// { dg-message "evaluating '__builtin_source_location'" "" { target *-*-* } .-1 }
+// { dg-message "using '__builtin_source_location'" "" { target *-*-* } .-1 }
diff --git a/gcc/testsuite/g++.dg/cpp2a/srcloc8.C b/gcc/testsuite/g++.dg/cpp2a/srcloc8.C
index caef812..158cc3f 100644
--- a/gcc/testsuite/g++.dg/cpp2a/srcloc8.C
+++ b/gcc/testsuite/g++.dg/cpp2a/srcloc8.C
@@ -7,4 +7,4 @@ namespace std {
 }
 
 auto x = __builtin_source_location ();	// { dg-error "'std::source_location::__impl()' is not a class type" }
-// { dg-message "evaluating '__builtin_source_location'" "" { target *-*-* } .-1 }
+// { dg-message "using '__builtin_source_location'" "" { target *-*-* } .-1 }
diff --git a/gcc/testsuite/g++.dg/cpp2a/srcloc9.C b/gcc/testsuite/g++.dg/cpp2a/srcloc9.C
index 47fce00..618e093 100644
--- a/gcc/testsuite/g++.dg/cpp2a/srcloc9.C
+++ b/gcc/testsuite/g++.dg/cpp2a/srcloc9.C
@@ -8,4 +8,4 @@ namespace std {
 }
 
 auto x = __builtin_source_location ();	// { dg-error "'std::source_location::__impl' does not contain only non-static data members '_M_file_name', '_M_function_name', '_M_line' and '_M_column'" }
-// { dg-message "evaluating '__builtin_source_location'" "" { target *-*-* } .-1 }
+// { dg-message "using '__builtin_source_location'" "" { target *-*-* } .-1 }
diff --git a/gcc/testsuite/g++.dg/modules/pr100881_a.C b/gcc/testsuite/g++.dg/modules/pr100881_a.C
new file mode 100644
index 0000000..9554693
--- /dev/null
+++ b/gcc/testsuite/g++.dg/modules/pr100881_a.C
@@ -0,0 +1,34 @@
+// PR c++/100881
+// { dg-additional-options "-std=c++20 -fmodules-ts" }
+// { dg-module-cmi pr100881 }
+module;
+#include <source_location>
+export module pr100881;
+
+export
+consteval int
+current_line_fn(const std::source_location& loc = std::source_location::current())
+{
+  return loc.line();
+}
+
+export
+struct current_line_cls
+{
+  int line = std::source_location::current().line();
+};
+
+export
+template<class T>
+consteval int
+current_line_fn_tmpl(const std::source_location& loc = std::source_location::current())
+{
+  return loc.line();
+}
+
+export
+template<class T>
+struct current_line_cls_tmpl
+{
+  int line = std::source_location::current().line();
+};
diff --git a/gcc/testsuite/g++.dg/modules/pr100881_b.C b/gcc/testsuite/g++.dg/modules/pr100881_b.C
new file mode 100644
index 0000000..7f25b21
--- /dev/null
+++ b/gcc/testsuite/g++.dg/modules/pr100881_b.C
@@ -0,0 +1,8 @@
+// PR c++/100881
+// { dg-additional-options "-std=c++20 -fmodules-ts" }
+import pr100881;
+
+static_assert(current_line_fn() == 5);
+static_assert(current_line_cls{}.line == 6);
+static_assert(current_line_fn_tmpl<int>() == 7);
+static_assert(current_line_cls_tmpl<int>{}.line == 8);
diff --git a/gcc/testsuite/gcc.dg/c99-complit-2.c b/gcc/testsuite/gcc.dg/c99-complit-2.c
index 8120ce8..5e1b5be 100644
--- a/gcc/testsuite/gcc.dg/c99-complit-2.c
+++ b/gcc/testsuite/gcc.dg/c99-complit-2.c
@@ -23,7 +23,7 @@ foo (int a)
   /* { dg-error "init" "incomplete union type" { target *-*-* } .-1 } */
   /* { dg-error "invalid use of undefined type" "" { target *-*-* } .-2 } */
   (void (void)) { 0 }; /* { dg-bogus "warning" "warning in place of error" } */
-  /* { dg-error "init" "function type" { target *-*-* } .-1 } */
+  /* { dg-error "compound literal has function type" "function type" { target *-*-* } .-1 } */
   (int [a]) { 1 }; /* { dg-bogus "warning" "warning in place of error" } */
   /* { dg-error "init|variable" "VLA type" { target *-*-* } .-1 } */
   /* Initializers must not attempt to initialize outside the object
diff --git a/gcc/testsuite/gcc.dg/pr108043.c b/gcc/testsuite/gcc.dg/pr108043.c
new file mode 100644
index 0000000..0cc0700
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr108043.c
@@ -0,0 +1,12 @@
+/* PR c/108043 */
+/* { dg-do compile } */
+/* { dg-options "" } */
+
+typedef void F (void);
+
+void
+foo (void)
+{
+  (F) {};		/* { dg-error "compound literal has function type" } */
+  (F) { foo };		/* { dg-error "compound literal has function type" } */
+}
diff --git a/gcc/testsuite/gcc.dg/pr108164.c b/gcc/testsuite/gcc.dg/pr108164.c
new file mode 100644
index 0000000..d76d557
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr108164.c
@@ -0,0 +1,19 @@
+/* { dg-do run } */
+/* { dg-options "-O3 -fno-tree-dce" } */
+
+int a, b, c;
+int main()
+{
+  int e = -1;
+  short f = -1;
+  for (; c < 1; c++)
+    while (f >= e)
+      f++;
+  for (; a < 2; a++) {
+    short g = ~(~b | ~f);
+    int h = -g;
+    int i = (3 / ~h) / ~b;
+    b = i;
+  }
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.dg/pr64536.c b/gcc/testsuite/gcc.dg/pr64536.c
index f2728fb..18afa9d 100644
--- a/gcc/testsuite/gcc.dg/pr64536.c
+++ b/gcc/testsuite/gcc.dg/pr64536.c
@@ -40,8 +40,8 @@ bar (int x)
 	      h->q = *f;
 	    }
 	  else
-	    i = (long *) (h->q = *f);
-	  *c++ = (long) f;
+	    i = (long *) (__INTPTR_TYPE__) (h->q = *f);
+	  *c++ = (__INTPTR_TYPE__) f;
 	  e += 6;
 	}
       else
@@ -54,8 +54,8 @@ bar (int x)
 	      h->q = *f;
 	    }
 	  else
-	    i = (long *) (h->q = *f);
-	  *c++ = (long) f;
+	    i = (long *) (__INTPTR_TYPE__) (h->q = *f);
+	  *c++ = (__INTPTR_TYPE__) f;
 	  e += 6;
 	}
     }
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/pr108140.c b/gcc/testsuite/gcc.target/aarch64/acle/pr108140.c
new file mode 100644
index 0000000..967928a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/acle/pr108140.c
@@ -0,0 +1,15 @@
+/* PR target/108140  */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#include<arm_acle.h>
+
+int
+main(int argc, char *argv[])
+{
+	unsigned long long input = argc-1;
+	unsigned long long v = __clz(__rbit(input));
+	__builtin_printf("%d %d\n", argc, v >= 64 ? 123 : 456);
+	return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/powerpc/pr103743.c b/gcc/testsuite/gcc.target/powerpc/pr103743.c
new file mode 100644
index 0000000..41c686b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr103743.c
@@ -0,0 +1,52 @@
+/* { dg-options "-O2" } */
+/* { dg-do compile { target has_arch_ppc64 } } */
+
+/* { dg-final { scan-assembler-times {\mcmpldi\M} 10  } } */
+/* { dg-final { scan-assembler-times {\mcmpdi\M} 4  } } */
+/* { dg-final { scan-assembler-times {\mrotldi\M} 14  } } */
+
+int foo (int a);
+
+int __attribute__ ((noinline)) udi_fun (unsigned long long in)
+{
+  if (in == (0x8642000000000000ULL))
+    return foo (1);
+  if (in == (0x7642000000000000ULL))
+    return foo (12);
+  if (in == (0x8000000000000000ULL))
+    return foo (32);
+  if (in == (0x8700000000000091ULL))
+    return foo (33);
+  if (in == (0x8642FFFFFFFFFFFFULL))
+    return foo (46);
+  if (in == (0x7642FFFFFFFFFFFFULL))
+    return foo (51);
+  if (in == (0x7567000000ULL))
+    return foo (9);
+  if (in == (0xFFF8567FFFFFFFFFULL))
+    return foo (19);
+
+  return 0;
+}
+
+int __attribute__ ((noinline)) di_fun (long long in)
+{
+  if (in == (0x8642000000000000LL))
+    return foo (1);
+  if (in == (0x7642000000000000LL))
+    return foo (12);
+  if (in == (0x8000000000000000LL))
+    return foo (32);
+  if (in == (0x8700000000000091LL))
+    return foo (33);
+  if (in == (0x8642FFFFFFFFFFFFLL))
+    return foo (46);
+  if (in == (0x7642FFFFFFFFFFFFLL))
+    return foo (51);
+  if (in == (0x7567000000LL))
+    return foo (9);
+  if (in == (0xFFF8567FFFFFFFFFLL))
+    return foo (19);
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/pr103743_1.c b/gcc/testsuite/gcc.target/powerpc/pr103743_1.c
new file mode 100644
index 0000000..e128aae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr103743_1.c
@@ -0,0 +1,95 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -std=c99" } */
+
+int
+foo (int a)
+{
+  return a + 6;
+}
+
+int __attribute__ ((noipa)) udi_fun (unsigned long long in)
+{
+  if (in == (0x8642000000000000ULL))
+    return foo (1);
+  if (in == (0x7642000000000000ULL))
+    return foo (12);
+  if (in == (0x8000000000000000ULL))
+    return foo (32);
+  if (in == (0x8700000000000091ULL))
+    return foo (33);
+  if (in == (0x8642FFFFFFFFFFFFULL))
+    return foo (46);
+  if (in == (0x7642FFFFFFFFFFFFULL))
+    return foo (51);
+  if (in == (0x7567000000ULL))
+    return foo (9);
+  if (in == (0xFFF8567FFFFFFFFFULL))
+    return foo (19);
+  
+  return 0;
+}
+
+int __attribute__ ((noipa)) di_fun (long long in)
+{
+  if (in == (0x8642000000000000LL))
+    return foo (1);
+  if (in == (0x7642000000000000LL))
+    return foo (12);
+  if (in == (0x8000000000000000LL))
+    return foo (32);
+  if (in == (0x8700000000000091LL))
+    return foo (33);
+  if (in == (0x8642FFFFFFFFFFFFLL))
+    return foo (46);
+  if (in == (0x7642FFFFFFFFFFFFLL))
+    return foo (51);
+  return 0;
+}
+
+int
+main ()
+{
+  int e = 0;
+  if (udi_fun (6) != 0)
+    e++;
+  if (udi_fun (0x8642000000000000ULL) != foo (1))
+    e++;
+  if (udi_fun (0x7642000000000000ULL) != foo (12))
+    e++;
+  if (udi_fun (0x8000000000000000ULL) != foo (32))
+    e++;
+  if (udi_fun (0x8700000000000091ULL) != foo (33))
+    e++;
+  if (udi_fun (0x8642FFFFFFFFFFFFULL) != foo (46))
+    e++;
+  if (udi_fun (0x7642FFFFFFFFFFFFULL) != foo (51))
+    e++;
+  if (udi_fun (0x7567000000ULL) != foo (9))
+    e++;
+  if (udi_fun (0xFFF8567FFFFFFFFFULL) != foo (19))
+    e++;
+
+  if (di_fun (6) != 0)
+    e++;
+  if (di_fun (0x8642000000000000LL) != foo (1))
+    e++;
+  if (di_fun (0x7642000000000000LL) != foo (12))
+    e++;
+  if (di_fun (0x8000000000000000LL) != foo (32))
+    e++;
+  if (di_fun (0x8700000000000091LL) != foo (33))
+    e++;
+  if (di_fun (0x8642FFFFFFFFFFFFLL) != foo (46))
+    e++;
+  if (di_fun (0x7642FFFFFFFFFFFFLL) != foo (51))
+    e++;
+  if (udi_fun (0x7567000000LL) != foo (9))
+    e++;
+  if (udi_fun (0xFFF8567FFFFFFFFFLL) != foo (19))
+    e++;
+
+  if (e)
+    __builtin_abort ();
+  return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/powerpc/pr106708.c b/gcc/testsuite/gcc.target/powerpc/pr106708.c
new file mode 100644
index 0000000..ddb9160
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr106708.c
@@ -0,0 +1,41 @@
+/* PR target/106708 */
+/* { dg-do run } */
+/* { dg-options "-O2 -mno-prefixed -save-temps" } */
+/* { dg-require-effective-target has_arch_ppc64 } */
+
+long long arr[]
+  = {0xffffffff7cdeab55LL, 0x98765432LL, 0xabcd0000LL};
+
+void __attribute__ ((__noipa__)) test_li_xoris (long long *arg)
+{
+  *arg = 0xffffffff7cdeab55LL;
+}
+/* { dg-final { scan-assembler-times {\mli .*,-21675\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxoris .*0x8321\M} 1 } } */
+
+void __attribute__ ((__noipa__)) test_li_oris (long long *arg)
+{
+  *arg = 0x98765432LL;
+}
+/* { dg-final { scan-assembler-times {\mli .*,21554\M} 1 } } */
+/* { dg-final { scan-assembler-times {\moris .*0x9876\M} 1 } } */
+
+void __attribute__ ((__noipa__)) test_lis_rldicl (long long *arg)
+{
+  *arg = 0xabcd0000LL;
+}
+/* { dg-final { scan-assembler-times {\mlis .*,0xabcd\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mrldicl .*,0,32\M} 1 } } */
+
+int
+main ()
+{
+  long long a[sizeof (arr) / sizeof (arr[0])];
+
+  test_li_xoris (a);
+  test_li_oris (a + 1);
+  test_lis_rldicl (a + 2);
+  if (__builtin_memcmp (a, arr, sizeof (arr)) != 0)
+    __builtin_abort ();
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c
index 6a235e3..fbf2526 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c
@@ -2,13 +2,13 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 /*
 ** mov1:
-**	vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]
-**	vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]
+**	vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov1 (int8_t *in, int8_t *out)
@@ -19,9 +19,9 @@ void mov1 (int8_t *in, int8_t *out)
 
 /*
 ** mov2:
-**	vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]
-**	vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]
+**	vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov2 (int8_t *in, int8_t *out)
@@ -32,9 +32,9 @@ void mov2 (int8_t *in, int8_t *out)
 
 /*
 ** mov3:
-**	vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]
-**	vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]
+**	vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov3 (int8_t *in, int8_t *out)
@@ -45,8 +45,8 @@ void mov3 (int8_t *in, int8_t *out)
 
 /*
 ** mov4:
-**	vl1re8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs1r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl1re8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs1r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov4 (int8_t *in, int8_t *out)
@@ -57,8 +57,8 @@ void mov4 (int8_t *in, int8_t *out)
 
 /*
 ** mov5:
-**	vl2re8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs2r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl2re8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs2r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov5 (int8_t *in, int8_t *out)
@@ -69,8 +69,8 @@ void mov5 (int8_t *in, int8_t *out)
 
 /*
 ** mov6:
-**	vl4re8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs4r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl4re8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs4r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov6 (int8_t *in, int8_t *out)
@@ -81,8 +81,8 @@ void mov6 (int8_t *in, int8_t *out)
 
 /*
 ** mov7:
-**	vl8re8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs8r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl8re8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs8r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov7 (int8_t *in, int8_t *out)
@@ -93,9 +93,9 @@ void mov7 (int8_t *in, int8_t *out)
 
 /*
 ** mov8:
-**	vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]
-**	vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]
+**	vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov8 (uint8_t *in, uint8_t *out)
@@ -106,9 +106,9 @@ void mov8 (uint8_t *in, uint8_t *out)
 
 /*
 ** mov9:
-**	vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]
-**	vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]
+**	vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov9 (uint8_t *in, uint8_t *out)
@@ -119,9 +119,9 @@ void mov9 (uint8_t *in, uint8_t *out)
 
 /*
 ** mov10:
-**	vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]
-**	vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]
+**	vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov10 (uint8_t *in, uint8_t *out)
@@ -132,8 +132,8 @@ void mov10 (uint8_t *in, uint8_t *out)
 
 /*
 ** mov11:
-**	vl1re8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs1r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl1re8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs1r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov11 (uint8_t *in, uint8_t *out)
@@ -144,8 +144,8 @@ void mov11 (uint8_t *in, uint8_t *out)
 
 /*
 ** mov12:
-**	vl2re8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs2r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl2re8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs2r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov12 (uint8_t *in, uint8_t *out)
@@ -156,8 +156,8 @@ void mov12 (uint8_t *in, uint8_t *out)
 
 /*
 ** mov13:
-**	vl4re8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs4r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl4re8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs4r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov13 (uint8_t *in, uint8_t *out)
@@ -168,8 +168,8 @@ void mov13 (uint8_t *in, uint8_t *out)
 
 /*
 ** mov14:
-**	vl8re8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs8r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl8re8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs8r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov14 (uint8_t *in, uint8_t *out)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c
index 10aa829..d628f59 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c
@@ -2,12 +2,12 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h> 
+#include "riscv_vector.h" 
 
 /*
 ** mov1:
-**	vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]
-**	vle8\.v\tv1,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]
+**	vle8\.v\tv1,0\s*\([a-x0-9]+\)
 **  ...
 **  vmv1r\.v\tv2,v1
 **	...
@@ -24,8 +24,8 @@ void mov1 (int8_t *in, int8_t *out)
 
 /*
 ** mov2:
-**	vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]
-**	vle8\.v\tv1,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]
+**	vle8\.v\tv1,0\s*\([a-x0-9]+\)
 **	...
 **  vmv1r\.v\tv2,v1
 **	...
@@ -42,8 +42,8 @@ void mov2 (int8_t *in, int8_t *out)
 
 /*
 ** mov3:
-**	vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]
-**	vle8\.v\tv1,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]
+**	vle8\.v\tv1,0\s*\([a-x0-9]+\)
 **	...
 **  vmv1r\.v\tv2,v1
 **	...
@@ -60,7 +60,7 @@ void mov3 (int8_t *in, int8_t *out)
 
 /*
 ** mov4:
-**	vl1re8\.v\tv1,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl1re8\.v\tv1,0\s*\([a-x0-9]+\)
 **	...
 **  vmv1r\.v\tv2,v1
 **	...
@@ -77,7 +77,7 @@ void mov4 (int8_t *in, int8_t *out)
 
 /*
 ** mov5:
-**	vl2re8\.v\tv2,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl2re8\.v\tv2,0\s*\([a-x0-9]+\)
 **	...
 **  vmv2r\.v\tv4,v2
 **	...
@@ -94,7 +94,7 @@ void mov5 (int8_t *in, int8_t *out)
 
 /*
 ** mov6:
-**	vl4re8\.v\tv4,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl4re8\.v\tv4,0\s*\([a-x0-9]+\)
 **	...
 **  vmv4r\.v\tv8,v4
 **	...
@@ -111,7 +111,7 @@ void mov6 (int8_t *in, int8_t *out)
 
 /*
 ** mov7:
-**	vl8re8\.v\tv8,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl8re8\.v\tv8,0\s*\([a-x0-9]+\)
 **	...
 **  vmv8r\.v\tv16,v8
 **	...
@@ -128,8 +128,8 @@ void mov7 (int8_t *in, int8_t *out)
 
 /*
 ** mov8:
-**	vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]
-**	vle16\.v\tv1,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]
+**	vle16\.v\tv1,0\s*\([a-x0-9]+\)
 **	...
 **  vmv1r\.v\tv2,v1
 **	...
@@ -146,8 +146,8 @@ void mov8 (int16_t *in, int16_t *out)
 
 /*
 ** mov9:
-**	vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]
-**	vle16\.v\tv1,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]
+**	vle16\.v\tv1,0\s*\([a-x0-9]+\)
 **	...
 **  vmv1r\.v\tv2,v1
 **	...
@@ -164,7 +164,7 @@ void mov9 (int16_t *in, int16_t *out)
 
 /*
 ** mov10:
-**	vl1re16\.v\tv1,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl1re16\.v\tv1,0\s*\([a-x0-9]+\)
 **	...
 **  vmv1r\.v\tv2,v1
 **	...
@@ -181,7 +181,7 @@ void mov10 (int16_t *in, int16_t *out)
 
 /*
 ** mov11:
-**	vl2re16\.v\tv2,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl2re16\.v\tv2,0\s*\([a-x0-9]+\)
 **	...
 **  vmv2r\.v\tv4,v2
 **	...
@@ -198,7 +198,7 @@ void mov11 (int16_t *in, int16_t *out)
 
 /*
 ** mov12:
-**	vl4re16\.v\tv4,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl4re16\.v\tv4,0\s*\([a-x0-9]+\)
 **	...
 **  vmv4r\.v\tv8,v4
 **	...
@@ -215,7 +215,7 @@ void mov12 (int16_t *in, int16_t *out)
 
 /*
 ** mov13:
-**	vl8re16\.v\tv8,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl8re16\.v\tv8,0\s*\([a-x0-9]+\)
 **	...
 **  vmv8r\.v\tv16,v8
 **	...
@@ -232,8 +232,8 @@ void mov13 (int32_t *in, int32_t *out)
 
 /*
 ** mov14:
-**	vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]
-**	vle32\.v\tv1,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]
+**	vle32\.v\tv1,0\s*\([a-x0-9]+\)
 **	...
 **  vmv1r\.v\tv2,v1
 **	...
@@ -250,7 +250,7 @@ void mov14 (int32_t *in, int32_t *out)
 
 /*
 ** mov15:
-**	vl1re32\.v\tv1,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl1re32\.v\tv1,0\s*\([a-x0-9]+\)
 **	...
 **  vmv1r\.v\tv2,v1
 **	...
@@ -267,7 +267,7 @@ void mov15 (int32_t *in, int32_t *out)
 
 /*
 ** mov16:
-**	vl2re32\.v\tv2,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl2re32\.v\tv2,0\s*\([a-x0-9]+\)
 **	...
 **  vmv2r\.v\tv4,v2
 **	...
@@ -284,7 +284,7 @@ void mov16 (int32_t *in, int32_t *out)
 
 /*
 ** mov17:
-**	vl4re32\.v\tv4,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl4re32\.v\tv4,0\s*\([a-x0-9]+\)
 **	...
 **  vmv4r\.v\tv8,v4
 **	...
@@ -301,7 +301,7 @@ void mov17 (int32_t *in, int32_t *out)
 
 /*
 ** mov18:
-**	vl8re32\.v\tv8,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl8re32\.v\tv8,0\s*\([a-x0-9]+\)
 **	...
 **  vmv8r\.v\tv16,v8
 **	...
@@ -318,7 +318,7 @@ void mov18 (int32_t *in, int32_t *out)
 
 /*
 ** mov19:
-**	vl1re64\.v\tv1,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl1re64\.v\tv1,0\s*\([a-x0-9]+\)
 **	...
 **  vmv1r\.v\tv2,v1
 **	...
@@ -335,7 +335,7 @@ void mov19 (int64_t *in, int64_t *out)
 
 /*
 ** mov20:
-**	vl2re64\.v\tv2,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl2re64\.v\tv2,0\s*\([a-x0-9]+\)
 **	...
 **  vmv2r\.v\tv4,v2
 **	...
@@ -352,7 +352,7 @@ void mov20 (int64_t *in, int64_t *out)
 
 /*
 ** mov21:
-**	vl4re64\.v\tv4,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl4re64\.v\tv4,0\s*\([a-x0-9]+\)
 **	...
 **  vmv4r\.v\tv8,v4
 **	...
@@ -369,7 +369,7 @@ void mov21 (int64_t *in, int64_t *out)
 
 /*
 ** mov22:
-**	vl8re64\.v\tv8,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl8re64\.v\tv8,0\s*\([a-x0-9]+\)
 **	...
 **  vmv8r\.v\tv16,v8
 **	...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c
index f8da5bb..4429c0b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c
@@ -2,12 +2,12 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h> 
+#include "riscv_vector.h" 
 
 /*
 ** mov1:
-**	vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]
-**	vle8\.v\tv1,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]
+**	vle8\.v\tv1,0\s*\([a-x0-9]+\)
 **  ...
 **  vmv1r\.v\tv2,v1
 **	...
@@ -24,8 +24,8 @@ void mov1 (uint8_t *in, uint8_t *out)
 
 /*
 ** mov2:
-**	vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]
-**	vle8\.v\tv1,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]
+**	vle8\.v\tv1,0\s*\([a-x0-9]+\)
 **	...
 **  vmv1r\.v\tv2,v1
 **	...
@@ -42,8 +42,8 @@ void mov2 (uint8_t *in, uint8_t *out)
 
 /*
 ** mov3:
-**	vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]
-**	vle8\.v\tv1,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]
+**	vle8\.v\tv1,0\s*\([a-x0-9]+\)
 **	...
 **  vmv1r\.v\tv2,v1
 **	...
@@ -60,7 +60,7 @@ void mov3 (uint8_t *in, uint8_t *out)
 
 /*
 ** mov4:
-**	vl1re8\.v\tv1,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl1re8\.v\tv1,0\s*\([a-x0-9]+\)
 **	...
 **  vmv1r\.v\tv2,v1
 **	...
@@ -77,7 +77,7 @@ void mov4 (uint8_t *in, uint8_t *out)
 
 /*
 ** mov5:
-**	vl2re8\.v\tv2,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl2re8\.v\tv2,0\s*\([a-x0-9]+\)
 **	...
 **  vmv2r\.v\tv4,v2
 **	...
@@ -94,7 +94,7 @@ void mov5 (uint8_t *in, uint8_t *out)
 
 /*
 ** mov6:
-**	vl4re8\.v\tv4,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl4re8\.v\tv4,0\s*\([a-x0-9]+\)
 **	...
 **  vmv4r\.v\tv8,v4
 **	...
@@ -111,7 +111,7 @@ void mov6 (uint8_t *in, uint8_t *out)
 
 /*
 ** mov7:
-**	vl8re8\.v\tv8,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl8re8\.v\tv8,0\s*\([a-x0-9]+\)
 **	...
 **  vmv8r\.v\tv16,v8
 **	...
@@ -128,8 +128,8 @@ void mov7 (uint8_t *in, uint8_t *out)
 
 /*
 ** mov8:
-**	vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]
-**	vle16\.v\tv1,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]
+**	vle16\.v\tv1,0\s*\([a-x0-9]+\)
 **	...
 **  vmv1r\.v\tv2,v1
 **	...
@@ -146,8 +146,8 @@ void mov8 (uint16_t *in, uint16_t *out)
 
 /*
 ** mov9:
-**	vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]
-**	vle16\.v\tv1,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]
+**	vle16\.v\tv1,0\s*\([a-x0-9]+\)
 **	...
 **  vmv1r\.v\tv2,v1
 **	...
@@ -164,7 +164,7 @@ void mov9 (uint16_t *in, uint16_t *out)
 
 /*
 ** mov10:
-**	vl1re16\.v\tv1,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl1re16\.v\tv1,0\s*\([a-x0-9]+\)
 **	...
 **  vmv1r\.v\tv2,v1
 **	...
@@ -181,7 +181,7 @@ void mov10 (uint16_t *in, uint16_t *out)
 
 /*
 ** mov11:
-**	vl2re16\.v\tv2,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl2re16\.v\tv2,0\s*\([a-x0-9]+\)
 **	...
 **  vmv2r\.v\tv4,v2
 **	...
@@ -198,7 +198,7 @@ void mov11 (uint16_t *in, uint16_t *out)
 
 /*
 ** mov12:
-**	vl4re16\.v\tv4,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl4re16\.v\tv4,0\s*\([a-x0-9]+\)
 **	...
 **  vmv4r\.v\tv8,v4
 **	...
@@ -215,7 +215,7 @@ void mov12 (uint16_t *in, uint16_t *out)
 
 /*
 ** mov13:
-**	vl8re16\.v\tv8,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl8re16\.v\tv8,0\s*\([a-x0-9]+\)
 **	...
 **  vmv8r\.v\tv16,v8
 **	...
@@ -232,8 +232,8 @@ void mov13 (uint32_t *in, uint32_t *out)
 
 /*
 ** mov14:
-**	vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]
-**	vle32\.v\tv1,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]
+**	vle32\.v\tv1,0\s*\([a-x0-9]+\)
 **	...
 **  vmv1r\.v\tv2,v1
 **	...
@@ -250,7 +250,7 @@ void mov14 (uint32_t *in, uint32_t *out)
 
 /*
 ** mov15:
-**	vl1re32\.v\tv1,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl1re32\.v\tv1,0\s*\([a-x0-9]+\)
 **	...
 **  vmv1r\.v\tv2,v1
 **	...
@@ -267,7 +267,7 @@ void mov15 (uint32_t *in, uint32_t *out)
 
 /*
 ** mov16:
-**	vl2re32\.v\tv2,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl2re32\.v\tv2,0\s*\([a-x0-9]+\)
 **	...
 **  vmv2r\.v\tv4,v2
 **	...
@@ -284,7 +284,7 @@ void mov16 (uint32_t *in, uint32_t *out)
 
 /*
 ** mov17:
-**	vl4re32\.v\tv4,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl4re32\.v\tv4,0\s*\([a-x0-9]+\)
 **	...
 **  vmv4r\.v\tv8,v4
 **	...
@@ -301,7 +301,7 @@ void mov17 (uint32_t *in, uint32_t *out)
 
 /*
 ** mov18:
-**	vl8re32\.v\tv8,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl8re32\.v\tv8,0\s*\([a-x0-9]+\)
 **	...
 **  vmv8r\.v\tv16,v8
 **	...
@@ -318,7 +318,7 @@ void mov18 (uint32_t *in, uint32_t *out)
 
 /*
 ** mov19:
-**	vl1re64\.v\tv1,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl1re64\.v\tv1,0\s*\([a-x0-9]+\)
 **	...
 **  vmv1r\.v\tv2,v1
 **	...
@@ -335,7 +335,7 @@ void mov19 (uint64_t *in, uint64_t *out)
 
 /*
 ** mov20:
-**	vl2re64\.v\tv2,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl2re64\.v\tv2,0\s*\([a-x0-9]+\)
 **	...
 **  vmv2r\.v\tv4,v2
 **	...
@@ -352,7 +352,7 @@ void mov20 (uint64_t *in, uint64_t *out)
 
 /*
 ** mov21:
-**	vl4re64\.v\tv4,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl4re64\.v\tv4,0\s*\([a-x0-9]+\)
 **	...
 **  vmv4r\.v\tv8,v4
 **	...
@@ -369,7 +369,7 @@ void mov21 (uint64_t *in, uint64_t *out)
 
 /*
 ** mov22:
-**	vl8re64\.v\tv8,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl8re64\.v\tv8,0\s*\([a-x0-9]+\)
 **	...
 **  vmv8r\.v\tv16,v8
 **	...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c
index 5b8ce40..d34c139 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c
@@ -2,12 +2,12 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h> 
+#include "riscv_vector.h" 
 
 /*
 ** mov14:
-**	vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]
-**	vle32\.v\tv1,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]
+**	vle32\.v\tv1,0\s*\([a-x0-9]+\)
 **	...
 **  vmv1r\.v\tv2,v1
 **	...
@@ -24,7 +24,7 @@ void mov14 (float *in, float *out)
 
 /*
 ** mov15:
-**	vl1re32\.v\tv1,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl1re32\.v\tv1,0\s*\([a-x0-9]+\)
 **	...
 **  vmv1r\.v\tv2,v1
 **	...
@@ -41,7 +41,7 @@ void mov15 (float *in, float *out)
 
 /*
 ** mov16:
-**	vl2re32\.v\tv2,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl2re32\.v\tv2,0\s*\([a-x0-9]+\)
 **	...
 **  vmv2r\.v\tv4,v2
 **	...
@@ -58,7 +58,7 @@ void mov16 (float *in, float *out)
 
 /*
 ** mov17:
-**	vl4re32\.v\tv4,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl4re32\.v\tv4,0\s*\([a-x0-9]+\)
 **	...
 **  vmv4r\.v\tv8,v4
 **	...
@@ -75,7 +75,7 @@ void mov17 (float *in, float *out)
 
 /*
 ** mov18:
-**	vl8re32\.v\tv8,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl8re32\.v\tv8,0\s*\([a-x0-9]+\)
 **	...
 **  vmv8r\.v\tv16,v8
 **	...
@@ -92,7 +92,7 @@ void mov18 (float *in, float *out)
 
 /*
 ** mov19:
-**	vl1re64\.v\tv1,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl1re64\.v\tv1,0\s*\([a-x0-9]+\)
 **	...
 **  vmv1r\.v\tv2,v1
 **	...
@@ -109,7 +109,7 @@ void mov19 (uint64_t *in, uint64_t *out)
 
 /*
 ** mov20:
-**	vl2re64\.v\tv2,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl2re64\.v\tv2,0\s*\([a-x0-9]+\)
 **	...
 **  vmv2r\.v\tv4,v2
 **	...
@@ -126,7 +126,7 @@ void mov20 (uint64_t *in, uint64_t *out)
 
 /*
 ** mov21:
-**	vl4re64\.v\tv4,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl4re64\.v\tv4,0\s*\([a-x0-9]+\)
 **	...
 **  vmv4r\.v\tv8,v4
 **	...
@@ -143,7 +143,7 @@ void mov21 (uint64_t *in, uint64_t *out)
 
 /*
 ** mov22:
-**	vl8re64\.v\tv8,0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl8re64\.v\tv8,0\s*\([a-x0-9]+\)
 **	...
 **  vmv8r\.v\tv16,v8
 **	...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c
index 8c630f3..9515e07 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 
-#include <riscv_vector.h> 
+#include "riscv_vector.h" 
 
 void mov1 (int8_t *in, int8_t *out) 
 { 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c
index b9bdd51..630daf5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c
@@ -2,13 +2,13 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 /*
 ** mov2:
-**	vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]
-**	vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]
+**	vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov2 (int16_t *in, int16_t *out)
@@ -19,9 +19,9 @@ void mov2 (int16_t *in, int16_t *out)
 
 /*
 ** mov3:
-**	vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]
-**	vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]
+**	vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov3 (int16_t *in, int16_t *out)
@@ -32,8 +32,8 @@ void mov3 (int16_t *in, int16_t *out)
 
 /*
 ** mov4:
-**	vl1re16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs1r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl1re16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs1r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov4 (int16_t *in, int16_t *out)
@@ -44,8 +44,8 @@ void mov4 (int16_t *in, int16_t *out)
 
 /*
 ** mov5:
-**	vl2re16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs2r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl2re16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs2r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov5 (int16_t *in, int16_t *out)
@@ -56,8 +56,8 @@ void mov5 (int16_t *in, int16_t *out)
 
 /*
 ** mov6:
-**	vl4re16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs4r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl4re16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs4r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov6 (int16_t *in, int16_t *out)
@@ -68,8 +68,8 @@ void mov6 (int16_t *in, int16_t *out)
 
 /*
 ** mov7:
-**	vl8re16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs8r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl8re16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs8r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov7 (int16_t *in, int16_t *out)
@@ -80,9 +80,9 @@ void mov7 (int16_t *in, int16_t *out)
 
 /*
 ** mov8:
-**	vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]
-**	vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]
+**	vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov8 (uint16_t *in, uint16_t *out)
@@ -93,9 +93,9 @@ void mov8 (uint16_t *in, uint16_t *out)
 
 /*
 ** mov9:
-**	vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]
-**	vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]
+**	vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vse16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov9 (uint16_t *in, uint16_t *out)
@@ -106,8 +106,8 @@ void mov9 (uint16_t *in, uint16_t *out)
 
 /*
 ** mov10:
-**	vl1re16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs1r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl1re16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs1r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov10 (uint16_t *in, uint16_t *out)
@@ -118,8 +118,8 @@ void mov10 (uint16_t *in, uint16_t *out)
 
 /*
 ** mov11:
-**	vl2re16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs2r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl2re16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs2r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov11 (uint16_t *in, uint16_t *out)
@@ -130,8 +130,8 @@ void mov11 (uint16_t *in, uint16_t *out)
 
 /*
 ** mov12:
-**	vl4re16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs4r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl4re16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs4r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov12 (uint16_t *in, uint16_t *out)
@@ -142,8 +142,8 @@ void mov12 (uint16_t *in, uint16_t *out)
 
 /*
 ** mov13:
-**	vl8re16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs8r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl8re16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs8r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov13 (uint16_t *in, uint16_t *out)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c
index a7a89db..bf847bc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c
@@ -2,13 +2,13 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 /*
 ** mov3:
-**	vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]
-**	vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]
+**	vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov3 (int32_t *in, int32_t *out)
@@ -19,8 +19,8 @@ void mov3 (int32_t *in, int32_t *out)
 
 /*
 ** mov4:
-**	vl1re32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs1r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl1re32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs1r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov4 (int32_t *in, int32_t *out)
@@ -31,8 +31,8 @@ void mov4 (int32_t *in, int32_t *out)
 
 /*
 ** mov5:
-**	vl2re32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs2r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl2re32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs2r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov5 (int32_t *in, int32_t *out)
@@ -43,8 +43,8 @@ void mov5 (int32_t *in, int32_t *out)
 
 /*
 ** mov6:
-**	vl4re32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs4r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl4re32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs4r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov6 (int32_t *in, int32_t *out)
@@ -55,8 +55,8 @@ void mov6 (int32_t *in, int32_t *out)
 
 /*
 ** mov7:
-**	vl8re32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs8r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl8re32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs8r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov7 (int32_t *in, int32_t *out)
@@ -67,9 +67,9 @@ void mov7 (int32_t *in, int32_t *out)
 
 /*
 ** mov8:
-**	vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]
-**	vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]
+**	vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov8 (uint32_t *in, uint32_t *out)
@@ -80,8 +80,8 @@ void mov8 (uint32_t *in, uint32_t *out)
 
 /*
 ** mov9:
-**	vl1re32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs1r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl1re32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs1r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov9 (uint32_t *in, uint32_t *out)
@@ -92,8 +92,8 @@ void mov9 (uint32_t *in, uint32_t *out)
 
 /*
 ** mov10:
-**	vl2re32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs2r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl2re32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs2r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov10 (uint32_t *in, uint32_t *out)
@@ -104,8 +104,8 @@ void mov10 (uint32_t *in, uint32_t *out)
 
 /*
 ** mov11:
-**	vl4re32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs4r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl4re32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs4r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov11 (uint32_t *in, uint32_t *out)
@@ -116,8 +116,8 @@ void mov11 (uint32_t *in, uint32_t *out)
 
 /*
 ** mov12:
-**	vl8re32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs8r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl8re32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs8r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov12 (uint32_t *in, uint32_t *out)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c
index e8cfb4b..b23a033 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c
@@ -2,12 +2,12 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 /*
 ** mov4:
-**	vl1re64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs1r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl1re64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs1r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov4 (int64_t *in, int64_t *out)
@@ -18,8 +18,8 @@ void mov4 (int64_t *in, int64_t *out)
 
 /*
 ** mov5:
-**	vl2re64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs2r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl2re64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs2r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov5 (int64_t *in, int64_t *out)
@@ -30,8 +30,8 @@ void mov5 (int64_t *in, int64_t *out)
 
 /*
 ** mov6:
-**	vl4re64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs4r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl4re64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs4r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov6 (int64_t *in, int64_t *out)
@@ -42,8 +42,8 @@ void mov6 (int64_t *in, int64_t *out)
 
 /*
 ** mov7:
-**	vl8re64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs8r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl8re64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs8r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov7 (int64_t *in, int64_t *out)
@@ -54,8 +54,8 @@ void mov7 (int64_t *in, int64_t *out)
 
 /*
 ** mov8:
-**	vl1re64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs1r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl1re64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs1r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov8 (uint64_t *in, uint64_t *out)
@@ -66,8 +66,8 @@ void mov8 (uint64_t *in, uint64_t *out)
 
 /*
 ** mov9:
-**	vl2re64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs2r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl2re64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs2r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov9 (uint64_t *in, uint64_t *out)
@@ -78,8 +78,8 @@ void mov9 (uint64_t *in, uint64_t *out)
 
 /*
 ** mov10:
-**	vl4re64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs4r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl4re64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs4r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov10 (uint64_t *in, uint64_t *out)
@@ -90,8 +90,8 @@ void mov10 (uint64_t *in, uint64_t *out)
 
 /*
 ** mov11:
-**	vl8re64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs8r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl8re64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs8r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov11 (uint64_t *in, uint64_t *out)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c
index 5ca232b..1348eec 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c
@@ -2,13 +2,13 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 /*
 ** mov3:
-**	vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]
-**	vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]
+**	vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vse32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov3 (float *in, float *out)
@@ -19,8 +19,8 @@ void mov3 (float *in, float *out)
 
 /*
 ** mov4:
-**	vl1re32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs1r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl1re32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs1r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov4 (float *in, float *out)
@@ -31,8 +31,8 @@ void mov4 (float *in, float *out)
 
 /*
 ** mov5:
-**	vl2re32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs2r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl2re32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs2r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov5 (float *in, float *out)
@@ -43,8 +43,8 @@ void mov5 (float *in, float *out)
 
 /*
 ** mov6:
-**	vl4re32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs4r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl4re32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs4r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov6 (float *in, float *out)
@@ -55,8 +55,8 @@ void mov6 (float *in, float *out)
 
 /*
 ** mov7:
-**	vl8re32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs8r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl8re32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs8r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov7 (float *in, float *out)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c
index 41fc73b..463be11 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c
@@ -2,12 +2,12 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 /*
 ** mov4:
-**	vl1re64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs1r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl1re64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs1r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov4 (double *in, double *out)
@@ -18,8 +18,8 @@ void mov4 (double *in, double *out)
 
 /*
 ** mov5:
-**	vl2re64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs2r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl2re64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs2r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov5 (double *in, double *out)
@@ -30,8 +30,8 @@ void mov5 (double *in, double *out)
 
 /*
 ** mov6:
-**	vl4re64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs4r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl4re64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs4r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov6 (double *in, double *out)
@@ -42,8 +42,8 @@ void mov6 (double *in, double *out)
 
 /*
 ** mov7:
-**	vl8re64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vs8r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vl8re64\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vs8r\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov7 (double *in, double *out)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c
index d4636e0..c60920a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 /* This testcase is testing whether RISC-V define REGMODE_NATURAL_SIZE.  */
 void foo (int8_t *in, int8_t *out)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c
index 9447b05..26a699d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c
@@ -2,13 +2,13 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 /*
 ** mov1:
-**	vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]
-**	vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vsm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]
+**	vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vsm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov1 (int8_t *in, int8_t *out)
@@ -19,9 +19,9 @@ void mov1 (int8_t *in, int8_t *out)
 
 /*
 ** mov2:
-**	vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]
-**	vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vsm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]
+**	vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vsm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov2 (int8_t *in, int8_t *out)
@@ -32,9 +32,9 @@ void mov2 (int8_t *in, int8_t *out)
 
 /*
 ** mov3:
-**	vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]
-**	vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vsm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]
+**	vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vsm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov3 (int8_t *in, int8_t *out)
@@ -45,9 +45,9 @@ void mov3 (int8_t *in, int8_t *out)
 
 /*
 ** mov4:
-**	vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]
-**	vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vsm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]
+**	vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vsm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov4 (int8_t *in, int8_t *out)
@@ -58,9 +58,9 @@ void mov4 (int8_t *in, int8_t *out)
 
 /*
 ** mov5:
-**	vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]
-**	vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vsm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]
+**	vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vsm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov5 (int8_t *in, int8_t *out)
@@ -71,9 +71,9 @@ void mov5 (int8_t *in, int8_t *out)
 
 /*
 ** mov6:
-**	vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]
-**	vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vsm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]
+**	vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vsm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov6 (int8_t *in, int8_t *out)
@@ -84,9 +84,9 @@ void mov6 (int8_t *in, int8_t *out)
 
 /*
 ** mov7:
-**	vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]
-**	vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vsm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]
+**	vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vsm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov7 (int8_t *in, int8_t *out)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c
index 6d39e3c..7fd38f6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c
@@ -2,18 +2,18 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 /* Test tieable of RVV types with same LMUL.  */
 /*
 ** mov1:
-**	vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]
-**	vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**  addi\t(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),1
-**	vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**  addi\t(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),2
-**	vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]
+**	vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**  addi\t[a-x0-9]+,[a-x0-9]+,1
+**	vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**  addi\t[a-x0-9]+,[a-x0-9]+,2
+**	vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov1 (int8_t *in, int8_t *out, int M)
@@ -28,11 +28,11 @@ void mov1 (int8_t *in, int8_t *out, int M)
 
 /*
 ** mov2:
-**	vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]
-**	vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**	vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**  addi\t(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),1
-**	vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
+**	vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]
+**	vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**	vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
+**  addi\t[a-x0-9]+,[a-x0-9]+,1
+**	vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)
 **  ret
 */
 void mov2 (int8_t *in, int8_t *out, int M)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c
index fa643c5..950b778 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c
@@ -1,8 +1,7 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-O3" } */
-/* { dg-skip-if "test intrinsic using rvv" { *-*-* } { "*" } { "-march=rv*v*zfh*" } } */
+/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d" } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 unsigned long vread_csr_vstart(void) {
   return vread_csr(RVV_VSTART);
@@ -20,7 +19,7 @@ unsigned long vread_csr_vcsr(void) {
   return vread_csr(RVV_VCSR);
 }
 
-/* { dg-final { scan-assembler-times {csrr\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*vstart} 1 } } */
-/* { dg-final { scan-assembler-times {csrr\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*vxsat} 1 } } */
-/* { dg-final { scan-assembler-times {csrr\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*vxrm} 1 } } */
-/* { dg-final { scan-assembler-times {csrr\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*vcsr} 1 } } */
+/* { dg-final { scan-assembler-times {csrr\s+[a-x0-9]+,\s*vstart} 1 } } */
+/* { dg-final { scan-assembler-times {csrr\s+[a-x0-9]+,\s*vxsat} 1 } } */
+/* { dg-final { scan-assembler-times {csrr\s+[a-x0-9]+,\s*vxrm} 1 } } */
+/* { dg-final { scan-assembler-times {csrr\s+[a-x0-9]+,\s*vcsr} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c
index 661f2c9..7921f12 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 
 #include <stddef.h>
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 size_t test_vsetvl_e8mf8_imm0()
 {
@@ -660,91 +660,91 @@ size_t test_vsetvlmax_e64m8()
   return vl;
 }
 
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e8,\s*mf8,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e8,\s*mf8,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*mf8,\s*ta,\s*mu} 2 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e8,\s*mf4,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e8,\s*mf4,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*mf4,\s*ta,\s*mu} 2 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e8,\s*mf2,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e8,\s*mf2,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*mf2,\s*ta,\s*mu} 2 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e8,\s*m1,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e8,\s*m1,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m1,\s*ta,\s*mu} 2 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m1,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e8,\s*m2,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e8,\s*m2,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m2,\s*ta,\s*mu} 2 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m2,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e8,\s*m4,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e8,\s*m4,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m4,\s*ta,\s*mu} 2 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m4,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e8,\s*m8,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e8,\s*m8,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m8,\s*ta,\s*mu} 2 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m8,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e16,\s*mf4,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e16,\s*mf4,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*mf4,\s*ta,\s*mu} 2 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf4,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e16,\s*mf2,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e16,\s*mf2,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*mf2,\s*ta,\s*mu} 2 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf2,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e16,\s*m1,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e16,\s*m1,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m1,\s*ta,\s*mu} 2 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*m1,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e16,\s*m2,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e16,\s*m2,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m2,\s*ta,\s*mu} 2 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*m2,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e16,\s*m4,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e16,\s*m4,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m4,\s*ta,\s*mu} 2 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*m4,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e16,\s*m8,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e16,\s*m8,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m8,\s*ta,\s*mu} 2 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*m8,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e32,\s*mf2,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e32,\s*mf2,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*mf2,\s*ta,\s*mu} 2 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e32,\s*m1,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e32,\s*m1,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m1,\s*ta,\s*mu} 2 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*m1,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e32,\s*m2,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e32,\s*m2,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m2,\s*ta,\s*mu} 2 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*m2,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e32,\s*m4,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e32,\s*m4,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m4,\s*ta,\s*mu} 2 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*m4,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e32,\s*m8,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e32,\s*m8,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m8,\s*ta,\s*mu} 2 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*m8,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e64,\s*m1,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e64,\s*m1,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m1,\s*ta,\s*mu} 2 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e64,\s*m1,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e64,\s*m2,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e64,\s*m2,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m2,\s*ta,\s*mu} 2 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e64,\s*m2,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e64,\s*m4,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e64,\s*m4,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m4,\s*ta,\s*mu} 2 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e64,\s*m4,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e64,\s*m8,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e64,\s*m8,\s*ta,\s*mu} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m8,\s*ta,\s*mu} 2 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e64,\s*m8,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*0,\s*e8,\s*mf8,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*31,\s*e8,\s*mf8,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*ta,\s*mu} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*0,\s*e8,\s*mf4,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*31,\s*e8,\s*mf4,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*ta,\s*mu} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*0,\s*e8,\s*mf2,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*31,\s*e8,\s*mf2,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*ta,\s*mu} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*0,\s*e8,\s*m1,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*31,\s*e8,\s*m1,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*e8,\s*m1,\s*ta,\s*mu} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*0,\s*e8,\s*m2,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*31,\s*e8,\s*m2,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*e8,\s*m2,\s*ta,\s*mu} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*0,\s*e8,\s*m4,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*31,\s*e8,\s*m4,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*e8,\s*m4,\s*ta,\s*mu} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*0,\s*e8,\s*m8,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*31,\s*e8,\s*m8,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*e8,\s*m8,\s*ta,\s*mu} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*0,\s*e16,\s*mf4,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*31,\s*e16,\s*mf4,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*ta,\s*mu} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*0,\s*e16,\s*mf2,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*31,\s*e16,\s*mf2,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*ta,\s*mu} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*0,\s*e16,\s*m1,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*31,\s*e16,\s*m1,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*e16,\s*m1,\s*ta,\s*mu} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*0,\s*e16,\s*m2,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*31,\s*e16,\s*m2,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*e16,\s*m2,\s*ta,\s*mu} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m2,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*0,\s*e16,\s*m4,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*31,\s*e16,\s*m4,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*e16,\s*m4,\s*ta,\s*mu} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m4,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*0,\s*e16,\s*m8,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*31,\s*e16,\s*m8,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*e16,\s*m8,\s*ta,\s*mu} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m8,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*0,\s*e32,\s*mf2,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*31,\s*e32,\s*mf2,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*ta,\s*mu} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*0,\s*e32,\s*m1,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*31,\s*e32,\s*m1,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*e32,\s*m1,\s*ta,\s*mu} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*0,\s*e32,\s*m2,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*31,\s*e32,\s*m2,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*e32,\s*m2,\s*ta,\s*mu} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m2,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*0,\s*e32,\s*m4,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*31,\s*e32,\s*m4,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*e32,\s*m4,\s*ta,\s*mu} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m4,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*0,\s*e32,\s*m8,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*31,\s*e32,\s*m8,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*e32,\s*m8,\s*ta,\s*mu} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m8,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*0,\s*e64,\s*m1,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*31,\s*e64,\s*m1,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*e64,\s*m1,\s*ta,\s*mu} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*0,\s*e64,\s*m2,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*31,\s*e64,\s*m2,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*e64,\s*m2,\s*ta,\s*mu} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m2,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*0,\s*e64,\s*m4,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*31,\s*e64,\s*m4,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*e64,\s*m4,\s*ta,\s*mu} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m4,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*0,\s*e64,\s*m8,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+[a-x0-9]+,\s*31,\s*e64,\s*m8,\s*ta,\s*mu} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*e64,\s*m8,\s*ta,\s*mu} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m8,\s*ta,\s*mu} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c
index e23da4b..e40636e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c
@@ -1,8 +1,7 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-O3" } */
-/* { dg-skip-if "test intrinsic using rvv" { *-*-* } { "*" } { "-march=rv*v*zfh*" } } */
+/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d" } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 void vwrite_csr_vstart(unsigned long value) {
   vwrite_csr(RVV_VSTART, value);
@@ -20,7 +19,7 @@ void vwrite_csr_vcsr(unsigned long value) {
   vwrite_csr(RVV_VCSR, value);
 }
 
-/* { dg-final { scan-assembler-times {csrw\s+vstart,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])} 1 } } */
-/* { dg-final { scan-assembler-times {csrw\s+vxsat,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])} 1 } } */
-/* { dg-final { scan-assembler-times {csrw\s+vxrm,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])} 1 } } */
-/* { dg-final { scan-assembler-times {csrw\s+vcsr,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])} 1 } } */
+/* { dg-final { scan-assembler-times {csrw\s+vstart,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {csrw\s+vxsat,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {csrw\s+vxrm,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {csrw\s+vcsr,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
index 25e09f4..2ed29e2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
+++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
@@ -42,6 +42,8 @@ dg-init
 set CFLAGS "$DEFAULT_CFLAGS -march=$gcc_march -O3"
 dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/base/*.\[cS\]]] \
 	"" $CFLAGS
+gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vsetvl/*.\[cS\]]] \
+	"" $CFLAGS
 
 # All done.
 dg-finish
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/dump-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/dump-1.c
new file mode 100644
index 0000000..fb4edb4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/dump-1.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fdump-rtl-vsetvl-details" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, void * restrict in2, void * restrict out2,  int n, int cond)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vuint16mf4_t v2;
+      *(vuint16mf4_t*)(out + i + 1000) = v2;
+      vbool32_t v4;
+      *(vbool32_t*)(out + i + 3000) = v4;
+      vbool16_t v5;
+      *(vbool16_t*)(out + i + 4000) = v5;
+      vbool8_t v6;
+      *(vbool8_t*)(out + i + 5000) = v6;
+      vbool4_t v7;
+      *(vbool4_t*)(out + i + 6000) = v7;
+      vbool2_t v8;
+      *(vbool2_t*)(out + i + 7000) = v8;
+      vbool1_t v9;
+      *(vbool1_t*)(out + i + 8000) = v9;
+      vuint32mf2_t v10;
+      *(vuint32mf2_t*)(out + i + 100000) = v10;
+    }
+  
+  for (int i = 0; i < n; i++) 
+    {
+      vint8mf8_t v1 = *(vint8mf8_t*)(in + i + 100000);
+      *(vint8mf8_t*)(out + i + 10) = v1;
+    }
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c
new file mode 100644
index 0000000..fbf451f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  for (int i = 0; i < n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*)in;
+    *(vint8mf8_t*)(out + i + 200) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 200);
+    *(vint32mf2_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint64m1_t v = *(vint64m1_t*)(in + 300);
+    *(vint64m1_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 400);
+    *(vfloat32mf2_t*)(out + i + 500) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat64m1_t v = *(vfloat64m1_t*)(in + 500);
+    *(vfloat64m1_t*)(out + i + 600) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint16mf4_t v;
+    *(vint16mf4_t*)(out + i + 700) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c
new file mode 100644
index 0000000..ba289f2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c
@@ -0,0 +1,59 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+
+void f (int32_t * restrict in, int32_t * restrict out, int n, int cond, int cond2, int cond3)
+{
+  for (int i = 0; i < n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*)in;
+    *(vint8mf8_t*)(out + i + 200) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 200);
+    *(vint32mf2_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint64m1_t v = *(vint64m1_t*)(in + 300);
+    *(vint64m1_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 400);
+    *(vfloat32mf2_t*)(out + i + 500) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat64m1_t v = *(vfloat64m1_t*)(in + 500);
+    *(vfloat64m1_t*)(out + i + 600) = v;
+  }
+
+  if (cond == 0)
+  {
+    if (cond2 == 11)
+    {
+      for (int i = 0; i < n; i++)
+      {
+        out[i] = out[i] + 2;
+      }
+    }
+    else if (cond2 == 111)
+    {
+      if (cond3 == 300)
+      {
+        for (int i = 0; i < n; i++)
+        {
+          out[i] = out[i] + out[i];
+        }
+      }
+    }
+  }
+
+  for (int i = 0; i < n; i++) {
+    vint16mf4_t v;
+    *(vint16mf4_t*)(out + i + 700) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c
new file mode 100644
index 0000000..44e8a3f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c
@@ -0,0 +1,63 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int32_t * restrict in, int32_t * restrict out, int n, int cond, int cond2, int cond3)
+{
+  for (int i = 0; i < n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + i);
+    *(vint8mf8_t*)(out + i + 200) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 200 + i);
+    *(vint32mf2_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint64m1_t v = *(vint64m1_t*)(in + 300 + i);
+    *(vint64m1_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 400 + i);
+    *(vfloat32mf2_t*)(out + i + 500) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat64m1_t v = *(vfloat64m1_t*)(in + 500 + i);
+    *(vfloat64m1_t*)(out + i + 600) = v;
+  }
+
+  if (cond == 0)
+  {
+    if (cond2 == 11)
+    {
+      for (int i = 0; i < n; i++)
+      {
+        out[i] = out[i] + 2;
+      }
+    }
+    else if (cond2 == 111)
+    {
+      if (cond3 == 300)
+      {
+        for (int i = 0; i < n; i++)
+        {
+          out[i] = out[i] + out[i];
+        }
+      } else {
+        for (int i = 0; i < n; i++) {
+          vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 2000 + i);
+          *(vfloat32mf2_t*)(out + i + 4000) = v;
+        }
+      }
+    }
+  }
+
+  for (int i = 0; i < n; i++) {
+    vint16mf4_t v;
+    *(vint16mf4_t*)(out + i + 700) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c
new file mode 100644
index 0000000..a8f5af9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c
@@ -0,0 +1,64 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int32_t * restrict in, int32_t * restrict out, int n, int cond, int cond2, int cond3)
+{
+  for (int i = 0; i < n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + i);
+    *(vint8mf8_t*)(out + i + 200) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 200 + i);
+    *(vint32mf2_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint64m1_t v = *(vint64m1_t*)(in + 300 + i);
+    *(vint64m1_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 400 + i);
+    *(vfloat32mf2_t*)(out + i + 500) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat64m1_t v = *(vfloat64m1_t*)(in + 500 + i);
+    *(vfloat64m1_t*)(out + i + 600) = v;
+  }
+
+  if (cond == 0)
+  {
+    if (cond2 == 11)
+    {
+      for (int i = 0; i < n; i++)
+      {
+        out[i] = out[i] + 2;
+      }
+    }
+    else if (cond2 == 111)
+    {
+      if (cond3 == 300)
+      {
+        for (int i = 0; i < n; i++)
+        {
+          out[i] = out[i] + out[i];
+        }
+      } else {
+        for (int i = 0; i < n; i++) {
+          vint8mf2_t v = *(vint8mf2_t*)(in + 2000 + i);
+          *(vint8mf2_t*)(out + i + 4000) = v;
+        }
+      }
+    }
+  }
+
+  for (int i = 0; i < n; i++) {
+    vint16mf4_t v;
+    *(vint16mf4_t*)(out + i + 700) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c
new file mode 100644
index 0000000..31034bc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c
@@ -0,0 +1,64 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int32_t * restrict in, int32_t * restrict out, int n, int cond, int cond2, int cond3)
+{
+  for (int i = 0; i < n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + i);
+    *(vint8mf8_t*)(out + i + 200) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 200 + i);
+    *(vint32mf2_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint64m1_t v = *(vint64m1_t*)(in + 300 + i);
+    *(vint64m1_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 400 + i);
+    *(vfloat32mf2_t*)(out + i + 500) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat64m1_t v = *(vfloat64m1_t*)(in + 500 + i);
+    *(vfloat64m1_t*)(out + i + 600) = v;
+  }
+
+  if (cond == 0)
+  {
+    if (cond2 == 11)
+    {
+      for (int i = 0; i < n; i++)
+      {
+        out[i] = out[i] + 2;
+      }
+    }
+    else if (cond2 == 111)
+    {
+      if (cond3 == 300)
+      {
+        for (int i = 0; i < n; i++)
+        {
+          out[i] = out[i] + out[i];
+        }
+      } else {
+        for (int i = 0; i < n; i++) {
+          vint8mf2_t v = *(vint8mf2_t*)(in + 2000 + i);
+          *(vint8mf2_t*)(out + i + 4000) = v;
+        }
+      }
+    }
+  }
+
+  for (int i = 0; i < n; i++) {
+    vint16m1_t v;
+    *(vint16m1_t*)(out + i + 700) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c
new file mode 100644
index 0000000..dececb4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c
@@ -0,0 +1,58 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int32_t * restrict in, int32_t * restrict out, int n, int cond)
+{
+  for (int i = 0; i < n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*)in;
+    *(vint8mf8_t*)(out + i + 200) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 200);
+    *(vint32mf2_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint64m1_t v = *(vint64m1_t*)(in + 300);
+    *(vint64m1_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 400);
+    *(vfloat32mf2_t*)(out + i + 500) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat64m1_t v = *(vfloat64m1_t*)(in + 500);
+    *(vfloat64m1_t*)(out + i + 600) = v;
+  }
+
+  if (cond == 0) {
+    for (int i = 0; i < n; i++) {
+      vint8mf8_t v = *(vint8mf8_t*)(in + 333);
+      *(vint8mf8_t*)(out + i + 333) = v;
+    }
+  } else if (cond == 1){
+    for (int i = 0; i < n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 444);
+    *(vint32mf2_t*)(out + i + 444) = v;
+  }
+  } else if (cond == 2) {
+    for (int i = 0; i < n; i++) {
+    vint64m1_t v = *(vint64m1_t*)(in + 555);
+    *(vint64m1_t*)(out + i + 555) = v;
+  }
+  } else {
+    for (int i = 0; i < n; i++) {
+    vfloat64m1_t v = *(vfloat64m1_t*)(in + 666);
+    *(vfloat64m1_t*)(out + i + 666) = v;
+  }
+  }
+ 
+  for (int i = 0; i < n; i++) {
+    vint16mf4_t v;
+    *(vint16mf4_t*)(out + i + 700) = v;
+  }
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c
new file mode 100644
index 0000000..161d14c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c
@@ -0,0 +1,143 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int32_t * restrict in, int32_t * restrict out, int n, int cond)
+{
+  for (int i = 0; i < n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*)in;
+    *(vint8mf8_t*)(out + i + 200) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 200);
+    *(vint32mf2_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint64m1_t v = *(vint64m1_t*)(in + 300);
+    *(vint64m1_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 400);
+    *(vfloat32mf2_t*)(out + i + 500) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat64m1_t v = *(vfloat64m1_t*)(in + 500);
+    *(vfloat64m1_t*)(out + i + 600) = v;
+  }
+
+  if (cond == 0) {
+    for (int i = 0; i < n; i++) {
+      vint8mf8_t v = *(vint8mf8_t*)(in + 333);
+      *(vint8mf8_t*)(out + i + 333) = v;
+    }
+  } else if (cond == 1){
+    for (int i = 0; i < n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 444);
+    *(vint32mf2_t*)(out + i + 444) = v;
+  }
+  } else if (cond == 2) {
+    for (int i = 0; i < n; i++) {
+    vint64m1_t v = *(vint64m1_t*)(in + 555);
+    *(vint64m1_t*)(out + i + 555) = v;
+  }
+  } else {
+    for (int i = 0; i < n; i++) {
+    vfloat64m1_t v = *(vfloat64m1_t*)(in + 666);
+    *(vfloat64m1_t*)(out + i + 666) = v;
+  }
+  }
+ 
+   if (cond == 0) {
+    for (int i = 0; i < n; i++) {
+      vint8mf8_t v = *(vint8mf8_t*)(in + 333);
+      *(vint8mf8_t*)(out + i + 333) = v;
+    }
+  } else if (cond == 1){
+    for (int i = 0; i < n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 444);
+    *(vint32mf2_t*)(out + i + 444) = v;
+  }
+  } else if (cond == 2) {
+    for (int i = 0; i < n; i++) {
+    vint64m1_t v = *(vint64m1_t*)(in + 555);
+    *(vint64m1_t*)(out + i + 555) = v;
+  }
+  } else {
+    for (int i = 0; i < n; i++) {
+    vfloat64m1_t v = *(vfloat64m1_t*)(in + 666);
+    *(vfloat64m1_t*)(out + i + 666) = v;
+  }
+  }
+
+    if (cond == 0) {
+    for (int i = 0; i < n; i++) {
+      vint8mf8_t v = *(vint8mf8_t*)(in + 333);
+      *(vint8mf8_t*)(out + i + 333) = v;
+    }
+  } else if (cond == 1){
+    for (int i = 0; i < n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 444);
+    *(vint32mf2_t*)(out + i + 444) = v;
+  }
+  } else if (cond == 2) {
+    for (int i = 0; i < n; i++) {
+    vint64m1_t v = *(vint64m1_t*)(in + 555);
+    *(vint64m1_t*)(out + i + 555) = v;
+  }
+  } else {
+    for (int i = 0; i < n; i++) {
+    vfloat64m1_t v = *(vfloat64m1_t*)(in + 666);
+    *(vfloat64m1_t*)(out + i + 666) = v;
+  }
+  }
+    if (cond == 0) {
+    for (int i = 0; i < n; i++) {
+      vint8mf8_t v = *(vint8mf8_t*)(in + 333);
+      *(vint8mf8_t*)(out + i + 333) = v;
+    }
+  } else if (cond == 1){
+    for (int i = 0; i < n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 444);
+    *(vint32mf2_t*)(out + i + 444) = v;
+  }
+  } else if (cond == 2) {
+    for (int i = 0; i < n; i++) {
+    vint64m1_t v = *(vint64m1_t*)(in + 555);
+    *(vint64m1_t*)(out + i + 555) = v;
+  }
+  } else {
+    for (int i = 0; i < n; i++) {
+    vfloat64m1_t v = *(vfloat64m1_t*)(in + 666);
+    *(vfloat64m1_t*)(out + i + 666) = v;
+  }
+  }
+    if (cond == 0) {
+    for (int i = 0; i < n; i++) {
+      vint8mf8_t v = *(vint8mf8_t*)(in + 333);
+      *(vint8mf8_t*)(out + i + 333) = v;
+    }
+  } else if (cond == 1){
+    for (int i = 0; i < n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 444);
+    *(vint32mf2_t*)(out + i + 444) = v;
+  }
+  } else if (cond == 2) {
+    for (int i = 0; i < n; i++) {
+    vint64m1_t v = *(vint64m1_t*)(in + 555);
+    *(vint64m1_t*)(out + i + 555) = v;
+  }
+  } else {
+    for (int i = 0; i < n; i++) {
+    vfloat64m1_t v = *(vfloat64m1_t*)(in + 666);
+    *(vfloat64m1_t*)(out + i + 666) = v;
+  }
+  }
+  for (int i = 0; i < n; i++) {
+    vint16mf4_t v;
+    *(vint16mf4_t*)(out + i + 700) = v;
+  }
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c
new file mode 100644
index 0000000..84abe55
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c
@@ -0,0 +1,54 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int32_t * restrict in, int32_t * restrict out, int n, int cond)
+{
+  for (int i = 0; i < n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*)in;
+    *(vint8mf8_t*)(out + i + 200) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 200);
+    *(vint32mf2_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint64m1_t v = *(vint64m1_t*)(in + 300);
+    *(vint64m1_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 400);
+    *(vfloat32mf2_t*)(out + i + 500) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat64m1_t v = *(vfloat64m1_t*)(in + 500);
+    *(vfloat64m1_t*)(out + i + 600) = v;
+  }
+
+  if (cond == 0) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 771);
+    *(vint8mf8_t*)(out + 771) = v;
+    vint32mf2_t v2 = *(vint32mf2_t*)(in + 71);
+    *(vint32mf2_t*)(out + 71) = v2;
+    vfloat32mf2_t v3 = *(vfloat32mf2_t*)(in + 17);
+    *(vfloat32mf2_t*)(out + 17) = v3;
+     vuint32mf2_t v4 = *(vuint32mf2_t*)(in + 117);
+    *(vuint32mf2_t*)(out + 117) = v4;
+  } else {
+    vfloat32mf2_t v0 = *(vfloat32mf2_t*)(in + 1123);
+    *(vfloat32mf2_t*)(out + 1123) = v0;
+    vint8mf8_t v = *(vint8mf8_t*)(in + 333);
+    *(vint8mf8_t*)(out + 333) = v;
+    vbool64_t v2 = *(vbool64_t*)(in + 91);
+    *(vbool64_t*)(out + 91) = v2;
+  }
+ 
+  for (int i = 0; i < n; i++) {
+    vint16mf4_t v;
+    *(vint16mf4_t*)(out + i + 700) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c
new file mode 100644
index 0000000..1f3bae2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c
@@ -0,0 +1,59 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int32_t * restrict in, int32_t * restrict out, int n, int cond)
+{
+  for (int i = 0; i < n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*)in;
+    *(vint8mf8_t*)(out + i + 200) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 200);
+    *(vint32mf2_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint64m1_t v = *(vint64m1_t*)(in + 300);
+    *(vint64m1_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 400);
+    *(vfloat32mf2_t*)(out + i + 500) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat64m1_t v = *(vfloat64m1_t*)(in + 500);
+    *(vfloat64m1_t*)(out + i + 600) = v;
+  }
+
+  if (cond == 0) {
+    for (int i = 0; i < n; i++){
+      vint8mf8_t v = *(vint8mf8_t*)(in + 771 + i);
+      *(vint8mf8_t*)(out + 771 + i) = v;
+      vint32mf2_t v2 = *(vint32mf2_t*)(in + 71 + i);
+      *(vint32mf2_t*)(out + 71 + i) = v2;
+      vfloat32mf2_t v3 = *(vfloat32mf2_t*)(in + 17 + i);
+      *(vfloat32mf2_t*)(out + 17 + i) = v3;
+       vuint32mf2_t v4 = *(vuint32mf2_t*)(in + 117 + i);
+      *(vuint32mf2_t*)(out + 117 + i) = v4;
+    }
+  } else {
+    for (int i = 0; i < n; i++){
+      vfloat32mf2_t v0 = *(vfloat32mf2_t*)(in + 1123 + i);
+      *(vfloat32mf2_t*)(out + 1123 + i) = v0;
+      vint8mf8_t v = *(vint8mf8_t*)(in + 333 + i);
+      *(vint8mf8_t*)(out + 333 + i) = v;
+      vbool64_t v2 = *(vbool64_t*)(in + 91 + i);
+      *(vbool64_t*)(out + 91 + i) = v2;
+    }
+  }
+ 
+  for (int i = 0; i < n; i++) {
+    vint16mf4_t v;
+    *(vint16mf4_t*)(out + i + 700) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c
new file mode 100644
index 0000000..33885e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c
@@ -0,0 +1,58 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int32_t * restrict in, int32_t * restrict out, int n, int cond)
+{
+  for (int i = 0; i < n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*)in;
+    *(vint8mf8_t*)(out + i + 200) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 200);
+    *(vint32mf2_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint64m1_t v = *(vint64m1_t*)(in + 300);
+    *(vint64m1_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 400);
+    *(vfloat32mf2_t*)(out + i + 500) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat64m1_t v = *(vfloat64m1_t*)(in + 500);
+    *(vfloat64m1_t*)(out + i + 600) = v;
+  }
+
+  if (cond == 0) {
+    for (int i = 0; i < n; i++){
+      vint8mf8_t v = *(vint8mf8_t*)(in + 771 + i);
+      *(vint8mf8_t*)(out + 771 + i) = v;
+      vint32mf2_t v2 = *(vint32mf2_t*)(in + 71 + i);
+      *(vint32mf2_t*)(out + 71 + i) = v2;
+      vfloat32mf2_t v3 = *(vfloat32mf2_t*)(in + 17 + i);
+      *(vfloat32mf2_t*)(out + 17 + i) = v3;
+       vuint32mf2_t v4 = *(vuint32mf2_t*)(in + 117 + i);
+      *(vuint32mf2_t*)(out + 117 + i) = v4;
+    }
+  } else {
+    vfloat32mf2_t v0 = *(vfloat32mf2_t*)(in + 1123);
+    *(vfloat32mf2_t*)(out + 1123) = v0;
+    vint8mf8_t v = *(vint8mf8_t*)(in + 333);
+    *(vint8mf8_t*)(out + 333) = v;
+    vbool64_t v2 = *(vbool64_t*)(in + 91);
+    *(vbool64_t*)(out + 91) = v2;
+  }
+ 
+  for (int i = 0; i < n; i++) {
+    vint16mf4_t v;
+    *(vint16mf4_t*)(out + i + 700) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c
new file mode 100644
index 0000000..213c48a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c
@@ -0,0 +1,48 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int32_t * restrict in, int32_t * restrict out, int n, int cond)
+{
+  for (int i = 0; i < n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*)in;
+    *(vint8mf8_t*)(out + i + 200) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 200);
+    *(vint32mf2_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint64m1_t v = *(vint64m1_t*)(in + 300);
+    *(vint64m1_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 400);
+    *(vfloat32mf2_t*)(out + i + 500) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat64m1_t v = *(vfloat64m1_t*)(in + 500);
+    *(vfloat64m1_t*)(out + i + 600) = v;
+  }
+
+  if (cond == 0) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 771);
+    *(vint8mf8_t*)(out + 771) = v;
+    vint32mf2_t v2 = *(vint32mf2_t*)(in + 71);
+    *(vint32mf2_t*)(out + 71) = v2;
+    vfloat32mf2_t v3 = *(vfloat32mf2_t*)(in + 17);
+    *(vfloat32mf2_t*)(out + 17) = v3;
+     vuint32mf2_t v4 = *(vuint32mf2_t*)(in + 117);
+    *(vuint32mf2_t*)(out + 117) = v4;
+  }
+ 
+  for (int i = 0; i < n; i++) {
+    vint16mf4_t v;
+    *(vint16mf4_t*)(out + i + 700) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c
new file mode 100644
index 0000000..b8c2cc0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c
@@ -0,0 +1,50 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int32_t * restrict in, int32_t * restrict out, int n, int cond)
+{
+  for (int i = 0; i < n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*)in;
+    *(vint8mf8_t*)(out + i + 200) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 200);
+    *(vint32mf2_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint64m1_t v = *(vint64m1_t*)(in + 300);
+    *(vint64m1_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 400);
+    *(vfloat32mf2_t*)(out + i + 500) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat64m1_t v = *(vfloat64m1_t*)(in + 500);
+    *(vfloat64m1_t*)(out + i + 600) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    out[i] = out[i] + 2;
+  }
+  for (int i = 0; i < n; i++) {
+    out[i] = out[i] + out[i];
+  }
+  for (int i = 0; i < n; i++) {
+    out[i] = out[i] * 2;
+  }
+  for (int i = 0; i < n; i++) {
+    out[i] = out[i] * out[i];
+  }
+  for (int i = 0; i < n; i++) {
+    out[i] = out[i] * out[i] + 100;
+  }
+  for (int i = 0; i < n; i++) {
+    vint16mf4_t v;
+    *(vint16mf4_t*)(out + i + 700) = v;
+  }
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c
new file mode 100644
index 0000000..1f3bae2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c
@@ -0,0 +1,59 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int32_t * restrict in, int32_t * restrict out, int n, int cond)
+{
+  for (int i = 0; i < n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*)in;
+    *(vint8mf8_t*)(out + i + 200) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 200);
+    *(vint32mf2_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint64m1_t v = *(vint64m1_t*)(in + 300);
+    *(vint64m1_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 400);
+    *(vfloat32mf2_t*)(out + i + 500) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat64m1_t v = *(vfloat64m1_t*)(in + 500);
+    *(vfloat64m1_t*)(out + i + 600) = v;
+  }
+
+  if (cond == 0) {
+    for (int i = 0; i < n; i++){
+      vint8mf8_t v = *(vint8mf8_t*)(in + 771 + i);
+      *(vint8mf8_t*)(out + 771 + i) = v;
+      vint32mf2_t v2 = *(vint32mf2_t*)(in + 71 + i);
+      *(vint32mf2_t*)(out + 71 + i) = v2;
+      vfloat32mf2_t v3 = *(vfloat32mf2_t*)(in + 17 + i);
+      *(vfloat32mf2_t*)(out + 17 + i) = v3;
+       vuint32mf2_t v4 = *(vuint32mf2_t*)(in + 117 + i);
+      *(vuint32mf2_t*)(out + 117 + i) = v4;
+    }
+  } else {
+    for (int i = 0; i < n; i++){
+      vfloat32mf2_t v0 = *(vfloat32mf2_t*)(in + 1123 + i);
+      *(vfloat32mf2_t*)(out + 1123 + i) = v0;
+      vint8mf8_t v = *(vint8mf8_t*)(in + 333 + i);
+      *(vint8mf8_t*)(out + 333 + i) = v;
+      vbool64_t v2 = *(vbool64_t*)(in + 91 + i);
+      *(vbool64_t*)(out + 91 + i) = v2;
+    }
+  }
+ 
+  for (int i = 0; i < n; i++) {
+    vint16mf4_t v;
+    *(vint16mf4_t*)(out + i + 700) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c
new file mode 100644
index 0000000..b60a652
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c
@@ -0,0 +1,50 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int32_t * restrict in, int32_t * restrict out, int n, int cond)
+{
+  for (int i = 0; i < n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*)in;
+    *(vint8mf8_t*)(out + i + 200) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 200);
+    *(vint32mf2_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint64m1_t v = *(vint64m1_t*)(in + 300);
+    *(vint64m1_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 400);
+    *(vfloat32mf2_t*)(out + i + 500) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat64m1_t v = *(vfloat64m1_t*)(in + 500);
+    *(vfloat64m1_t*)(out + i + 600) = v;
+  }
+
+  if (cond == 0) {
+    for (int i = 0; i < n; i++){
+      vint8mf8_t v = *(vint8mf8_t*)(in + 771 + i);
+      *(vint8mf8_t*)(out + 771 + i) = v;
+      vint32mf2_t v2 = *(vint32mf2_t*)(in + 71 + i);
+      *(vint32mf2_t*)(out + 71 + i) = v2;
+      vfloat32mf2_t v3 = *(vfloat32mf2_t*)(in + 17 + i);
+      *(vfloat32mf2_t*)(out + 17 + i) = v3;
+       vuint32mf2_t v4 = *(vuint32mf2_t*)(in + 117 + i);
+      *(vuint32mf2_t*)(out + 117 + i) = v4;
+    }
+  }
+ 
+  for (int i = 0; i < n; i++) {
+    vint16mf4_t v;
+    *(vint16mf4_t*)(out + i + 700) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c
new file mode 100644
index 0000000..c4a0451
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c
@@ -0,0 +1,58 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int32_t * restrict in, int32_t * restrict out, int n, int cond)
+{
+  for (int i = 0; i < n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*)in;
+    *(vint8mf8_t*)(out + i + 200) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 200);
+    *(vint32mf2_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint64m1_t v = *(vint64m1_t*)(in + 300);
+    *(vint64m1_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 400);
+    *(vfloat32mf2_t*)(out + i + 500) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat64m1_t v = *(vfloat64m1_t*)(in + 500);
+    *(vfloat64m1_t*)(out + i + 600) = v;
+  }
+
+  if (cond == 0) {
+    for (int i = 0; i < n; i++){
+      vint8mf8_t v = *(vint8mf8_t*)(in + 771 + i);
+      *(vint8mf8_t*)(out + 771 + i) = v;
+      vint32mf2_t v2 = *(vint32mf2_t*)(in + 71 + i);
+      *(vint32mf2_t*)(out + 71 + i) = v2;
+      vfloat32mf2_t v3 = *(vfloat32mf2_t*)(in + 17 + i);
+      *(vfloat32mf2_t*)(out + 17 + i) = v3;
+       vuint32mf2_t v4 = *(vuint32mf2_t*)(in + 117 + i);
+      *(vuint32mf2_t*)(out + 117 + i) = v4;
+    }
+  } else {
+    vfloat32mf2_t v0 = *(vfloat32mf2_t*)(in + 1123);
+    *(vfloat32mf2_t*)(out + 1123) = v0;
+    vint8mf8_t v = *(vint8mf8_t*)(in + 333);
+    *(vint8mf8_t*)(out + 333) = v;
+    vbool64_t v2 = *(vbool64_t*)(in + 91);
+    *(vbool64_t*)(out + 91) = v2;
+  }
+ 
+  for (int i = 0; i < n; i++) {
+    vint16mf4_t v;
+    *(vint16mf4_t*)(out + i + 700) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c
new file mode 100644
index 0000000..36a18a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c
@@ -0,0 +1,41 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int32_t * restrict in, int32_t * restrict out, int n, int cond)
+{
+  for (int i = 0; i < n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*)in;
+    *(vint8mf8_t*)(out + i + 200) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 200);
+    *(vint32mf2_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint64m1_t v = *(vint64m1_t*)(in + 300);
+    *(vint64m1_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 400);
+    *(vfloat32mf2_t*)(out + i + 500) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat64m1_t v = *(vfloat64m1_t*)(in + 500);
+    *(vfloat64m1_t*)(out + i + 600) = v;
+  }
+
+  vint32mf2_t v;
+  *(vint32mf2_t*)(out + 7000) = v;
+ 
+  for (int i = 0; i < n; i++) {
+    vint16mf4_t v;
+    *(vint16mf4_t*)(out + i + 700) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 4 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c
new file mode 100644
index 0000000..b4d4240b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c
@@ -0,0 +1,41 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int32_t * restrict in, int32_t * restrict out, int n, int cond)
+{
+  for (int i = 0; i < n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*)in;
+    *(vint8mf8_t*)(out + i + 200) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 200);
+    *(vint32mf2_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint64m1_t v = *(vint64m1_t*)(in + 300);
+    *(vint64m1_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 400);
+    *(vfloat32mf2_t*)(out + i + 500) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat64m1_t v = *(vfloat64m1_t*)(in + 500);
+    *(vfloat64m1_t*)(out + i + 600) = v;
+  }
+
+  vint32mf2_t v;
+  *(vint32mf2_t*)(out + 7000) = v;
+ 
+  for (int i = 0; i < n; i++) {
+    vbool64_t v;
+    *(vbool64_t*)(out + i + 700) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c
new file mode 100644
index 0000000..4295ac3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c
@@ -0,0 +1,96 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 0) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 100);
+    *(vint8mf8_t*)(out + 100) = v;
+    for (int i = 0; i < n; i++)
+      {
+        vint16mf4_t v2;
+        *(vint16mf4_t*)(out + i + 100) = v2;
+      }
+  } else if (cond == 1) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 200);
+    *(vint8mf8_t*)(out + 200) = v;
+    for (int i = 0; i < n; i++)
+      {
+        vint32mf2_t v2;
+        *(vint32mf2_t*)(out + i + 200) = v2;
+      }
+  } else if (cond == 2) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 300);
+    *(vint8mf8_t*)(out + 300) = v;
+    for (int i = 0; i < n; i++)
+      {
+        vint8mf8_t v2;
+        *(vint8mf8_t*)(out + i + 300) = v2;
+      }
+  } else if (cond == 3) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 400);
+    *(vint8mf8_t*)(out + 400) = v;
+    for (int i = 0; i < n; i++)
+      {
+        vint64m1_t v2;
+        *(vint64m1_t*)(out + i + 400) = v2;
+      }
+  } else if (cond == 4) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 500);
+    *(vint8mf8_t*)(out + 500) = v;
+    for (int i = 0; i < n; i++)
+      {
+        vfloat32mf2_t v2;
+        *(vfloat32mf2_t*)(out + i + 500) = v2;
+      }
+  } else if (cond == 5) {
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 600);
+    *(vuint8mf8_t*)(out + 600) = v;
+    for (int i = 0; i < n; i++)
+      {
+        vuint16mf4_t v2;
+        *(vuint16mf4_t*)(out + i + 600) = v2;
+      }
+  } else if (cond == 6) {
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 700);
+    *(vuint8mf8_t*)(out + 700) = v;
+    for (int i = 0; i < n; i++)
+      {
+        vuint32mf2_t v2;
+        *(vuint32mf2_t*)(out + i + 700) = v2;
+      }
+  } else if (cond == 7) {
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 800);
+    *(vuint8mf8_t*)(out + 800) = v;
+    for (int i = 0; i < n; i++)
+      {
+        vuint8mf8_t v2;
+        *(vuint8mf8_t*)(out + i + 800) = v2;
+      }
+  } else if (cond == 8) {
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 900);
+    *(vuint8mf8_t*)(out + 900) = v;
+    for (int i = 0; i < n; i++)
+      {
+        vuint64m1_t v2;
+        *(vuint64m1_t*)(out + i + 900) = v2;
+      }
+  } else {
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 1000);
+    *(vuint8mf8_t*)(out + 1000) = v;
+    for (int i = 0; i < n; i++)
+      {
+        vfloat32mf2_t v2;
+        *(vfloat32mf2_t*)(out + i + 1000) = v2;
+      }
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 10 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 20 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c
new file mode 100644
index 0000000..59e069f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c
@@ -0,0 +1,89 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 0) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 100);
+    *(vint8mf8_t*)(out + 100) = v;
+    for (int i = 0; i < n; i++)
+      {
+        vint16mf4_t v2;
+        *(vint16mf4_t*)(out + i + 100) = v2;
+      }
+  } else if (cond == 1) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 200);
+    *(vint8mf8_t*)(out + 200) = v;
+    for (int i = 0; i < n; i++)
+      {
+        vint32mf2_t v2;
+        *(vint32mf2_t*)(out + i + 200) = v2;
+      }
+  } else if (cond == 2) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 300);
+    *(vint8mf8_t*)(out + 300) = v;
+    for (int i = 0; i < n; i++)
+      {
+        vint8mf8_t v2;
+        *(vint8mf8_t*)(out + i + 300) = v2;
+      }
+  } else if (cond == 3) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 400);
+    *(vint8mf8_t*)(out + 400) = v;
+    for (int i = 0; i < n; i++)
+      {
+        vint64m1_t v2;
+        *(vint64m1_t*)(out + i + 400) = v2;
+      }
+  } else if (cond == 4) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 500);
+    *(vint8mf8_t*)(out + 500) = v;
+    for (int i = 0; i < n; i++)
+      {
+        vfloat32mf2_t v2;
+        *(vfloat32mf2_t*)(out + i + 500) = v2;
+      }
+  } else if (cond == 5) {
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 600);
+    *(vuint8mf8_t*)(out + 600) = v;
+    for (int i = 0; i < n; i++)
+      {
+        vuint16mf4_t v2;
+        *(vuint16mf4_t*)(out + i + 600) = v2;
+      }
+  } else if (cond == 6) {
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 700);
+    *(vuint8mf8_t*)(out + 700) = v;
+    for (int i = 0; i < n; i++)
+      {
+        vuint32mf2_t v2;
+        *(vuint32mf2_t*)(out + i + 700) = v2;
+      }
+  } else if (cond == 7) {
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 800);
+    *(vuint8mf8_t*)(out + 800) = v;
+    for (int i = 0; i < n; i++)
+      {
+        vuint8mf8_t v2;
+        *(vuint8mf8_t*)(out + i + 800) = v2;
+      }
+  } else if (cond == 8) {
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 900);
+    *(vuint8mf8_t*)(out + 900) = v;
+    for (int i = 0; i < n; i++)
+      {
+        vuint64m1_t v2;
+        *(vuint64m1_t*)(out + i + 900) = v2;
+      }
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 8 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 17 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c
new file mode 100644
index 0000000..e148a1c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c
@@ -0,0 +1,51 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, void * restrict in2, void * restrict out2,  int n, int cond)
+{
+  if (cond == 0) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 100);
+    *(vint8mf8_t*)(out + 100) = v;
+    for (int i = 0; i < n; i++)
+      {
+        vint16mf4_t v2;
+        *(vint16mf4_t*)(out + i + 100) = v2;
+      }
+  } else {
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 1000);
+    *(vuint8mf8_t*)(out + 1000) = v;
+    for (int i = 0; i < n; i++)
+      {
+        vfloat32mf2_t v2;
+        *(vfloat32mf2_t*)(out + i + 1000) = v2;
+        vbool64_t v3;
+        *(vbool64_t*)(out + i + 2000) = v3;
+        vbool32_t v4;
+        *(vbool32_t*)(out + i + 3000) = v4;
+        vbool16_t v5;
+        *(vbool16_t*)(out + i + 4000) = v5;
+        vbool8_t v6;
+        *(vbool8_t*)(out + i + 5000) = v6;
+        vbool4_t v7;
+        *(vbool4_t*)(out + i + 6000) = v7;
+        vbool2_t v8;
+        *(vbool2_t*)(out + i + 7000) = v8;
+        vbool1_t v9;
+        *(vbool1_t*)(out + i + 8000) = v9;
+      }
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 9 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c
new file mode 100644
index 0000000..e8340a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c
@@ -0,0 +1,54 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, void * restrict in2, void * restrict out2,  int n, int cond)
+{
+  if (cond == 0) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 100);
+    *(vint8mf8_t*)(out + 100) = v;
+    for (int i = 0; i < n; i++)
+      {
+        vint16mf4_t v2;
+        *(vint16mf4_t*)(out + i + 100) = v2;
+      }
+  } else {
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 1000);
+    *(vuint8mf8_t*)(out + 1000) = v;
+    for (int i = 0; i < n; i++)
+      {
+        vfloat32mf2_t v2;
+        *(vfloat32mf2_t*)(out + i + 1000) = v2;
+        vbool64_t v3;
+        *(vbool64_t*)(out + i + 2000) = v3;
+        vbool32_t v4;
+        *(vbool32_t*)(out + i + 3000) = v4;
+        vbool16_t v5;
+        *(vbool16_t*)(out + i + 4000) = v5;
+        vbool8_t v6;
+        *(vbool8_t*)(out + i + 5000) = v6;
+        vbool4_t v7;
+        *(vbool4_t*)(out + i + 6000) = v7;
+        vbool2_t v8;
+        *(vbool2_t*)(out + i + 7000) = v8;
+        vbool1_t v9;
+        *(vbool1_t*)(out + i + 8000) = v9;
+        vuint32mf2_t v10;
+        *(vuint32mf2_t*)(out + i + 100000) = v10;
+      }
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 10 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c
new file mode 100644
index 0000000..74584e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c
@@ -0,0 +1,54 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, void * restrict in2, void * restrict out2,  int n, int cond)
+{
+  if (cond == 0) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 100);
+    *(vint8mf8_t*)(out + 100) = v;
+    for (int i = 0; i < n; i++)
+      {
+        vint16mf4_t v2;
+        *(vint16mf4_t*)(out + i + 100) = v2;
+      }
+  } else {
+    vuint8mf8_t v;
+    *(vuint8mf8_t*)(out + 1000) = v;
+    for (int i = 0; i < n; i++)
+      {
+        vfloat32mf2_t v2;
+        *(vfloat32mf2_t*)(out + i + 1000) = v2;
+        vbool64_t v3;
+        *(vbool64_t*)(out + i + 2000) = v3;
+        vbool32_t v4;
+        *(vbool32_t*)(out + i + 3000) = v4;
+        vbool16_t v5;
+        *(vbool16_t*)(out + i + 4000) = v5;
+        vbool8_t v6;
+        *(vbool8_t*)(out + i + 5000) = v6;
+        vbool4_t v7;
+        *(vbool4_t*)(out + i + 6000) = v7;
+        vbool2_t v8;
+        *(vbool2_t*)(out + i + 7000) = v8;
+        vbool1_t v9;
+        *(vbool1_t*)(out + i + 8000) = v9;
+        vuint32mf2_t v10;
+        *(vuint32mf2_t*)(out + i + 100000) = v10;
+      }
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 11 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c
new file mode 100644
index 0000000..63f6c72
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c
@@ -0,0 +1,47 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int32_t * restrict in, int32_t * restrict out, int n, int cond)
+{
+  for (int i = 0; i < n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*)in;
+    *(vint8mf8_t*)(out + i + 200) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 200);
+    *(vint32mf2_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint64m1_t v = *(vint64m1_t*)(in + 300);
+    *(vint64m1_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 400);
+    *(vfloat32mf2_t*)(out + i + 500) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat64m1_t v = *(vfloat64m1_t*)(in + 500);
+    *(vfloat64m1_t*)(out + i + 600) = v;
+  }
+
+  if (cond == 0) {
+    for (int i = 0; i < n; i++) {
+      out[i] = out[i] + 2;
+    }
+  } else {
+    for (int i = 0; i < n; i++) {
+      out[i] = out[i] + 3;
+    }
+  }
+ 
+  for (int i = 0; i < n; i++) {
+    vint16mf4_t v;
+    *(vint16mf4_t*)(out + i + 700) = v;
+  }
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c
new file mode 100644
index 0000000..92bf3ab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c
@@ -0,0 +1,44 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, void * restrict in2, void * restrict out2,  int n, int cond)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vfloat32mf2_t v2 = *(vfloat32mf2_t*)(in + i + 1000);
+      *(vfloat32mf2_t*)(out + i + 1000) = v2;
+      vbool32_t v4;
+      *(vbool32_t*)(out + i + 3000) = v4;
+      vbool16_t v5;
+      *(vbool16_t*)(out + i + 4000) = v5;
+      vbool8_t v6;
+      *(vbool8_t*)(out + i + 5000) = v6;
+      vbool4_t v7;
+      *(vbool4_t*)(out + i + 6000) = v7;
+      vbool2_t v8;
+      *(vbool2_t*)(out + i + 7000) = v8;
+      vbool1_t v9;
+      *(vbool1_t*)(out + i + 8000) = v9;
+      vuint32mf2_t v10 = *(vuint32mf2_t*)(in + i + 100000);
+      *(vuint32mf2_t*)(out + i + 100000) = v10;
+    }
+  
+  for (int i = 0; i < n; i++) 
+    {
+      vint8mf8_t v1;
+      *(vint8mf8_t*)(out + i + 10) = v1;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli} 9 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c
new file mode 100644
index 0000000..4d25457
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c
@@ -0,0 +1,46 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, void * restrict in2, void * restrict out2,  int n, int cond)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vuint16mf4_t v2 = *(vuint16mf4_t*)(in + i + 1000);
+      *(vuint16mf4_t*)(out + i + 1000) = v2;
+      vbool32_t v4;
+      *(vbool32_t*)(out + i + 3000) = v4;
+      vbool16_t v5;
+      *(vbool16_t*)(out + i + 4000) = v5;
+      vbool8_t v6;
+      *(vbool8_t*)(out + i + 5000) = v6;
+      vbool4_t v7;
+      *(vbool4_t*)(out + i + 6000) = v7;
+      vbool2_t v8;
+      *(vbool2_t*)(out + i + 7000) = v8;
+      vbool1_t v9;
+      *(vbool1_t*)(out + i + 8000) = v9;
+      vuint32mf2_t v10 = *(vuint32mf2_t*)(in + i + 100000);
+      *(vuint32mf2_t*)(out + i + 100000) = v10;
+    }
+  
+  for (int i = 0; i < n; i++) 
+    {
+      vint8mf8_t v1;
+      *(vint8mf8_t*)(out + i + 10) = v1;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli} 9 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c
new file mode 100644
index 0000000..284df72
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c
@@ -0,0 +1,46 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, void * restrict in2, void * restrict out2,  int n, int cond)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vuint16mf4_t v2 = *(vuint16mf4_t*)(in + i + 1000);
+      *(vuint16mf4_t*)(out + i + 1000) = v2;
+      vbool32_t v4;
+      *(vbool32_t*)(out + i + 3000) = v4;
+      vbool16_t v5;
+      *(vbool16_t*)(out + i + 4000) = v5;
+      vbool8_t v6;
+      *(vbool8_t*)(out + i + 5000) = v6;
+      vbool4_t v7;
+      *(vbool4_t*)(out + i + 6000) = v7;
+      vbool2_t v8;
+      *(vbool2_t*)(out + i + 7000) = v8;
+      vbool1_t v9;
+      *(vbool1_t*)(out + i + 8000) = v9;
+      vuint32mf2_t v10;
+      *(vuint32mf2_t*)(out + i + 100000) = v10;
+    }
+  
+  for (int i = 0; i < n; i++) 
+    {
+      vint8mf8_t v1 = *(vint8mf8_t*)(in + i + 100000);
+      *(vint8mf8_t*)(out + i + 10) = v1;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]:+} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli} 8 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c
new file mode 100644
index 0000000..1057b1b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c
@@ -0,0 +1,45 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, void * restrict in2, void * restrict out2,  int n, int cond)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vuint16mf4_t v2;
+      *(vuint16mf4_t*)(out + i + 1000) = v2;
+      vbool32_t v4;
+      *(vbool32_t*)(out + i + 3000) = v4;
+      vbool16_t v5;
+      *(vbool16_t*)(out + i + 4000) = v5;
+      vbool8_t v6;
+      *(vbool8_t*)(out + i + 5000) = v6;
+      vbool4_t v7;
+      *(vbool4_t*)(out + i + 6000) = v7;
+      vbool2_t v8;
+      *(vbool2_t*)(out + i + 7000) = v8;
+      vbool1_t v9;
+      *(vbool1_t*)(out + i + 8000) = v9;
+      vuint32mf2_t v10;
+      *(vuint32mf2_t*)(out + i + 100000) = v10;
+    }
+  
+  for (int i = 0; i < n; i++) 
+    {
+      vint8mf8_t v1 = *(vint8mf8_t*)(in + i + 100000);
+      *(vint8mf8_t*)(out + i + 10) = v1;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli} 8 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.c
new file mode 100644
index 0000000..9746ebe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.c
@@ -0,0 +1,45 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int32_t * restrict in, int32_t * restrict out, int32_t * restrict in2, int32_t * restrict out2,  int n, int cond)
+{
+  if (cond == 0)
+    {
+      for (int i = 0; i < n; i++)
+        {
+          out2[i] = out[i] + in[i];
+        }
+    }
+  else if (cond == 1)
+   {
+      for (int i = 0; i < n; i++)
+          {
+            out2[i] = out[i] + in[i];
+          }
+      for (int i = 0; i < n; i++)
+          {
+            out[i] = out2[i] / in[i];
+          }
+      for (int i = 0; i < n; i++)
+        {
+          out2[i] = out[i] * in[i];
+        }
+   }
+  else
+   {
+     for (int i = 0; i < n; i++)
+      {
+        out[i] = in[i] + 4;
+      }
+   }
+  for (int i = 0; i < n; i++) 
+    {
+      vint8mf8_t v1;
+      *(vint8mf8_t*)(out + i + 10) = v1;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c
new file mode 100644
index 0000000..0547d62
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int32_t * restrict in, int32_t * restrict out, int32_t * restrict in2, int32_t * restrict out2,  int n, int cond)
+{
+  if (cond == 0)
+    {
+      for (int i = 0; i < n; i++)
+        {
+          out2[i] = out[i] + in[i];
+        }
+    }
+  else if (cond == 1)
+   {
+      for (int i = 0; i < n; i++)
+          {
+            out2[i] = out[i] + in[i];
+          }
+      for (int i = 0; i < n; i++)
+          {
+            out[i] = out2[i] / in[i];
+          }
+      for (int i = 0; i < n; i++)
+        {
+          out2[i] = out[i] * in[i];
+        }
+   }
+  for (int i = 0; i < n; i++) 
+    {
+      vint8mf8_t v1;
+      *(vint8mf8_t*)(out + i + 10) = v1;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c
new file mode 100644
index 0000000..a82b86f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c
@@ -0,0 +1,47 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int32_t * restrict in, int32_t * restrict out, int32_t * restrict in2, int32_t * restrict out2,  int n, int cond)
+{
+  if (cond == 0)
+    {
+      for (int i = 0; i < n; i++)
+        {
+          out2[i] = out[i] + in[i];
+        }
+    }
+  else if (cond == 1)
+   {
+      for (int i = 0; i < n; i++)
+          {
+            out2[i] = out[i] + in[i];
+          }
+      for (int i = 0; i < n; i++)
+          {
+            out[i] = out2[i] / in[i];
+          }
+      for (int i = 0; i < n; i++)
+        {
+          out2[i] = out[i] * in[i];
+        }
+   }
+  else
+   {
+     for (int i = 0; i < n; i++) 
+      {
+        vint32mf2_t v1 = *(vint32mf2_t*)in2;
+        *(vint32mf2_t*)(out + i + 10) = v1;
+      }
+   }
+  for (int i = 0; i < n; i++) 
+    {
+      vint8mf8_t v1;
+      *(vint8mf8_t*)(out + i + 10) = v1;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]+:} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c
new file mode 100644
index 0000000..981e90e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c
@@ -0,0 +1,41 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void fn3 (void);
+
+void f (int32_t * restrict in, int32_t * restrict out, int32_t * restrict in2, int32_t * restrict out2,  int n, int cond)
+{
+  if (cond == 0)
+    {
+      for (int i = 0; i < n; i++) 
+      {
+        vfloat32mf2_t v1 = *(vfloat32mf2_t*)(in + 1000);
+        *(vfloat32mf2_t*)(out + i + 1000) = v1;
+      }
+      for (int i = 0; i < n; i++) 
+      {
+        vint32mf2_t v1 = *(vint32mf2_t*)in;
+        *(vint32mf2_t*)(out + i + 10) = v1;
+      }
+    for (int i = 0; i < n; i++) 
+      {
+        vint16mf4_t v1 = *(vint16mf4_t*)(in + 100);
+        *(vint16mf4_t*)(out + i + 100) = v1;
+      }
+    }
+  else
+   {
+     fn3 ();
+   }
+  for (int i = 0; i < n; i++) 
+    {
+      vint8mf8_t v1;
+      *(vint8mf8_t*)(out + i + 10) = v1;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.c
new file mode 100644
index 0000000..79dbeefb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.c
@@ -0,0 +1,73 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int32_t * restrict in, int32_t * restrict out, int32_t * restrict in2, int32_t * restrict out2,  int n, int cond, int cond2)
+{
+  if (cond == 0)
+    {
+      if (cond2) {
+      for (int i = 0; i < n; i++) 
+      {
+        vfloat32mf2_t v1 = *(vfloat32mf2_t*)(in + 1000);
+        *(vfloat32mf2_t*)(out + i + 1000) = v1;
+      }
+      for (int i = 0; i < n; i++) 
+      {
+        vint32mf2_t v1 = *(vint32mf2_t*)in;
+        *(vint32mf2_t*)(out + i + 10) = v1;
+      }
+    for (int i = 0; i < n; i++) 
+      {
+        vint16mf4_t v1 = *(vint16mf4_t*)(in + 100);
+        *(vint16mf4_t*)(out + i + 100) = v1;
+      }
+      } else {
+        for (int i = 0; i < n; i++) 
+      {
+        vfloat32mf2_t v1 = *(vfloat32mf2_t*)(in + 2000);
+        *(vfloat32mf2_t*)(out + i + 2000) = v1;
+      }
+      for (int i = 0; i < n; i++) 
+      {
+        vint32mf2_t v1 = *(vint32mf2_t*)(in + 200);
+        *(vint32mf2_t*)(out + i + 200) = v1;
+      }
+    for (int i = 0; i < n; i++) 
+      {
+        vint16mf4_t v1 = *(vint16mf4_t*)(in + 300);
+        *(vint16mf4_t*)(out + i + 300) = v1;
+      }
+      }
+    }
+  else
+   {
+     for (int i = 0; i < n; i++) 
+      {
+        vint16mf4_t v1 = *(vint16mf4_t*)(in + 30000);
+        *(vint16mf4_t*)(out + i + 30000) = v1;
+      }
+    for (int i = 0; i < n; i++) 
+      {
+        vint32mf2_t v1 = *(vint32mf2_t*)(in + 40000);
+        *(vint32mf2_t*)(out + i + 40000) = v1;
+      }
+    for (int i = 0; i < n; i++) 
+      {
+        vuint32mf2_t v1 = *(vuint32mf2_t*)(in + 50000);
+        *(vuint32mf2_t*)(out + i + 50000) = v1;
+      }
+   }
+  for (int i = 0; i < n; i++) 
+    {
+      vint8mf8_t v1;
+      *(vint8mf8_t*)(out + i + 10) = v1;
+    }
+}
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 4 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.c
new file mode 100644
index 0000000..c3eb6f9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void foo5_3 (int32_t * restrict in, int32_t * restrict out, size_t n, int cond)
+{
+  vint8mf2_t v;
+  for (size_t i = 0; i < n; i++)
+    {
+      if (i % 2 == 0) {
+        v = *(vint8mf2_t*)(in + i);
+      } else {
+        *(vint8mf2_t*)(out + i) = v;
+      }
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+j\s+\.L[0-9]+} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c
new file mode 100644
index 0000000..0ba6004
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c
@@ -0,0 +1,104 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int32_t * restrict in, int32_t * restrict out, int n, int cond)
+{
+  for (int i = 0; i < n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*)in;
+    *(vint8mf8_t*)(out + i + 200) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 200);
+    *(vint32mf2_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint64m1_t v = *(vint64m1_t*)(in + 300);
+    *(vint64m1_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 400);
+    *(vfloat32mf2_t*)(out + i + 500) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat64m1_t v = *(vfloat64m1_t*)(in + 500);
+    *(vfloat64m1_t*)(out + i + 600) = v;
+  }
+
+  if (cond == 0) {
+    for (int i = 0; i < n; i++) {
+      out[i] = out[i] + 2;
+    }
+  } else if (cond == 1){
+    for (int i = 0; i < n; i++) {
+      out[i] = out[i] + 3;
+    }
+  } else if (cond == 2) {
+    for (int i = 0; i < n; i++) {
+      out[i] = out[i] + 5;
+    }
+    for (int i = 0; i < n; i++) {
+      out[i] = out[i] + 6;
+    }
+  } else if (cond == 4) {
+    for (int i = 0; i < n; i++) {
+      out[i] = out[i] + 8;
+    }
+    for (int i = 0; i < n; i++) {
+      out[i] = out[i] + 9;
+    }
+  } else if (cond == 5) {
+    for (int i = 0; i < n; i++) {
+      out[i] = out[i] + 10;
+    }
+    for (int i = 0; i < n; i++) {
+      out[i] = out[i] + 11;
+    }
+  } else if (cond == 6) {
+    for (int i = 0; i < n; i++) {
+      out[i] = out[i] + 12;
+    }
+    for (int i = 0; i < n; i++) {
+      out[i] = out[i] + 13;
+    }
+    for (int i = 0; i < n; i++) {
+      out[i] = out[i] * out[i];
+    }
+  } else if (cond == 7) {
+    for (int i = 0; i < n; i++) {
+      out[i] = out[i] + 15;
+    }
+    for (int i = 0; i < n; i++) {
+      out[i] = out[i] + 16;
+    }
+    for (int i = 0; i < n; i++) {
+      out[i] = out[i] + out[i];
+    }
+  } else if (cond == 8) {
+    for (int i = 0; i < n; i++) {
+      out[i] = out[i] + 101;
+    }
+  } else if (cond == 9) {
+    for (int i = 0; i < n; i++) {
+      out[i] = out[i] * 101;
+    }
+  } else if (cond == 10) {
+    for (int i = 0; i < n; i++) {
+      out[i] = out[i] >> 3;
+    }
+  } else {
+    for (int i = 0; i < n; i++) {
+      out[i] = out[i] << 1;
+    }
+  }
+ 
+  for (int i = 0; i < n; i++) {
+    vint16mf4_t v;
+    *(vint16mf4_t*)(out + i + 700) = v;
+  }
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c
new file mode 100644
index 0000000..67f1a33
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void foo5_4 (int32_t * restrict in, int32_t * restrict out, size_t n, size_t m, int cond)
+{
+  vint8mf2_t v;
+  for (size_t i = 0; i < n; i++)
+    {
+      for (size_t j = 0; j < m; j += 1) {
+        if (j % 2 == 0) {
+          v = *(vint8mf2_t*)(in + i + j);
+        } else {
+          *(vint8mf2_t*)(out + i + j) = v;
+        }
+      }
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]+} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c
new file mode 100644
index 0000000..b2f4fee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void foo5_5 (int32_t * restrict in, int32_t * restrict out, size_t n, size_t m, int cond)
+{
+  vint8mf2_t v;
+  for (size_t i = 0; i < n; i++)
+    {
+      if (i % 2) {
+        for (size_t j = 0; j < m; j += 1) {
+          if (j % 2 == 0) {
+            v = *(vint8mf2_t*)(in + i + j);
+          } else {
+            *(vint8mf2_t*)(out + i + j) = v;
+          }
+        }
+      } else {
+        *(vint8mf2_t*)(out + i) = v;
+      }
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.c
new file mode 100644
index 0000000..4eb57de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void foo5_6 (int32_t * restrict in, int32_t * restrict out, size_t n, size_t m, int cond)
+{
+  vint8mf2_t v;
+  for (size_t i = 0; i < n; i++)
+    {
+      if (i % 2) {
+        for (size_t j = 0; j < m; j += 1) {
+          if (j % 2 == 0) {
+            v = *(vint8mf2_t*)(in + i + j);
+          } else {
+            *(vint8mf2_t*)(out + i + j) = v;
+          }
+        }
+      } else {
+      }
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.c
new file mode 100644
index 0000000..047369e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void foo5_3 (int32_t * restrict in, int32_t * restrict out, size_t n, int cond)
+{
+  for (size_t i = 0; i < n; i++)
+    {
+      if (i % 16 == 0) {
+        vint8mf8_t v = *(vint8mf8_t*)(in + i + 100);
+        *(vint8mf8_t*)(out + i + 100) = v;
+      } else if (i % 8 == 0) {
+        vint16mf4_t v = *(vint16mf4_t*)(in + i + 200);
+        *(vint16mf4_t*)(out + i + 200) = v;
+      } else if (i % 4 == 0) {
+        vint32mf2_t v = *(vint32mf2_t*)(in + i + 300);
+        *(vint32mf2_t*)(out + i + 300) = v;
+      } else {
+        vbool64_t v = *(vbool64_t*)(in + i + 400);
+        *(vbool64_t*)(out + i + 400) = v;
+      }
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.c
new file mode 100644
index 0000000..05e9810
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void foo5_4 (int32_t * restrict in, int32_t * restrict out, size_t n, size_t m, int cond)
+{
+  for (size_t i = 0; i < n; i++)
+    {
+      for (size_t j = 0; j < m; j += 1) {
+        if (i % 16 == 0) {
+          vint8mf8_t v = *(vint8mf8_t*)(in + i + 100 + j);
+          *(vint8mf8_t*)(out + i + 100 + j) = v;
+        } else if (i % 8 == 0) {
+          vint16mf4_t v = *(vint16mf4_t*)(in + i + 200 + j);
+          *(vint16mf4_t*)(out + i + 200 + j) = v;
+        } else if (i % 4 == 0) {
+          vint32mf2_t v = *(vint32mf2_t*)(in + i + 300 + j);
+          *(vint32mf2_t*)(out + i + 300 + j) = v;
+        } else {
+          vbool64_t v = *(vbool64_t*)(in + i + 400 + j);
+          *(vbool64_t*)(out + i + 400 + j) = v;
+        }
+      }
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c
new file mode 100644
index 0000000..0f6b96e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void foo5_5 (int32_t * restrict in, int32_t * restrict out, size_t n, size_t m, int cond)
+{
+  for (size_t i = 0; i < n; i++)
+    {
+      if (i % 2) {
+        for (size_t j = 0; j < m; j += 1) {
+          if (i % 16 == 0) {
+          vint8mf8_t v = *(vint8mf8_t*)(in + i + 100 + j);
+          *(vint8mf8_t*)(out + i + 100 + j) = v;
+        } else if (i % 8 == 0) {
+          vint16mf4_t v = *(vint16mf4_t*)(in + i + 200 + j);
+          *(vint16mf4_t*)(out + i + 200 + j) = v;
+        } else if (i % 4 == 0) {
+          vint32mf2_t v = *(vint32mf2_t*)(in + i + 300 + j);
+          *(vint32mf2_t*)(out + i + 300 + j) = v;
+        } else {
+          vbool64_t v = *(vbool64_t*)(in + i + 400 + j);
+          *(vbool64_t*)(out + i + 400 + j) = v;
+        }
+        }
+      } else {
+        vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 88888);
+        *(vfloat32mf2_t*)(out + 88888) = v;
+      }
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+j\s+\.L[0-9]+} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.c
new file mode 100644
index 0000000..a211bed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void foo5_6 (int32_t * restrict in, int32_t * restrict out, size_t n, size_t m, int cond)
+{
+  for (size_t i = 0; i < n; i++)
+    {
+      if (i % 2) {
+        for (size_t j = 0; j < m; j += 1) {
+          if (i % 16 == 0) {
+          vint8mf8_t v = *(vint8mf8_t*)(in + i + 100 + j);
+          *(vint8mf8_t*)(out + i + 100 + j) = v;
+        } else if (i % 8 == 0) {
+          vint16mf4_t v = *(vint16mf4_t*)(in + i + 200 + j);
+          *(vint16mf4_t*)(out + i + 200 + j) = v;
+        } else if (i % 4 == 0) {
+          vint32mf2_t v = *(vint32mf2_t*)(in + i + 300 + j);
+          *(vint32mf2_t*)(out + i + 300 + j) = v;
+        } else {
+          vbool64_t v = *(vbool64_t*)(in + i + 400 + j);
+          *(vbool64_t*)(out + i + 400 + j) = v;
+        }
+        }
+      } else {
+      }
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.c
new file mode 100644
index 0000000..b38e362
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.c
@@ -0,0 +1,48 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f (int32_t * restrict in, int32_t * restrict out, int n, int cond)
+{
+  for (int i = 0; i < n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*)in;
+    *(vint8mf8_t*)(out + i + 200) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 200);
+    *(vint32mf2_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint64m1_t v = *(vint64m1_t*)(in + 300);
+    *(vint64m1_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 400);
+    *(vfloat32mf2_t*)(out + i + 500) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat64m1_t v = *(vfloat64m1_t*)(in + 500);
+    *(vfloat64m1_t*)(out + i + 600) = v;
+  }
+  
+  switch (cond)
+  {
+  case 0:
+    for (int i = 0; i < n; i++) {
+      out[i] = out[i] + 2;
+    }
+    break;
+  
+  default:
+    for (int i = 0; i < n; i++) {
+      out[i] = out[i] + 3;
+    }
+    break;
+  }
+ 
+  for (int i = 0; i < n; i++) {
+    vint16mf4_t v;
+    *(vint16mf4_t*)(out + i + 700) = v;
+  }
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.c
new file mode 100644
index 0000000..2edc181
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.c
@@ -0,0 +1,155 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int32_t * restrict in, int32_t * restrict out, int n, int cond)
+{
+  for (int i = 0; i < n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*)in;
+    *(vint8mf8_t*)(out + i + 200) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 200);
+    *(vint32mf2_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint64m1_t v = *(vint64m1_t*)(in + 300);
+    *(vint64m1_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 400);
+    *(vfloat32mf2_t*)(out + i + 500) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat64m1_t v = *(vfloat64m1_t*)(in + 500);
+    *(vfloat64m1_t*)(out + i + 600) = v;
+  }
+
+  switch (cond)
+  {
+  case 0:
+  {
+      for (int i = 0; i < n; i++)
+      {
+          out[i] = out[i] + 2;
+      }
+  }
+  break;
+  case 1:
+  {
+      for (int i = 0; i < n; i++)
+      {
+          out[i] = out[i] + 3;
+      }
+  }
+  break;
+  case 2:
+  {
+      for (int i = 0; i < n; i++)
+      {
+          out[i] = out[i] + 5;
+      }
+      for (int i = 0; i < n; i++)
+      {
+          out[i] = out[i] + 6;
+      }
+  }
+  break;
+  case 4:
+  {
+      for (int i = 0; i < n; i++)
+      {
+          out[i] = out[i] + 8;
+      }
+      for (int i = 0; i < n; i++)
+      {
+          out[i] = out[i] + 9;
+      }
+  }
+  break;
+  case 5:
+  {
+      for (int i = 0; i < n; i++)
+      {
+          out[i] = out[i] + 10;
+      }
+      for (int i = 0; i < n; i++)
+      {
+          out[i] = out[i] + 11;
+      }
+  }
+  break;
+  case 6:
+  {
+      for (int i = 0; i < n; i++)
+      {
+          out[i] = out[i] + 12;
+      }
+      for (int i = 0; i < n; i++)
+      {
+          out[i] = out[i] + 13;
+      }
+      for (int i = 0; i < n; i++)
+      {
+          out[i] = out[i] * out[i];
+      }
+  }
+  break;
+  case 7:
+  {
+      for (int i = 0; i < n; i++)
+      {
+          out[i] = out[i] + 15;
+      }
+      for (int i = 0; i < n; i++)
+      {
+          out[i] = out[i] + 16;
+      }
+      for (int i = 0; i < n; i++)
+      {
+          out[i] = out[i] + out[i];
+      }
+  }
+  break;
+  case 8:
+  {
+      for (int i = 0; i < n; i++)
+      {
+          out[i] = out[i] + 101;
+      }
+  }
+  break;
+  case 9:
+  {
+      for (int i = 0; i < n; i++)
+      {
+          out[i] = out[i] * 101;
+      }
+  }
+  break;
+  case 10:
+  {
+      for (int i = 0; i < n; i++)
+      {
+          out[i] = out[i] >> 3;
+      }
+  }
+  break;
+  default:
+  {
+      for (int i = 0; i < n; i++)
+      {
+          out[i] = out[i] << 1;
+      }
+  }
+  break;
+  }
+  for (int i = 0; i < n; i++) {
+    vint16mf4_t v;
+    *(vint16mf4_t*)(out + i + 700) = v;
+  }
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c
new file mode 100644
index 0000000..68d595f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c
@@ -0,0 +1,43 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int32_t * restrict in, int32_t * restrict out, int n, int cond)
+{
+  for (int i = 0; i < n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*)in;
+    *(vint8mf8_t*)(out + i + 200) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 200);
+    *(vint32mf2_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint64m1_t v = *(vint64m1_t*)(in + 300);
+    *(vint64m1_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 400);
+    *(vfloat32mf2_t*)(out + i + 500) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat64m1_t v = *(vfloat64m1_t*)(in + 500);
+    *(vfloat64m1_t*)(out + i + 600) = v;
+  }
+
+  if (cond == 0) {
+    for (int i = 0; i < n; i++) {
+      out[i] = out[i] + 2;
+    }
+  }
+ 
+  for (int i = 0; i < n; i++) {
+    vint16mf4_t v;
+    *(vint16mf4_t*)(out + i + 700) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c
new file mode 100644
index 0000000..f49eebd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c
@@ -0,0 +1,149 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int32_t * restrict in, int32_t * restrict out, int n, int cond)
+{
+  for (int i = 0; i < n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*)in;
+    *(vint8mf8_t*)(out + i + 200) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 200);
+    *(vint32mf2_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint64m1_t v = *(vint64m1_t*)(in + 300);
+    *(vint64m1_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 400);
+    *(vfloat32mf2_t*)(out + i + 500) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat64m1_t v = *(vfloat64m1_t*)(in + 500);
+    *(vfloat64m1_t*)(out + i + 600) = v;
+  }
+
+  switch (cond)
+  {
+  case 0:
+  {
+      for (int i = 0; i < n; i++)
+      {
+          out[i] = out[i] + 2;
+      }
+  }
+  break;
+  case 1:
+  {
+      for (int i = 0; i < n; i++)
+      {
+          out[i] = out[i] + 3;
+      }
+  }
+  break;
+  case 2:
+  {
+      for (int i = 0; i < n; i++)
+      {
+          out[i] = out[i] + 5;
+      }
+      for (int i = 0; i < n; i++)
+      {
+          out[i] = out[i] + 6;
+      }
+  }
+  break;
+  case 4:
+  {
+      for (int i = 0; i < n; i++)
+      {
+          out[i] = out[i] + 8;
+      }
+      for (int i = 0; i < n; i++)
+      {
+          out[i] = out[i] + 9;
+      }
+  }
+  break;
+  case 5:
+  {
+      for (int i = 0; i < n; i++)
+      {
+          out[i] = out[i] + 10;
+      }
+      for (int i = 0; i < n; i++)
+      {
+          out[i] = out[i] + 11;
+      }
+  }
+  break;
+  case 6:
+  {
+      for (int i = 0; i < n; i++)
+      {
+          out[i] = out[i] + 12;
+      }
+      for (int i = 0; i < n; i++)
+      {
+          out[i] = out[i] + 13;
+      }
+      for (int i = 0; i < n; i++)
+      {
+          out[i] = out[i] * out[i];
+      }
+  }
+  break;
+  case 7:
+  {
+      for (int i = 0; i < n; i++)
+      {
+          out[i] = out[i] + 15;
+      }
+      for (int i = 0; i < n; i++)
+      {
+          out[i] = out[i] + 16;
+      }
+      for (int i = 0; i < n; i++)
+      {
+          out[i] = out[i] + out[i];
+      }
+  }
+  break;
+  case 8:
+  {
+      for (int i = 0; i < n; i++)
+      {
+          out[i] = out[i] + 101;
+      }
+  }
+  break;
+  case 9:
+  {
+      for (int i = 0; i < n; i++)
+      {
+          out[i] = out[i] * 101;
+      }
+  }
+  break;
+  case 10:
+  {
+      for (int i = 0; i < n; i++)
+      {
+          out[i] = out[i] >> 3;
+      }
+  }
+  break;
+  default:
+  break;
+  }
+  for (int i = 0; i < n; i++) {
+    vint16mf4_t v;
+    *(vint16mf4_t*)(out + i + 700) = v;
+  }
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c
new file mode 100644
index 0000000..8483cdc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c
@@ -0,0 +1,44 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int32_t * restrict in, int32_t * restrict out, int n, int cond)
+{
+  for (int i = 0; i < n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*)in;
+    *(vint8mf8_t*)(out + i + 200) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 200);
+    *(vint32mf2_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint64m1_t v = *(vint64m1_t*)(in + 300);
+    *(vint64m1_t*)(out + i + 400) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 400);
+    *(vfloat32mf2_t*)(out + i + 500) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat64m1_t v = *(vfloat64m1_t*)(in + 500);
+    *(vfloat64m1_t*)(out + i + 600) = v;
+  }
+
+  if (cond == 0) {
+    for (int i = 0; i < n; i++) {
+      out[i] = out[i] + 2;
+    }
+  }
+ 
+  for (int i = 0; i < n; i++) {
+    vint16mf4_t v;
+    *(vint16mf4_t*)(out + i + 700) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c
new file mode 100644
index 0000000..4e4e16c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c
@@ -0,0 +1,182 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 500);
+    *(vint8mf8_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 600);
+    *(vint8mf8_t*)(out + 600) = v;
+  } else {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 700);
+    *(vint8mf8_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 900 + i);
+    *(vint8mf8_t*)(out + 900 + i) = v;
+  }
+}
+
+void f2 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vint8mf4_t v = *(vint8mf4_t*)(in + 500);
+    *(vint8mf4_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vint8mf4_t v = *(vint8mf4_t*)(in + 600);
+    *(vint8mf4_t*)(out + 600) = v;
+  } else {
+    vint8mf4_t v = *(vint8mf4_t*)(in + 700);
+    *(vint8mf4_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf4_t v = *(vint8mf4_t*)(in + 900 + i);
+    *(vint8mf4_t*)(out + 900 + i) = v;
+  }
+}
+
+void f3 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vint8mf2_t v = *(vint8mf2_t*)(in + 500);
+    *(vint8mf2_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vint8mf2_t v = *(vint8mf2_t*)(in + 600);
+    *(vint8mf2_t*)(out + 600) = v;
+  } else {
+    vint8mf2_t v = *(vint8mf2_t*)(in + 700);
+    *(vint8mf2_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf2_t v = *(vint8mf2_t*)(in + 900 + i);
+    *(vint8mf2_t*)(out + 900 + i) = v;
+  }
+}
+
+void f4 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vint16mf4_t v = *(vint16mf4_t*)(in + 500);
+    *(vint16mf4_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vint16mf4_t v = *(vint16mf4_t*)(in + 600);
+    *(vint16mf4_t*)(out + 600) = v;
+  } else {
+    vint16mf4_t v = *(vint16mf4_t*)(in + 700);
+    *(vint16mf4_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint16mf4_t v = *(vint16mf4_t*)(in + 900 + i);
+    *(vint16mf4_t*)(out + 900 + i) = v;
+  }
+}
+
+void f5 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vint16mf2_t v = *(vint16mf2_t*)(in + 500);
+    *(vint16mf2_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vint16mf2_t v = *(vint16mf2_t*)(in + 600);
+    *(vint16mf2_t*)(out + 600) = v;
+  } else {
+    vint16mf2_t v = *(vint16mf2_t*)(in + 700);
+    *(vint16mf2_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint16mf2_t v = *(vint16mf2_t*)(in + 900 + i);
+    *(vint16mf2_t*)(out + 900 + i) = v;
+  }
+}
+
+void f6 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 500);
+    *(vint32mf2_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 600);
+    *(vint32mf2_t*)(out + 600) = v;
+  } else {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 700);
+    *(vint32mf2_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 900 + i);
+    *(vint32mf2_t*)(out + 900 + i) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O2" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O2" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O2" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O2" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O2" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O2" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O2" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O2" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O2" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c
new file mode 100644
index 0000000..f78c348
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c
@@ -0,0 +1,230 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vint8mf8_t v = *(vint8mf8_t*)(in + 500);
+    *(vint8mf8_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vint8mf8_t v = *(vint8mf8_t*)(in + 500);
+    *(vint8mf8_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    vint8mf8_t v = *(vint8mf8_t*)(in + 700);
+    *(vint8mf8_t*)(out + 700) = v;
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 900 + i);
+    *(vint8mf8_t*)(out + 900 + i) = v;
+  }
+}
+
+void f2 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vint8mf4_t v = *(vint8mf4_t*)(in + 500);
+    *(vint8mf4_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vint8mf4_t v = *(vint8mf4_t*)(in + 500);
+    *(vint8mf4_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    vint8mf4_t v = *(vint8mf4_t*)(in + 700);
+    *(vint8mf4_t*)(out + 700) = v;
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf4_t v = *(vint8mf4_t*)(in + 900 + i);
+    *(vint8mf4_t*)(out + 900 + i) = v;
+  }
+}
+
+void f3 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vint8mf2_t v = *(vint8mf2_t*)(in + 500);
+    *(vint8mf2_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vint8mf2_t v = *(vint8mf2_t*)(in + 500);
+    *(vint8mf2_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    vint8mf2_t v = *(vint8mf2_t*)(in + 700);
+    *(vint8mf2_t*)(out + 700) = v;
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf2_t v = *(vint8mf2_t*)(in + 900 + i);
+    *(vint8mf2_t*)(out + 900 + i) = v;
+  }
+}
+
+void f4 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vint16mf4_t v = *(vint16mf4_t*)(in + 500);
+    *(vint16mf4_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vint16mf4_t v = *(vint16mf4_t*)(in + 500);
+    *(vint16mf4_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    vint16mf4_t v = *(vint16mf4_t*)(in + 700);
+    *(vint16mf4_t*)(out + 700) = v;
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint16mf4_t v = *(vint16mf4_t*)(in + 900 + i);
+    *(vint16mf4_t*)(out + 900 + i) = v;
+  }
+}
+
+void f5 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vint16mf2_t v = *(vint16mf2_t*)(in + 500);
+    *(vint16mf2_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vint16mf2_t v = *(vint16mf2_t*)(in + 500);
+    *(vint16mf2_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    vint16mf2_t v = *(vint16mf2_t*)(in + 700);
+    *(vint16mf2_t*)(out + 700) = v;
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint16mf2_t v = *(vint16mf2_t*)(in + 900 + i);
+    *(vint16mf2_t*)(out + 900 + i) = v;
+  }
+}
+
+void f6 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vuint32mf2_t v = *(vuint32mf2_t*)(in + 500);
+    *(vuint32mf2_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vuint32mf2_t v = *(vuint32mf2_t*)(in + 500);
+    *(vuint32mf2_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    vuint32mf2_t v = *(vuint32mf2_t*)(in + 700);
+    *(vuint32mf2_t*)(out + 700) = v;
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint32mf2_t v = *(vuint32mf2_t*)(in + 900 + i);
+    *(vuint32mf2_t*)(out + 900 + i) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9][0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c
new file mode 100644
index 0000000..1dfa2e9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c
@@ -0,0 +1,43 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 500);
+    *(vfloat32mf2_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 500);
+    *(vfloat32mf2_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 700);
+    *(vfloat32mf2_t*)(out + 700) = v;
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 900 + i);
+    *(vfloat32mf2_t*)(out + 900 + i) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c
new file mode 100644
index 0000000..fed1aa3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c
@@ -0,0 +1,266 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vbool64_t v = *(vbool64_t*)(in + 500);
+    *(vbool64_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vbool64_t v = *(vbool64_t*)(in + 500);
+    *(vbool64_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    vbool64_t v = *(vbool64_t*)(in + 700);
+    *(vbool64_t*)(out + 700) = v;
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool64_t v = *(vbool64_t*)(in + 900 + i);
+    *(vbool64_t*)(out + 900 + i) = v;
+  }
+}
+
+void f2 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vbool32_t v = *(vbool32_t*)(in + 500);
+    *(vbool32_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vbool32_t v = *(vbool32_t*)(in + 500);
+    *(vbool32_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    vbool32_t v = *(vbool32_t*)(in + 700);
+    *(vbool32_t*)(out + 700) = v;
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool32_t v = *(vbool32_t*)(in + 900 + i);
+    *(vbool32_t*)(out + 900 + i) = v;
+  }
+}
+
+void f3 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vbool16_t v = *(vbool16_t*)(in + 500);
+    *(vbool16_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vbool16_t v = *(vbool16_t*)(in + 500);
+    *(vbool16_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    vbool16_t v = *(vbool16_t*)(in + 700);
+    *(vbool16_t*)(out + 700) = v;
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool16_t v = *(vbool16_t*)(in + 900 + i);
+    *(vbool16_t*)(out + 900 + i) = v;
+  }
+}
+
+void f4 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vbool8_t v = *(vbool8_t*)(in + 500);
+    *(vbool8_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vbool8_t v = *(vbool8_t*)(in + 500);
+    *(vbool8_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    vbool8_t v = *(vbool8_t*)(in + 700);
+    *(vbool8_t*)(out + 700) = v;
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool8_t v = *(vbool8_t*)(in + 900 + i);
+    *(vbool8_t*)(out + 900 + i) = v;
+  }
+}
+
+void f5 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vbool4_t v = *(vbool4_t*)(in + 500);
+    *(vbool4_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vbool4_t v = *(vbool4_t*)(in + 500);
+    *(vbool4_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    vbool4_t v = *(vbool4_t*)(in + 700);
+    *(vbool4_t*)(out + 700) = v;
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool4_t v = *(vbool4_t*)(in + 900 + i);
+    *(vbool4_t*)(out + 900 + i) = v;
+  }
+}
+
+void f6 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vbool2_t v = *(vbool2_t*)(in + 500);
+    *(vbool2_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vbool2_t v = *(vbool2_t*)(in + 500);
+    *(vbool2_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    vbool2_t v = *(vbool2_t*)(in + 700);
+    *(vbool2_t*)(out + 700) = v;
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool2_t v = *(vbool2_t*)(in + 900 + i);
+    *(vbool2_t*)(out + 900 + i) = v;
+  }
+}
+
+void f7 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vbool1_t v = *(vbool1_t*)(in + 500);
+    *(vbool1_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vbool1_t v = *(vbool1_t*)(in + 500);
+    *(vbool1_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    vbool1_t v = *(vbool1_t*)(in + 700);
+    *(vbool1_t*)(out + 700) = v;
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool1_t v = *(vbool1_t*)(in + 900 + i);
+    *(vbool1_t*)(out + 900 + i) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" no-opts "-O1" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c
new file mode 100644
index 0000000..bcf8e1c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c
@@ -0,0 +1,221 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vint8mf8_t v = *(vint8mf8_t*)(in + 500);
+    *(vint8mf8_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vint8mf8_t v = *(vint8mf8_t*)(in + 500);
+    *(vint8mf8_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 900 + i);
+    *(vint8mf8_t*)(out + 900 + i) = v;
+  }
+}
+
+void f2 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vint8mf4_t v = *(vint8mf4_t*)(in + 500);
+    *(vint8mf4_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vint8mf4_t v = *(vint8mf4_t*)(in + 500);
+    *(vint8mf4_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf4_t v = *(vint8mf4_t*)(in + 900 + i);
+    *(vint8mf4_t*)(out + 900 + i) = v;
+  }
+}
+
+void f3 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vint8mf2_t v = *(vint8mf2_t*)(in + 500);
+    *(vint8mf2_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vint8mf2_t v = *(vint8mf2_t*)(in + 500);
+    *(vint8mf2_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf2_t v = *(vint8mf2_t*)(in + 900 + i);
+    *(vint8mf2_t*)(out + 900 + i) = v;
+  }
+}
+
+void f4 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vint16mf4_t v = *(vint16mf4_t*)(in + 500);
+    *(vint16mf4_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vint16mf4_t v = *(vint16mf4_t*)(in + 500);
+    *(vint16mf4_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint16mf4_t v = *(vint16mf4_t*)(in + 900 + i);
+    *(vint16mf4_t*)(out + 900 + i) = v;
+  }
+}
+
+void f5 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vint16mf2_t v = *(vint16mf2_t*)(in + 500);
+    *(vint16mf2_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vint16mf2_t v = *(vint16mf2_t*)(in + 500);
+    *(vint16mf2_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint16mf2_t v = *(vint16mf2_t*)(in + 900 + i);
+    *(vint16mf2_t*)(out + 900 + i) = v;
+  }
+}
+
+void f6 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vint32mf2_t v = *(vint32mf2_t*)(in + 500);
+    *(vint32mf2_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vint32mf2_t v = *(vint32mf2_t*)(in + 500);
+    *(vint32mf2_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 900 + i);
+    *(vint32mf2_t*)(out + 900 + i) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c
new file mode 100644
index 0000000..c2a8c3b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c
@@ -0,0 +1,221 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 500);
+    *(vuint8mf8_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 500);
+    *(vuint8mf8_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 900 + i);
+    *(vuint8mf8_t*)(out + 900 + i) = v;
+  }
+}
+
+void f2 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vuint8mf4_t v = *(vuint8mf4_t*)(in + 500);
+    *(vuint8mf4_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vuint8mf4_t v = *(vuint8mf4_t*)(in + 500);
+    *(vuint8mf4_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint8mf4_t v = *(vuint8mf4_t*)(in + 900 + i);
+    *(vuint8mf4_t*)(out + 900 + i) = v;
+  }
+}
+
+void f3 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vuint8mf2_t v = *(vuint8mf2_t*)(in + 500);
+    *(vuint8mf2_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vuint8mf2_t v = *(vuint8mf2_t*)(in + 500);
+    *(vuint8mf2_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint8mf2_t v = *(vuint8mf2_t*)(in + 900 + i);
+    *(vuint8mf2_t*)(out + 900 + i) = v;
+  }
+}
+
+void f4 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vuint16mf4_t v = *(vuint16mf4_t*)(in + 500);
+    *(vuint16mf4_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vuint16mf4_t v = *(vuint16mf4_t*)(in + 500);
+    *(vuint16mf4_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint16mf4_t v = *(vuint16mf4_t*)(in + 900 + i);
+    *(vuint16mf4_t*)(out + 900 + i) = v;
+  }
+}
+
+void f5 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vuint16mf2_t v = *(vuint16mf2_t*)(in + 500);
+    *(vuint16mf2_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vuint16mf2_t v = *(vuint16mf2_t*)(in + 500);
+    *(vuint16mf2_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint16mf2_t v = *(vuint16mf2_t*)(in + 900 + i);
+    *(vuint16mf2_t*)(out + 900 + i) = v;
+  }
+}
+
+void f6 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vuint32mf2_t v = *(vuint32mf2_t*)(in + 500);
+    *(vuint32mf2_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vuint32mf2_t v = *(vuint32mf2_t*)(in + 500);
+    *(vuint32mf2_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint32mf2_t v = *(vuint32mf2_t*)(in + 900 + i);
+    *(vuint32mf2_t*)(out + 900 + i) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c
new file mode 100644
index 0000000..e449078
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c
@@ -0,0 +1,41 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 500);
+    *(vfloat32mf2_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 500);
+    *(vfloat32mf2_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 900 + i);
+    *(vfloat32mf2_t*)(out + 900 + i) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c
new file mode 100644
index 0000000..224fc2e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c
@@ -0,0 +1,257 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vbool64_t v = *(vbool64_t*)(in + 500);
+    *(vbool64_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vbool64_t v = *(vbool64_t*)(in + 500);
+    *(vbool64_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool64_t v = *(vbool64_t*)(in + 900 + i);
+    *(vbool64_t*)(out + 900 + i) = v;
+  }
+}
+
+void f2 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vbool32_t v = *(vbool32_t*)(in + 500);
+    *(vbool32_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vbool32_t v = *(vbool32_t*)(in + 500);
+    *(vbool32_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool32_t v = *(vbool32_t*)(in + 900 + i);
+    *(vbool32_t*)(out + 900 + i) = v;
+  }
+}
+
+void f3 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vbool16_t v = *(vbool16_t*)(in + 500);
+    *(vbool16_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vbool16_t v = *(vbool16_t*)(in + 500);
+    *(vbool16_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool16_t v = *(vbool16_t*)(in + 900 + i);
+    *(vbool16_t*)(out + 900 + i) = v;
+  }
+}
+
+void f4 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vbool8_t v = *(vbool8_t*)(in + 500);
+    *(vbool8_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vbool8_t v = *(vbool8_t*)(in + 500);
+    *(vbool8_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool8_t v = *(vbool8_t*)(in + 900 + i);
+    *(vbool8_t*)(out + 900 + i) = v;
+  }
+}
+
+void f5 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vbool4_t v = *(vbool4_t*)(in + 500);
+    *(vbool4_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vbool4_t v = *(vbool4_t*)(in + 500);
+    *(vbool4_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool4_t v = *(vbool4_t*)(in + 900 + i);
+    *(vbool4_t*)(out + 900 + i) = v;
+  }
+}
+
+void f6 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vbool2_t v = *(vbool2_t*)(in + 500);
+    *(vbool2_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vbool2_t v = *(vbool2_t*)(in + 500);
+    *(vbool2_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool2_t v = *(vbool2_t*)(in + 900 + i);
+    *(vbool2_t*)(out + 900 + i) = v;
+  }
+}
+
+void f7 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vbool1_t v = *(vbool1_t*)(in + 500);
+    *(vbool1_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vbool1_t v = *(vbool1_t*)(in + 500);
+    *(vbool1_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool1_t v = *(vbool1_t*)(in + 900 + i);
+    *(vbool1_t*)(out + 900 + i) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+\.L[0-9][0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c
new file mode 100644
index 0000000..7cbabab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c
@@ -0,0 +1,177 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vint8mf8_t v = *(vint8mf8_t*)(in + 100);
+      *(vint8mf8_t*)(out + 100) = v;
+    }
+  else
+    {
+      vint8mf8_t v = *(vint8mf8_t*)(in + 200);
+      *(vint8mf8_t*)(out + 200) = v;
+      if (cond == 2)
+        {
+          out[1000] = 8000;
+        }
+      else
+        {
+          out[2000] = 9000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf8_t v = *(vint8mf8_t*)(in + i);
+      *(vint8mf8_t*)(out + i) = v;
+    }
+}
+
+void f2 (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vint8mf4_t v = *(vint8mf4_t*)(in + 100);
+      *(vint8mf4_t*)(out + 100) = v;
+    }
+  else
+    {
+      vint8mf4_t v = *(vint8mf4_t*)(in + 200);
+      *(vint8mf4_t*)(out + 200) = v;
+      if (cond == 2)
+        {
+          out[1000] = 8000;
+        }
+      else
+        {
+          out[2000] = 9000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf4_t v = *(vint8mf4_t*)(in + i);
+      *(vint8mf4_t*)(out + i) = v;
+    }
+}
+
+void f3 (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vint8mf2_t v = *(vint8mf2_t*)(in + 100);
+      *(vint8mf2_t*)(out + 100) = v;
+    }
+  else
+    {
+      vint8mf2_t v = *(vint8mf2_t*)(in + 200);
+      *(vint8mf2_t*)(out + 200) = v;
+      if (cond == 2)
+        {
+          out[1000] = 8000;
+        }
+      else
+        {
+          out[2000] = 9000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf2_t v = *(vint8mf2_t*)(in + i);
+      *(vint8mf2_t*)(out + i) = v;
+    }
+}
+
+void f4 (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vint16mf4_t v = *(vint16mf4_t*)(in + 100);
+      *(vint16mf4_t*)(out + 100) = v;
+    }
+  else
+    {
+      vint16mf4_t v = *(vint16mf4_t*)(in + 200);
+      *(vint16mf4_t*)(out + 200) = v;
+      if (cond == 2)
+        {
+          out[1000] = 8000;
+        }
+      else
+        {
+          out[2000] = 9000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vint16mf4_t v = *(vint16mf4_t*)(in + i);
+      *(vint16mf4_t*)(out + i) = v;
+    }
+}
+
+void f5 (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vint16mf2_t v = *(vint16mf2_t*)(in + 100);
+      *(vint16mf2_t*)(out + 100) = v;
+    }
+  else
+    {
+      vint16mf2_t v = *(vint16mf2_t*)(in + 200);
+      *(vint16mf2_t*)(out + 200) = v;
+      if (cond == 2)
+        {
+          out[1000] = 8000;
+        }
+      else
+        {
+          out[2000] = 9000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vint16mf2_t v = *(vint16mf2_t*)(in + i);
+      *(vint16mf2_t*)(out + i) = v;
+    }
+}
+
+void f6 (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vint32mf2_t v = *(vint32mf2_t*)(in + 100);
+      *(vint32mf2_t*)(out + 100) = v;
+    }
+  else
+    {
+      vint32mf2_t v = *(vint32mf2_t*)(in + 200);
+      *(vint32mf2_t*)(out + 200) = v;
+      if (cond == 2)
+        {
+          out[1000] = 8000;
+        }
+      else
+        {
+          out[2000] = 9000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vint32mf2_t v = *(vint32mf2_t*)(in + i);
+      *(vint32mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c
new file mode 100644
index 0000000..cfaba79
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c
@@ -0,0 +1,177 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vuint8mf8_t v = *(vuint8mf8_t*)(in + 100);
+      *(vuint8mf8_t*)(out + 100) = v;
+    }
+  else
+    {
+      vuint8mf8_t v = *(vuint8mf8_t*)(in + 200);
+      *(vuint8mf8_t*)(out + 200) = v;
+      if (cond == 2)
+        {
+          out[1000] = 8000;
+        }
+      else
+        {
+          out[2000] = 9000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vuint8mf8_t v = *(vuint8mf8_t*)(in + i);
+      *(vuint8mf8_t*)(out + i) = v;
+    }
+}
+
+void f2 (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vuint8mf4_t v = *(vuint8mf4_t*)(in + 100);
+      *(vuint8mf4_t*)(out + 100) = v;
+    }
+  else
+    {
+      vuint8mf4_t v = *(vuint8mf4_t*)(in + 200);
+      *(vuint8mf4_t*)(out + 200) = v;
+      if (cond == 2)
+        {
+          out[1000] = 8000;
+        }
+      else
+        {
+          out[2000] = 9000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vuint8mf4_t v = *(vuint8mf4_t*)(in + i);
+      *(vuint8mf4_t*)(out + i) = v;
+    }
+}
+
+void f3 (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vuint8mf2_t v = *(vuint8mf2_t*)(in + 100);
+      *(vuint8mf2_t*)(out + 100) = v;
+    }
+  else
+    {
+      vuint8mf2_t v = *(vuint8mf2_t*)(in + 200);
+      *(vuint8mf2_t*)(out + 200) = v;
+      if (cond == 2)
+        {
+          out[1000] = 8000;
+        }
+      else
+        {
+          out[2000] = 9000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vuint8mf2_t v = *(vuint8mf2_t*)(in + i);
+      *(vuint8mf2_t*)(out + i) = v;
+    }
+}
+
+void f4 (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vuint16mf4_t v = *(vuint16mf4_t*)(in + 100);
+      *(vuint16mf4_t*)(out + 100) = v;
+    }
+  else
+    {
+      vuint16mf4_t v = *(vuint16mf4_t*)(in + 200);
+      *(vuint16mf4_t*)(out + 200) = v;
+      if (cond == 2)
+        {
+          out[1000] = 8000;
+        }
+      else
+        {
+          out[2000] = 9000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vuint16mf4_t v = *(vuint16mf4_t*)(in + i);
+      *(vuint16mf4_t*)(out + i) = v;
+    }
+}
+
+void f5 (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vuint16mf2_t v = *(vuint16mf2_t*)(in + 100);
+      *(vuint16mf2_t*)(out + 100) = v;
+    }
+  else
+    {
+      vuint16mf2_t v = *(vuint16mf2_t*)(in + 200);
+      *(vuint16mf2_t*)(out + 200) = v;
+      if (cond == 2)
+        {
+          out[1000] = 8000;
+        }
+      else
+        {
+          out[2000] = 9000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vuint16mf2_t v = *(vuint16mf2_t*)(in + i);
+      *(vuint16mf2_t*)(out + i) = v;
+    }
+}
+
+void f6 (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vuint32mf2_t v = *(vuint32mf2_t*)(in + 100);
+      *(vuint32mf2_t*)(out + 100) = v;
+    }
+  else
+    {
+      vuint32mf2_t v = *(vuint32mf2_t*)(in + 200);
+      *(vuint32mf2_t*)(out + 200) = v;
+      if (cond == 2)
+        {
+          out[1000] = 8000;
+        }
+      else
+        {
+          out[2000] = 9000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vuint32mf2_t v = *(vuint32mf2_t*)(in + i);
+      *(vuint32mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c
new file mode 100644
index 0000000..4ea46c7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f6 (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 100);
+      *(vfloat32mf2_t*)(out + 100) = v;
+    }
+  else
+    {
+      vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 200);
+      *(vfloat32mf2_t*)(out + 200) = v;
+      if (cond == 2)
+        {
+          out[1000] = 8000;
+        }
+      else
+        {
+          out[2000] = 9000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vfloat32mf2_t v = *(vfloat32mf2_t*)(in + i);
+      *(vfloat32mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.c
new file mode 100644
index 0000000..4e478a8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.c
@@ -0,0 +1,182 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 500);
+    *(vuint8mf8_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 600);
+    *(vuint8mf8_t*)(out + 600) = v;
+  } else {
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 700);
+    *(vuint8mf8_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 900 + i);
+    *(vuint8mf8_t*)(out + 900 + i) = v;
+  }
+}
+
+void f2 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vuint8mf4_t v = *(vuint8mf4_t*)(in + 500);
+    *(vuint8mf4_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vuint8mf4_t v = *(vuint8mf4_t*)(in + 600);
+    *(vuint8mf4_t*)(out + 600) = v;
+  } else {
+    vuint8mf4_t v = *(vuint8mf4_t*)(in + 700);
+    *(vuint8mf4_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint8mf4_t v = *(vuint8mf4_t*)(in + 900 + i);
+    *(vuint8mf4_t*)(out + 900 + i) = v;
+  }
+}
+
+void f3 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vuint8mf2_t v = *(vuint8mf2_t*)(in + 500);
+    *(vuint8mf2_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vuint8mf2_t v = *(vuint8mf2_t*)(in + 600);
+    *(vuint8mf2_t*)(out + 600) = v;
+  } else {
+    vuint8mf2_t v = *(vuint8mf2_t*)(in + 700);
+    *(vuint8mf2_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint8mf2_t v = *(vuint8mf2_t*)(in + 900 + i);
+    *(vuint8mf2_t*)(out + 900 + i) = v;
+  }
+}
+
+void f4 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vuint16mf4_t v = *(vuint16mf4_t*)(in + 500);
+    *(vuint16mf4_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vuint16mf4_t v = *(vuint16mf4_t*)(in + 600);
+    *(vuint16mf4_t*)(out + 600) = v;
+  } else {
+    vuint16mf4_t v = *(vuint16mf4_t*)(in + 700);
+    *(vuint16mf4_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint16mf4_t v = *(vuint16mf4_t*)(in + 900 + i);
+    *(vuint16mf4_t*)(out + 900 + i) = v;
+  }
+}
+
+void f5 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vuint16mf2_t v = *(vuint16mf2_t*)(in + 500);
+    *(vuint16mf2_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vuint16mf2_t v = *(vuint16mf2_t*)(in + 600);
+    *(vuint16mf2_t*)(out + 600) = v;
+  } else {
+    vuint16mf2_t v = *(vuint16mf2_t*)(in + 700);
+    *(vuint16mf2_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint16mf2_t v = *(vuint16mf2_t*)(in + 900 + i);
+    *(vuint16mf2_t*)(out + 900 + i) = v;
+  }
+}
+
+void f6 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vuint32mf2_t v = *(vuint32mf2_t*)(in + 500);
+    *(vuint32mf2_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vuint32mf2_t v = *(vuint32mf2_t*)(in + 600);
+    *(vuint32mf2_t*)(out + 600) = v;
+  } else {
+    vuint32mf2_t v = *(vuint32mf2_t*)(in + 700);
+    *(vuint32mf2_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint32mf2_t v = *(vuint32mf2_t*)(in + 900 + i);
+    *(vuint32mf2_t*)(out + 900 + i) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O2" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O2" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O2" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O2" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O2" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O2" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O2" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O2" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O2" no-opts "-O1" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c
new file mode 100644
index 0000000..9562d8f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c
@@ -0,0 +1,203 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vbool64_t v = *(vbool64_t*)(in + 100);
+      *(vbool64_t*)(out + 100) = v;
+    }
+  else
+    {
+      vbool64_t v = *(vbool64_t*)(in + 200);
+      *(vbool64_t*)(out + 200) = v;
+      if (cond == 2)
+        {
+          out[1000] = 8000;
+        }
+      else
+        {
+          out[2000] = 9000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vbool64_t v = *(vbool64_t*)(in + i);
+      *(vbool64_t*)(out + i) = v;
+    }
+}
+
+void f2 (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vbool32_t v = *(vbool32_t*)(in + 100);
+      *(vbool32_t*)(out + 100) = v;
+    }
+  else
+    {
+      vbool32_t v = *(vbool32_t*)(in + 200);
+      *(vbool32_t*)(out + 200) = v;
+      if (cond == 2)
+        {
+          out[1000] = 8000;
+        }
+      else
+        {
+          out[2000] = 9000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vbool32_t v = *(vbool32_t*)(in + i);
+      *(vbool32_t*)(out + i) = v;
+    }
+}
+
+void f3 (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vbool16_t v = *(vbool16_t*)(in + 100);
+      *(vbool16_t*)(out + 100) = v;
+    }
+  else
+    {
+      vbool16_t v = *(vbool16_t*)(in + 200);
+      *(vbool16_t*)(out + 200) = v;
+      if (cond == 2)
+        {
+          out[1000] = 8000;
+        }
+      else
+        {
+          out[2000] = 9000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vbool16_t v = *(vbool16_t*)(in + i);
+      *(vbool16_t*)(out + i) = v;
+    }
+}
+
+void f4 (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vbool8_t v = *(vbool8_t*)(in + 100);
+      *(vbool8_t*)(out + 100) = v;
+    }
+  else
+    {
+      vbool8_t v = *(vbool8_t*)(in + 200);
+      *(vbool8_t*)(out + 200) = v;
+      if (cond == 2)
+        {
+          out[1000] = 8000;
+        }
+      else
+        {
+          out[2000] = 9000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vbool8_t v = *(vbool8_t*)(in + i);
+      *(vbool8_t*)(out + i) = v;
+    }
+}
+
+void f5 (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vbool4_t v = *(vbool4_t*)(in + 100);
+      *(vbool4_t*)(out + 100) = v;
+    }
+  else
+    {
+      vbool4_t v = *(vbool4_t*)(in + 200);
+      *(vbool4_t*)(out + 200) = v;
+      if (cond == 2)
+        {
+          out[1000] = 8000;
+        }
+      else
+        {
+          out[2000] = 9000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vbool4_t v = *(vbool4_t*)(in + i);
+      *(vbool4_t*)(out + i) = v;
+    }
+}
+
+void f6 (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vbool2_t v = *(vbool2_t*)(in + 100);
+      *(vbool2_t*)(out + 100) = v;
+    }
+  else
+    {
+      vbool2_t v = *(vbool2_t*)(in + 200);
+      *(vbool2_t*)(out + 200) = v;
+      if (cond == 2)
+        {
+          out[1000] = 8000;
+        }
+      else
+        {
+          out[2000] = 9000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vbool2_t v = *(vbool2_t*)(in + i);
+      *(vbool2_t*)(out + i) = v;
+    }
+}
+
+void f7 (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vbool1_t v = *(vbool1_t*)(in + 100);
+      *(vbool1_t*)(out + 100) = v;
+    }
+  else
+    {
+      vbool1_t v = *(vbool1_t*)(in + 200);
+      *(vbool1_t*)(out + 200) = v;
+      if (cond == 2)
+        {
+          out[1000] = 8000;
+        }
+      else
+        {
+          out[2000] = 9000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vbool1_t v = *(vbool1_t*)(in + i);
+      *(vbool1_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 6 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c
new file mode 100644
index 0000000..198b72f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c
@@ -0,0 +1,155 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vint8mf8_t v = *(vint8mf8_t*)(in + 100);
+      *(vint8mf8_t*)(out + 100) = v;
+    }
+  else
+    {
+      if (cond == 2)
+        {
+          vint8mf8_t v = *(vint8mf8_t*)(in + 200);
+          *(vint8mf8_t*)(out + 200) = v;
+          out[1000] = 8000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf8_t v = *(vint8mf8_t*)(in + i);
+      *(vint8mf8_t*)(out + i) = v;
+    }
+}
+
+void f2 (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vint8mf4_t v = *(vint8mf4_t*)(in + 100);
+      *(vint8mf4_t*)(out + 100) = v;
+    }
+  else
+    {
+      if (cond == 2)
+        {
+          vint8mf4_t v = *(vint8mf4_t*)(in + 200);
+          *(vint8mf4_t*)(out + 200) = v;
+          out[1000] = 8000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf4_t v = *(vint8mf4_t*)(in + i);
+      *(vint8mf4_t*)(out + i) = v;
+    }
+}
+
+void f3 (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vint8mf2_t v = *(vint8mf2_t*)(in + 100);
+      *(vint8mf2_t*)(out + 100) = v;
+    }
+  else
+    {
+      if (cond == 2)
+        {
+          vint8mf2_t v = *(vint8mf2_t*)(in + 200);
+          *(vint8mf2_t*)(out + 200) = v;
+          out[1000] = 8000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf2_t v = *(vint8mf2_t*)(in + i);
+      *(vint8mf2_t*)(out + i) = v;
+    }
+}
+
+void f4 (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vint16mf4_t v = *(vint16mf4_t*)(in + 100);
+      *(vint16mf4_t*)(out + 100) = v;
+    }
+  else
+    {
+      if (cond == 2)
+        {
+          vint16mf4_t v = *(vint16mf4_t*)(in + 200);
+          *(vint16mf4_t*)(out + 200) = v;
+          out[1000] = 8000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vint16mf4_t v = *(vint16mf4_t*)(in + i);
+      *(vint16mf4_t*)(out + i) = v;
+    }
+}
+
+void f5 (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vint16mf2_t v = *(vint16mf2_t*)(in + 100);
+      *(vint16mf2_t*)(out + 100) = v;
+    }
+  else
+    {
+      if (cond == 2)
+        {
+          vint16mf2_t v = *(vint16mf2_t*)(in + 200);
+          *(vint16mf2_t*)(out + 200) = v;
+          out[1000] = 8000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vint16mf2_t v = *(vint16mf2_t*)(in + i);
+      *(vint16mf2_t*)(out + i) = v;
+    }
+}
+
+void f6 (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vint32mf2_t v = *(vint32mf2_t*)(in + 100);
+      *(vint32mf2_t*)(out + 100) = v;
+    }
+  else
+    {
+      if (cond == 2)
+        {
+          vint32mf2_t v = *(vint32mf2_t*)(in + 200);
+          *(vint32mf2_t*)(out + 200) = v;
+          out[1000] = 8000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vint32mf2_t v = *(vint32mf2_t*)(in + i);
+      *(vint32mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c
new file mode 100644
index 0000000..ca20f2f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c
@@ -0,0 +1,155 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vuint8mf8_t v = *(vuint8mf8_t*)(in + 100);
+      *(vuint8mf8_t*)(out + 100) = v;
+    }
+  else
+    {
+      if (cond == 2)
+        {
+          vuint8mf8_t v = *(vuint8mf8_t*)(in + 200);
+          *(vuint8mf8_t*)(out + 200) = v;
+          out[1000] = 8000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vuint8mf8_t v = *(vuint8mf8_t*)(in + i);
+      *(vuint8mf8_t*)(out + i) = v;
+    }
+}
+
+void f2 (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vuint8mf4_t v = *(vuint8mf4_t*)(in + 100);
+      *(vuint8mf4_t*)(out + 100) = v;
+    }
+  else
+    {
+      if (cond == 2)
+        {
+          vuint8mf4_t v = *(vuint8mf4_t*)(in + 200);
+          *(vuint8mf4_t*)(out + 200) = v;
+          out[1000] = 8000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vuint8mf4_t v = *(vuint8mf4_t*)(in + i);
+      *(vuint8mf4_t*)(out + i) = v;
+    }
+}
+
+void f3 (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vuint8mf2_t v = *(vuint8mf2_t*)(in + 100);
+      *(vuint8mf2_t*)(out + 100) = v;
+    }
+  else
+    {
+      if (cond == 2)
+        {
+          vuint8mf2_t v = *(vuint8mf2_t*)(in + 200);
+          *(vuint8mf2_t*)(out + 200) = v;
+          out[1000] = 8000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vuint8mf2_t v = *(vuint8mf2_t*)(in + i);
+      *(vuint8mf2_t*)(out + i) = v;
+    }
+}
+
+void f4 (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vuint16mf4_t v = *(vuint16mf4_t*)(in + 100);
+      *(vuint16mf4_t*)(out + 100) = v;
+    }
+  else
+    {
+      if (cond == 2)
+        {
+          vuint16mf4_t v = *(vuint16mf4_t*)(in + 200);
+          *(vuint16mf4_t*)(out + 200) = v;
+          out[1000] = 8000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vuint16mf4_t v = *(vuint16mf4_t*)(in + i);
+      *(vuint16mf4_t*)(out + i) = v;
+    }
+}
+
+void f5 (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vuint16mf2_t v = *(vuint16mf2_t*)(in + 100);
+      *(vuint16mf2_t*)(out + 100) = v;
+    }
+  else
+    {
+      if (cond == 2)
+        {
+          vuint16mf2_t v = *(vuint16mf2_t*)(in + 200);
+          *(vuint16mf2_t*)(out + 200) = v;
+          out[1000] = 8000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vuint16mf2_t v = *(vuint16mf2_t*)(in + i);
+      *(vuint16mf2_t*)(out + i) = v;
+    }
+}
+
+void f6 (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vuint32mf2_t v = *(vuint32mf2_t*)(in + 100);
+      *(vuint32mf2_t*)(out + 100) = v;
+    }
+  else
+    {
+      if (cond == 2)
+        {
+          vuint32mf2_t v = *(vuint32mf2_t*)(in + 200);
+          *(vuint32mf2_t*)(out + 200) = v;
+          out[1000] = 8000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vuint32mf2_t v = *(vuint32mf2_t*)(in + i);
+      *(vuint32mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c
new file mode 100644
index 0000000..ecd8a20
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vuint32mf2_t v = *(vuint32mf2_t*)(in + 100);
+      *(vuint32mf2_t*)(out + 100) = v;
+    }
+  else
+    {
+      if (cond == 2)
+        {
+          vuint32mf2_t v = *(vuint32mf2_t*)(in + 200);
+          *(vuint32mf2_t*)(out + 200) = v;
+          out[1000] = 8000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vuint32mf2_t v = *(vuint32mf2_t*)(in + i);
+      *(vuint32mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c
new file mode 100644
index 0000000..a9ed211
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c
@@ -0,0 +1,180 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vbool64_t v = *(vbool64_t*)(in + 100);
+      *(vbool64_t*)(out + 100) = v;
+    }
+  else
+    {
+      if (cond == 2)
+        {
+          vbool64_t v = *(vbool64_t*)(in + 200);
+          *(vbool64_t*)(out + 200) = v;
+          out[1000] = 8000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vbool64_t v = *(vbool64_t*)(in + i);
+      *(vbool64_t*)(out + i) = v;
+    }
+}
+
+void f2 (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vbool32_t v = *(vbool32_t*)(in + 100);
+      *(vbool32_t*)(out + 100) = v;
+    }
+  else
+    {
+      if (cond == 2)
+        {
+          vbool32_t v = *(vbool32_t*)(in + 200);
+          *(vbool32_t*)(out + 200) = v;
+          out[1000] = 8000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vbool32_t v = *(vbool32_t*)(in + i);
+      *(vbool32_t*)(out + i) = v;
+    }
+}
+
+void f3 (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vbool16_t v = *(vbool16_t*)(in + 100);
+      *(vbool16_t*)(out + 100) = v;
+    }
+  else
+    {
+      if (cond == 2)
+        {
+          vbool16_t v = *(vbool16_t*)(in + 200);
+          *(vbool16_t*)(out + 200) = v;
+          out[1000] = 8000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vbool16_t v = *(vbool16_t*)(in + i);
+      *(vbool16_t*)(out + i) = v;
+    }
+}
+
+void f4 (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vbool8_t v = *(vbool8_t*)(in + 100);
+      *(vbool8_t*)(out + 100) = v;
+    }
+  else
+    {
+      if (cond == 2)
+        {
+          vbool8_t v = *(vbool8_t*)(in + 200);
+          *(vbool8_t*)(out + 200) = v;
+          out[1000] = 8000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vbool8_t v = *(vbool8_t*)(in + i);
+      *(vbool8_t*)(out + i) = v;
+    }
+}
+
+void f5 (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vbool4_t v = *(vbool4_t*)(in + 100);
+      *(vbool4_t*)(out + 100) = v;
+    }
+  else
+    {
+      if (cond == 2)
+        {
+          vbool4_t v = *(vbool4_t*)(in + 200);
+          *(vbool4_t*)(out + 200) = v;
+          out[1000] = 8000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vbool4_t v = *(vbool4_t*)(in + i);
+      *(vbool4_t*)(out + i) = v;
+    }
+}
+
+void f6 (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vbool2_t v = *(vbool2_t*)(in + 100);
+      *(vbool2_t*)(out + 100) = v;
+    }
+  else
+    {
+      if (cond == 2)
+        {
+          vbool2_t v = *(vbool2_t*)(in + 200);
+          *(vbool2_t*)(out + 200) = v;
+          out[1000] = 8000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vbool2_t v = *(vbool2_t*)(in + i);
+      *(vbool2_t*)(out + i) = v;
+    }
+}
+
+void f7 (int * restrict in, int * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vbool1_t v = *(vbool1_t*)(in + 100);
+      *(vbool1_t*)(out + 100) = v;
+    }
+  else
+    {
+      if (cond == 2)
+        {
+          vbool1_t v = *(vbool1_t*)(in + 200);
+          *(vbool1_t*)(out + 200) = v;
+          out[1000] = 8000;
+        }
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vbool1_t v = *(vbool1_t*)(in + i);
+      *(vbool1_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c
new file mode 100644
index 0000000..f87a8cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c
@@ -0,0 +1,572 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vbool64_t v = *(vbool64_t*)(in + 500);
+    *(vbool64_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vbool64_t v = *(vbool64_t*)(in + 600);
+    *(vbool64_t*)(out + 600) = v;
+  } else {
+    vbool64_t v = *(vbool64_t*)(in + 700);
+    *(vbool64_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool64_t v = *(vbool64_t*)(in + 900 + i);
+    *(vbool64_t*)(out + 900 + i) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  if (n == 0) {
+    vbool64_t v = *(vbool64_t*)(in + 500);
+    *(vbool64_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vbool64_t v = *(vbool64_t*)(in + 600);
+    *(vbool64_t*)(out + 600) = v;
+  } else {
+    vbool64_t v = *(vbool64_t*)(in + 700);
+    *(vbool64_t*)(out + 700) = v;
+  }
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool64_t v = *(vbool64_t*)(in + 900 + i);
+    *(vbool64_t*)(out + 900 + i) = v;
+  }
+}
+
+void f2 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vbool32_t v = *(vbool32_t*)(in + 500);
+    *(vbool32_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vbool32_t v = *(vbool32_t*)(in + 600);
+    *(vbool32_t*)(out + 600) = v;
+  } else {
+    vbool32_t v = *(vbool32_t*)(in + 700);
+    *(vbool32_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool32_t v = *(vbool32_t*)(in + 900 + i);
+    *(vbool32_t*)(out + 900 + i) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  if (n == 0) {
+    vbool32_t v = *(vbool32_t*)(in + 500);
+    *(vbool32_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vbool32_t v = *(vbool32_t*)(in + 600);
+    *(vbool32_t*)(out + 600) = v;
+  } else {
+    vbool32_t v = *(vbool32_t*)(in + 700);
+    *(vbool32_t*)(out + 700) = v;
+  }
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool32_t v = *(vbool32_t*)(in + 900 + i);
+    *(vbool32_t*)(out + 900 + i) = v;
+  }
+}
+
+void f3 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vbool16_t v = *(vbool16_t*)(in + 500);
+    *(vbool16_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vbool16_t v = *(vbool16_t*)(in + 600);
+    *(vbool16_t*)(out + 600) = v;
+  } else {
+    vbool16_t v = *(vbool16_t*)(in + 700);
+    *(vbool16_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool16_t v = *(vbool16_t*)(in + 900 + i);
+    *(vbool16_t*)(out + 900 + i) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  if (n == 0) {
+    vbool16_t v = *(vbool16_t*)(in + 500);
+    *(vbool16_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vbool16_t v = *(vbool16_t*)(in + 600);
+    *(vbool16_t*)(out + 600) = v;
+  } else {
+    vbool16_t v = *(vbool16_t*)(in + 700);
+    *(vbool16_t*)(out + 700) = v;
+  }
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool16_t v = *(vbool16_t*)(in + 900 + i);
+    *(vbool16_t*)(out + 900 + i) = v;
+  }
+}
+
+void f4 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vbool8_t v = *(vbool8_t*)(in + 500);
+    *(vbool8_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vbool8_t v = *(vbool8_t*)(in + 600);
+    *(vbool8_t*)(out + 600) = v;
+  } else {
+    vbool8_t v = *(vbool8_t*)(in + 700);
+    *(vbool8_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool8_t v = *(vbool8_t*)(in + 900 + i);
+    *(vbool8_t*)(out + 900 + i) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  if (n == 0) {
+    vbool8_t v = *(vbool8_t*)(in + 500);
+    *(vbool8_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vbool8_t v = *(vbool8_t*)(in + 600);
+    *(vbool8_t*)(out + 600) = v;
+  } else {
+    vbool8_t v = *(vbool8_t*)(in + 700);
+    *(vbool8_t*)(out + 700) = v;
+  }
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool8_t v = *(vbool8_t*)(in + 900 + i);
+    *(vbool8_t*)(out + 900 + i) = v;
+  }
+}
+
+void f5 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vbool4_t v = *(vbool4_t*)(in + 500);
+    *(vbool4_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vbool4_t v = *(vbool4_t*)(in + 600);
+    *(vbool4_t*)(out + 600) = v;
+  } else {
+    vbool4_t v = *(vbool4_t*)(in + 700);
+    *(vbool4_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool4_t v = *(vbool4_t*)(in + 900 + i);
+    *(vbool4_t*)(out + 900 + i) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  if (n == 0) {
+    vbool4_t v = *(vbool4_t*)(in + 500);
+    *(vbool4_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vbool4_t v = *(vbool4_t*)(in + 600);
+    *(vbool4_t*)(out + 600) = v;
+  } else {
+    vbool4_t v = *(vbool4_t*)(in + 700);
+    *(vbool4_t*)(out + 700) = v;
+  }
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool4_t v = *(vbool4_t*)(in + 900 + i);
+    *(vbool4_t*)(out + 900 + i) = v;
+  }
+}
+
+void f6 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vbool2_t v = *(vbool2_t*)(in + 500);
+    *(vbool2_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vbool2_t v = *(vbool2_t*)(in + 600);
+    *(vbool2_t*)(out + 600) = v;
+  } else {
+    vbool2_t v = *(vbool2_t*)(in + 700);
+    *(vbool2_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool2_t v = *(vbool2_t*)(in + 900 + i);
+    *(vbool2_t*)(out + 900 + i) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  if (n == 0) {
+    vbool2_t v = *(vbool2_t*)(in + 500);
+    *(vbool2_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vbool2_t v = *(vbool2_t*)(in + 600);
+    *(vbool2_t*)(out + 600) = v;
+  } else {
+    vbool2_t v = *(vbool2_t*)(in + 700);
+    *(vbool2_t*)(out + 700) = v;
+  }
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool2_t v = *(vbool2_t*)(in + 900 + i);
+    *(vbool2_t*)(out + 900 + i) = v;
+  }
+}
+
+void f7 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vbool1_t v = *(vbool1_t*)(in + 500);
+    *(vbool1_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vbool1_t v = *(vbool1_t*)(in + 600);
+    *(vbool1_t*)(out + 600) = v;
+  } else {
+    vbool1_t v = *(vbool1_t*)(in + 700);
+    *(vbool1_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool1_t v = *(vbool1_t*)(in + 900 + i);
+    *(vbool1_t*)(out + 900 + i) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  if (n == 0) {
+    vbool1_t v = *(vbool1_t*)(in + 500);
+    *(vbool1_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vbool1_t v = *(vbool1_t*)(in + 600);
+    *(vbool1_t*)(out + 600) = v;
+  } else {
+    vbool1_t v = *(vbool1_t*)(in + 700);
+    *(vbool1_t*)(out + 700) = v;
+  }
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool1_t v = *(vbool1_t*)(in + 900 + i);
+    *(vbool1_t*)(out + 900 + i) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c
new file mode 100644
index 0000000..c123855
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c
@@ -0,0 +1,492 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 500);
+    *(vint8mf8_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 600);
+    *(vint8mf8_t*)(out + 600) = v;
+  } else {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 700);
+    *(vint8mf8_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 900 + i);
+    *(vint8mf8_t*)(out + 900 + i) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  if (n == 0) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 500);
+    *(vint8mf8_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 600);
+    *(vint8mf8_t*)(out + 600) = v;
+  } else {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 700);
+    *(vint8mf8_t*)(out + 700) = v;
+  }
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 900 + i);
+    *(vint8mf8_t*)(out + 900 + i) = v;
+  }
+}
+
+void f2 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vint8mf4_t v = *(vint8mf4_t*)(in + 500);
+    *(vint8mf4_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vint8mf4_t v = *(vint8mf4_t*)(in + 600);
+    *(vint8mf4_t*)(out + 600) = v;
+  } else {
+    vint8mf4_t v = *(vint8mf4_t*)(in + 700);
+    *(vint8mf4_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf4_t v = *(vint8mf4_t*)(in + 900 + i);
+    *(vint8mf4_t*)(out + 900 + i) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  if (n == 0) {
+    vint8mf4_t v = *(vint8mf4_t*)(in + 500);
+    *(vint8mf4_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vint8mf4_t v = *(vint8mf4_t*)(in + 600);
+    *(vint8mf4_t*)(out + 600) = v;
+  } else {
+    vint8mf4_t v = *(vint8mf4_t*)(in + 700);
+    *(vint8mf4_t*)(out + 700) = v;
+  }
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf4_t v = *(vint8mf4_t*)(in + 900 + i);
+    *(vint8mf4_t*)(out + 900 + i) = v;
+  }
+}
+
+void f3 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vint8mf2_t v = *(vint8mf2_t*)(in + 500);
+    *(vint8mf2_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vint8mf2_t v = *(vint8mf2_t*)(in + 600);
+    *(vint8mf2_t*)(out + 600) = v;
+  } else {
+    vint8mf2_t v = *(vint8mf2_t*)(in + 700);
+    *(vint8mf2_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf2_t v = *(vint8mf2_t*)(in + 900 + i);
+    *(vint8mf2_t*)(out + 900 + i) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  if (n == 0) {
+    vint8mf2_t v = *(vint8mf2_t*)(in + 500);
+    *(vint8mf2_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vint8mf2_t v = *(vint8mf2_t*)(in + 600);
+    *(vint8mf2_t*)(out + 600) = v;
+  } else {
+    vint8mf2_t v = *(vint8mf2_t*)(in + 700);
+    *(vint8mf2_t*)(out + 700) = v;
+  }
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf2_t v = *(vint8mf2_t*)(in + 900 + i);
+    *(vint8mf2_t*)(out + 900 + i) = v;
+  }
+}
+
+void f4 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vint16mf4_t v = *(vint16mf4_t*)(in + 500);
+    *(vint16mf4_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vint16mf4_t v = *(vint16mf4_t*)(in + 600);
+    *(vint16mf4_t*)(out + 600) = v;
+  } else {
+    vint16mf4_t v = *(vint16mf4_t*)(in + 700);
+    *(vint16mf4_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint16mf4_t v = *(vint16mf4_t*)(in + 900 + i);
+    *(vint16mf4_t*)(out + 900 + i) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  if (n == 0) {
+    vint16mf4_t v = *(vint16mf4_t*)(in + 500);
+    *(vint16mf4_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vint16mf4_t v = *(vint16mf4_t*)(in + 600);
+    *(vint16mf4_t*)(out + 600) = v;
+  } else {
+    vint16mf4_t v = *(vint16mf4_t*)(in + 700);
+    *(vint16mf4_t*)(out + 700) = v;
+  }
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint16mf4_t v = *(vint16mf4_t*)(in + 900 + i);
+    *(vint16mf4_t*)(out + 900 + i) = v;
+  }
+}
+
+void f5 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vint16mf2_t v = *(vint16mf2_t*)(in + 500);
+    *(vint16mf2_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vint16mf2_t v = *(vint16mf2_t*)(in + 600);
+    *(vint16mf2_t*)(out + 600) = v;
+  } else {
+    vint16mf2_t v = *(vint16mf2_t*)(in + 700);
+    *(vint16mf2_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint16mf2_t v = *(vint16mf2_t*)(in + 900 + i);
+    *(vint16mf2_t*)(out + 900 + i) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  if (n == 0) {
+    vint16mf2_t v = *(vint16mf2_t*)(in + 500);
+    *(vint16mf2_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vint16mf2_t v = *(vint16mf2_t*)(in + 600);
+    *(vint16mf2_t*)(out + 600) = v;
+  } else {
+    vint16mf2_t v = *(vint16mf2_t*)(in + 700);
+    *(vint16mf2_t*)(out + 700) = v;
+  }
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint16mf2_t v = *(vint16mf2_t*)(in + 900 + i);
+    *(vint16mf2_t*)(out + 900 + i) = v;
+  }
+}
+
+void f6 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 500);
+    *(vint32mf2_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 600);
+    *(vint32mf2_t*)(out + 600) = v;
+  } else {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 700);
+    *(vint32mf2_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 900 + i);
+    *(vint32mf2_t*)(out + 900 + i) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  if (n == 0) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 500);
+    *(vint32mf2_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 600);
+    *(vint32mf2_t*)(out + 600) = v;
+  } else {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 700);
+    *(vint32mf2_t*)(out + 700) = v;
+  }
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 900 + i);
+    *(vint32mf2_t*)(out + 900 + i) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c
new file mode 100644
index 0000000..6265000
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c
@@ -0,0 +1,491 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 500);
+    *(vuint8mf8_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 600);
+    *(vuint8mf8_t*)(out + 600) = v;
+  } else {
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 700);
+    *(vuint8mf8_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 900 + i);
+    *(vuint8mf8_t*)(out + 900 + i) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  if (n == 0) {
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 500);
+    *(vuint8mf8_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 600);
+    *(vuint8mf8_t*)(out + 600) = v;
+  } else {
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 700);
+    *(vuint8mf8_t*)(out + 700) = v;
+  }
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 900 + i);
+    *(vuint8mf8_t*)(out + 900 + i) = v;
+  }
+}
+
+void f2 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vuint8mf4_t v = *(vuint8mf4_t*)(in + 500);
+    *(vuint8mf4_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vuint8mf4_t v = *(vuint8mf4_t*)(in + 600);
+    *(vuint8mf4_t*)(out + 600) = v;
+  } else {
+    vuint8mf4_t v = *(vuint8mf4_t*)(in + 700);
+    *(vuint8mf4_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint8mf4_t v = *(vuint8mf4_t*)(in + 900 + i);
+    *(vuint8mf4_t*)(out + 900 + i) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  if (n == 0) {
+    vuint8mf4_t v = *(vuint8mf4_t*)(in + 500);
+    *(vuint8mf4_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vuint8mf4_t v = *(vuint8mf4_t*)(in + 600);
+    *(vuint8mf4_t*)(out + 600) = v;
+  } else {
+    vuint8mf4_t v = *(vuint8mf4_t*)(in + 700);
+    *(vuint8mf4_t*)(out + 700) = v;
+  }
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint8mf4_t v = *(vuint8mf4_t*)(in + 900 + i);
+    *(vuint8mf4_t*)(out + 900 + i) = v;
+  }
+}
+
+void f3 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vuint8mf2_t v = *(vuint8mf2_t*)(in + 500);
+    *(vuint8mf2_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vuint8mf2_t v = *(vuint8mf2_t*)(in + 600);
+    *(vuint8mf2_t*)(out + 600) = v;
+  } else {
+    vuint8mf2_t v = *(vuint8mf2_t*)(in + 700);
+    *(vuint8mf2_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint8mf2_t v = *(vuint8mf2_t*)(in + 900 + i);
+    *(vuint8mf2_t*)(out + 900 + i) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  if (n == 0) {
+    vuint8mf2_t v = *(vuint8mf2_t*)(in + 500);
+    *(vuint8mf2_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vuint8mf2_t v = *(vuint8mf2_t*)(in + 600);
+    *(vuint8mf2_t*)(out + 600) = v;
+  } else {
+    vuint8mf2_t v = *(vuint8mf2_t*)(in + 700);
+    *(vuint8mf2_t*)(out + 700) = v;
+  }
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint8mf2_t v = *(vuint8mf2_t*)(in + 900 + i);
+    *(vuint8mf2_t*)(out + 900 + i) = v;
+  }
+}
+
+void f4 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vuint16mf4_t v = *(vuint16mf4_t*)(in + 500);
+    *(vuint16mf4_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vuint16mf4_t v = *(vuint16mf4_t*)(in + 600);
+    *(vuint16mf4_t*)(out + 600) = v;
+  } else {
+    vuint16mf4_t v = *(vuint16mf4_t*)(in + 700);
+    *(vuint16mf4_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint16mf4_t v = *(vuint16mf4_t*)(in + 900 + i);
+    *(vuint16mf4_t*)(out + 900 + i) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  if (n == 0) {
+    vuint16mf4_t v = *(vuint16mf4_t*)(in + 500);
+    *(vuint16mf4_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vuint16mf4_t v = *(vuint16mf4_t*)(in + 600);
+    *(vuint16mf4_t*)(out + 600) = v;
+  } else {
+    vuint16mf4_t v = *(vuint16mf4_t*)(in + 700);
+    *(vuint16mf4_t*)(out + 700) = v;
+  }
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint16mf4_t v = *(vuint16mf4_t*)(in + 900 + i);
+    *(vuint16mf4_t*)(out + 900 + i) = v;
+  }
+}
+
+void f5 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vuint16mf2_t v = *(vuint16mf2_t*)(in + 500);
+    *(vuint16mf2_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vuint16mf2_t v = *(vuint16mf2_t*)(in + 600);
+    *(vuint16mf2_t*)(out + 600) = v;
+  } else {
+    vuint16mf2_t v = *(vuint16mf2_t*)(in + 700);
+    *(vuint16mf2_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint16mf2_t v = *(vuint16mf2_t*)(in + 900 + i);
+    *(vuint16mf2_t*)(out + 900 + i) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  if (n == 0) {
+    vuint16mf2_t v = *(vuint16mf2_t*)(in + 500);
+    *(vuint16mf2_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vuint16mf2_t v = *(vuint16mf2_t*)(in + 600);
+    *(vuint16mf2_t*)(out + 600) = v;
+  } else {
+    vuint16mf2_t v = *(vuint16mf2_t*)(in + 700);
+    *(vuint16mf2_t*)(out + 700) = v;
+  }
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint16mf2_t v = *(vuint16mf2_t*)(in + 900 + i);
+    *(vuint16mf2_t*)(out + 900 + i) = v;
+  }
+}
+
+void f6 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vuint32mf2_t v = *(vuint32mf2_t*)(in + 500);
+    *(vuint32mf2_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vuint32mf2_t v = *(vuint32mf2_t*)(in + 600);
+    *(vuint32mf2_t*)(out + 600) = v;
+  } else {
+    vuint32mf2_t v = *(vuint32mf2_t*)(in + 700);
+    *(vuint32mf2_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint32mf2_t v = *(vuint32mf2_t*)(in + 900 + i);
+    *(vuint32mf2_t*)(out + 900 + i) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  if (n == 0) {
+    vuint32mf2_t v = *(vuint32mf2_t*)(in + 500);
+    *(vuint32mf2_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vuint32mf2_t v = *(vuint32mf2_t*)(in + 600);
+    *(vuint32mf2_t*)(out + 600) = v;
+  } else {
+    vuint32mf2_t v = *(vuint32mf2_t*)(in + 700);
+    *(vuint32mf2_t*)(out + 700) = v;
+  }
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint32mf2_t v = *(vuint32mf2_t*)(in + 900 + i);
+    *(vuint32mf2_t*)(out + 900 + i) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c
new file mode 100644
index 0000000..de7c5f9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c
@@ -0,0 +1,86 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f6 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 500);
+    *(vfloat32mf2_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 600);
+    *(vfloat32mf2_t*)(out + 600) = v;
+  } else {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 700);
+    *(vfloat32mf2_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 900 + i);
+    *(vfloat32mf2_t*)(out + 900 + i) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  if (n == 0) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 500);
+    *(vfloat32mf2_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 600);
+    *(vfloat32mf2_t*)(out + 600) = v;
+  } else {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 700);
+    *(vfloat32mf2_t*)(out + 700) = v;
+  }
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 900 + i);
+    *(vfloat32mf2_t*)(out + 900 + i) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c
new file mode 100644
index 0000000..f920017
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 500);
+    *(vfloat32mf2_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 600);
+    *(vfloat32mf2_t*)(out + 600) = v;
+  } else {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 700);
+    *(vfloat32mf2_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 900 + i);
+    *(vfloat32mf2_t*)(out + 900 + i) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c
new file mode 100644
index 0000000..31a9e43
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c
@@ -0,0 +1,210 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vbool64_t v = *(vbool64_t*)(in + 500);
+    *(vbool64_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vbool64_t v = *(vbool64_t*)(in + 600);
+    *(vbool64_t*)(out + 600) = v;
+  } else {
+    vbool64_t v = *(vbool64_t*)(in + 700);
+    *(vbool64_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool64_t v = *(vbool64_t*)(in + 900 + i);
+    *(vbool64_t*)(out + 900 + i) = v;
+  }
+}
+
+void f2 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vbool32_t v = *(vbool32_t*)(in + 500);
+    *(vbool32_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vbool32_t v = *(vbool32_t*)(in + 600);
+    *(vbool32_t*)(out + 600) = v;
+  } else {
+    vbool32_t v = *(vbool32_t*)(in + 700);
+    *(vbool32_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool32_t v = *(vbool32_t*)(in + 900 + i);
+    *(vbool32_t*)(out + 900 + i) = v;
+  }
+}
+
+void f3 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vbool16_t v = *(vbool16_t*)(in + 500);
+    *(vbool16_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vbool16_t v = *(vbool16_t*)(in + 600);
+    *(vbool16_t*)(out + 600) = v;
+  } else {
+    vbool16_t v = *(vbool16_t*)(in + 700);
+    *(vbool16_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool16_t v = *(vbool16_t*)(in + 900 + i);
+    *(vbool16_t*)(out + 900 + i) = v;
+  }
+}
+
+void f4 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vbool8_t v = *(vbool8_t*)(in + 500);
+    *(vbool8_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vbool8_t v = *(vbool8_t*)(in + 600);
+    *(vbool8_t*)(out + 600) = v;
+  } else {
+    vbool8_t v = *(vbool8_t*)(in + 700);
+    *(vbool8_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool8_t v = *(vbool8_t*)(in + 900 + i);
+    *(vbool8_t*)(out + 900 + i) = v;
+  }
+}
+
+void f5 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vbool4_t v = *(vbool4_t*)(in + 500);
+    *(vbool4_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vbool4_t v = *(vbool4_t*)(in + 600);
+    *(vbool4_t*)(out + 600) = v;
+  } else {
+    vbool4_t v = *(vbool4_t*)(in + 700);
+    *(vbool4_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool4_t v = *(vbool4_t*)(in + 900 + i);
+    *(vbool4_t*)(out + 900 + i) = v;
+  }
+}
+
+void f6 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vbool2_t v = *(vbool2_t*)(in + 500);
+    *(vbool2_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vbool2_t v = *(vbool2_t*)(in + 600);
+    *(vbool2_t*)(out + 600) = v;
+  } else {
+    vbool2_t v = *(vbool2_t*)(in + 700);
+    *(vbool2_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool2_t v = *(vbool2_t*)(in + 900 + i);
+    *(vbool2_t*)(out + 900 + i) = v;
+  }
+}
+
+void f7 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vbool1_t v = *(vbool1_t*)(in + 500);
+    *(vbool1_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vbool1_t v = *(vbool1_t*)(in + 600);
+    *(vbool1_t*)(out + 600) = v;
+  } else {
+    vbool1_t v = *(vbool1_t*)(in + 700);
+    *(vbool1_t*)(out + 700) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool1_t v = *(vbool1_t*)(in + 900 + i);
+    *(vbool1_t*)(out + 900 + i) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O2" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O2" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O2" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O2" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O2" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O2" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O2" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 6 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O2" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O2" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c
new file mode 100644
index 0000000..2cf28d7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c
@@ -0,0 +1,167 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 500);
+    *(vint8mf8_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 600);
+    *(vint8mf8_t*)(out + 600) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 900 + i);
+    *(vint8mf8_t*)(out + 900 + i) = v;
+  }
+}
+
+void f2 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vint8mf4_t v = *(vint8mf4_t*)(in + 500);
+    *(vint8mf4_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vint8mf4_t v = *(vint8mf4_t*)(in + 600);
+    *(vint8mf4_t*)(out + 600) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf4_t v = *(vint8mf4_t*)(in + 900 + i);
+    *(vint8mf4_t*)(out + 900 + i) = v;
+  }
+}
+
+void f3 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vint8mf2_t v = *(vint8mf2_t*)(in + 500);
+    *(vint8mf2_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vint8mf2_t v = *(vint8mf2_t*)(in + 600);
+    *(vint8mf2_t*)(out + 600) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf2_t v = *(vint8mf2_t*)(in + 900 + i);
+    *(vint8mf2_t*)(out + 900 + i) = v;
+  }
+}
+
+void f4 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vint16mf4_t v = *(vint16mf4_t*)(in + 500);
+    *(vint16mf4_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vint16mf4_t v = *(vint16mf4_t*)(in + 600);
+    *(vint16mf4_t*)(out + 600) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint16mf4_t v = *(vint16mf4_t*)(in + 900 + i);
+    *(vint16mf4_t*)(out + 900 + i) = v;
+  }
+}
+
+void f5 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vint16mf2_t v = *(vint16mf2_t*)(in + 500);
+    *(vint16mf2_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vint16mf2_t v = *(vint16mf2_t*)(in + 600);
+    *(vint16mf2_t*)(out + 600) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint16mf2_t v = *(vint16mf2_t*)(in + 900 + i);
+    *(vint16mf2_t*)(out + 900 + i) = v;
+  }
+}
+
+void f6 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 500);
+    *(vint32mf2_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 600);
+    *(vint32mf2_t*)(out + 600) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 900 + i);
+    *(vint32mf2_t*)(out + 900 + i) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c
new file mode 100644
index 0000000..d52c1bb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c
@@ -0,0 +1,167 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 500);
+    *(vint8mf8_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 600);
+    *(vint8mf8_t*)(out + 600) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 900 + i);
+    *(vint8mf8_t*)(out + 900 + i) = v;
+  }
+}
+
+void f2 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vint8mf4_t v = *(vint8mf4_t*)(in + 500);
+    *(vint8mf4_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vint8mf4_t v = *(vint8mf4_t*)(in + 600);
+    *(vint8mf4_t*)(out + 600) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf4_t v = *(vint8mf4_t*)(in + 900 + i);
+    *(vint8mf4_t*)(out + 900 + i) = v;
+  }
+}
+
+void f3 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vint8mf2_t v = *(vint8mf2_t*)(in + 500);
+    *(vint8mf2_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vint8mf2_t v = *(vint8mf2_t*)(in + 600);
+    *(vint8mf2_t*)(out + 600) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf2_t v = *(vint8mf2_t*)(in + 900 + i);
+    *(vint8mf2_t*)(out + 900 + i) = v;
+  }
+}
+
+void f4 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vint16mf4_t v = *(vint16mf4_t*)(in + 500);
+    *(vint16mf4_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vint16mf4_t v = *(vint16mf4_t*)(in + 600);
+    *(vint16mf4_t*)(out + 600) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint16mf4_t v = *(vint16mf4_t*)(in + 900 + i);
+    *(vint16mf4_t*)(out + 900 + i) = v;
+  }
+}
+
+void f5 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vint16mf2_t v = *(vint16mf2_t*)(in + 500);
+    *(vint16mf2_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vint16mf2_t v = *(vint16mf2_t*)(in + 600);
+    *(vint16mf2_t*)(out + 600) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint16mf2_t v = *(vint16mf2_t*)(in + 900 + i);
+    *(vint16mf2_t*)(out + 900 + i) = v;
+  }
+}
+
+void f6 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vuint32mf2_t v = *(vuint32mf2_t*)(in + 500);
+    *(vuint32mf2_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vuint32mf2_t v = *(vuint32mf2_t*)(in + 600);
+    *(vuint32mf2_t*)(out + 600) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint32mf2_t v = *(vuint32mf2_t*)(in + 900 + i);
+    *(vuint32mf2_t*)(out + 900 + i) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c
new file mode 100644
index 0000000..bd6d68b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 500);
+    *(vfloat32mf2_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 600);
+    *(vfloat32mf2_t*)(out + 600) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 900 + i);
+    *(vfloat32mf2_t*)(out + 900 + i) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c
new file mode 100644
index 0000000..d3b3fa3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c
@@ -0,0 +1,194 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vbool64_t v = *(vbool64_t*)(in + 500);
+    *(vbool64_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vbool64_t v = *(vbool64_t*)(in + 600);
+    *(vbool64_t*)(out + 600) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool64_t v = *(vbool64_t*)(in + 900 + i);
+    *(vbool64_t*)(out + 900 + i) = v;
+  }
+}
+
+void f2 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vbool32_t v = *(vbool32_t*)(in + 500);
+    *(vbool32_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vbool32_t v = *(vbool32_t*)(in + 600);
+    *(vbool32_t*)(out + 600) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool32_t v = *(vbool32_t*)(in + 900 + i);
+    *(vbool32_t*)(out + 900 + i) = v;
+  }
+}
+
+void f3 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vbool16_t v = *(vbool16_t*)(in + 500);
+    *(vbool16_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vbool16_t v = *(vbool16_t*)(in + 600);
+    *(vbool16_t*)(out + 600) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool16_t v = *(vbool16_t*)(in + 900 + i);
+    *(vbool16_t*)(out + 900 + i) = v;
+  }
+}
+
+void f4 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vbool8_t v = *(vbool8_t*)(in + 500);
+    *(vbool8_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vbool8_t v = *(vbool8_t*)(in + 600);
+    *(vbool8_t*)(out + 600) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool8_t v = *(vbool8_t*)(in + 900 + i);
+    *(vbool8_t*)(out + 900 + i) = v;
+  }
+}
+
+void f5 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vbool4_t v = *(vbool4_t*)(in + 500);
+    *(vbool4_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vbool4_t v = *(vbool4_t*)(in + 600);
+    *(vbool4_t*)(out + 600) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool4_t v = *(vbool4_t*)(in + 900 + i);
+    *(vbool4_t*)(out + 900 + i) = v;
+  }
+}
+
+void f6 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vbool2_t v = *(vbool2_t*)(in + 500);
+    *(vbool2_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vbool2_t v = *(vbool2_t*)(in + 600);
+    *(vbool2_t*)(out + 600) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool2_t v = *(vbool2_t*)(in + 900 + i);
+    *(vbool2_t*)(out + 900 + i) = v;
+  }
+}
+
+void f7 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  if (n == 0) {
+    vbool1_t v = *(vbool1_t*)(in + 500);
+    *(vbool1_t*)(out + 500) = v;
+  } else if (n == 1) {
+    vbool1_t v = *(vbool1_t*)(in + 600);
+    *(vbool1_t*)(out + 600) = v;
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool1_t v = *(vbool1_t*)(in + 900 + i);
+    *(vbool1_t*)(out + 900 + i) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+\.L[0-9][0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c
new file mode 100644
index 0000000..e1c5609
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c
@@ -0,0 +1,230 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vint8mf8_t v = *(vint8mf8_t*)(in + 500);
+    *(vint8mf8_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vint8mf8_t v = *(vint8mf8_t*)(in + 500);
+    *(vint8mf8_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    vint8mf8_t v = *(vint8mf8_t*)(in + 700);
+    *(vint8mf8_t*)(out + 700) = v;
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 900 + i);
+    *(vint8mf8_t*)(out + 900 + i) = v;
+  }
+}
+
+void f2 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vint8mf4_t v = *(vint8mf4_t*)(in + 500);
+    *(vint8mf4_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vint8mf4_t v = *(vint8mf4_t*)(in + 500);
+    *(vint8mf4_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    vint8mf4_t v = *(vint8mf4_t*)(in + 700);
+    *(vint8mf4_t*)(out + 700) = v;
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf4_t v = *(vint8mf4_t*)(in + 900 + i);
+    *(vint8mf4_t*)(out + 900 + i) = v;
+  }
+}
+
+void f3 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vint8mf2_t v = *(vint8mf2_t*)(in + 500);
+    *(vint8mf2_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vint8mf2_t v = *(vint8mf2_t*)(in + 500);
+    *(vint8mf2_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    vint8mf2_t v = *(vint8mf2_t*)(in + 700);
+    *(vint8mf2_t*)(out + 700) = v;
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf2_t v = *(vint8mf2_t*)(in + 900 + i);
+    *(vint8mf2_t*)(out + 900 + i) = v;
+  }
+}
+
+void f4 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vint16mf4_t v = *(vint16mf4_t*)(in + 500);
+    *(vint16mf4_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vint16mf4_t v = *(vint16mf4_t*)(in + 500);
+    *(vint16mf4_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    vint16mf4_t v = *(vint16mf4_t*)(in + 700);
+    *(vint16mf4_t*)(out + 700) = v;
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint16mf4_t v = *(vint16mf4_t*)(in + 900 + i);
+    *(vint16mf4_t*)(out + 900 + i) = v;
+  }
+}
+
+void f5 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vint16mf2_t v = *(vint16mf2_t*)(in + 500);
+    *(vint16mf2_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vint16mf2_t v = *(vint16mf2_t*)(in + 500);
+    *(vint16mf2_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    vint16mf2_t v = *(vint16mf2_t*)(in + 700);
+    *(vint16mf2_t*)(out + 700) = v;
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint16mf2_t v = *(vint16mf2_t*)(in + 900 + i);
+    *(vint16mf2_t*)(out + 900 + i) = v;
+  }
+}
+
+void f6 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  switch (n)
+  {
+  case 0:{
+    vint32mf2_t v = *(vint32mf2_t*)(in + 500);
+    *(vint32mf2_t*)(out + 500) = v;
+    break;
+  }
+  case 1:{
+    vint32mf2_t v = *(vint32mf2_t*)(in + 500);
+    *(vint32mf2_t*)(out + 500) = v;
+    break;
+  }
+  default:{
+    vint32mf2_t v = *(vint32mf2_t*)(in + 700);
+    *(vint32mf2_t*)(out + 700) = v;
+    break;
+  }
+  }
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 900 + i);
+    *(vint32mf2_t*)(out + 900 + i) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9][0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-O1" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c
new file mode 100644
index 0000000..89b6abe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c
@@ -0,0 +1,239 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void fn3 (void);
+
+void f (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool64_t v = *(vbool64_t*)(in + 900 + i);
+    *(vbool64_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool64_t v = *(vbool64_t*)(in + 900 + i);
+    *(vbool64_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool64_t v = *(vbool64_t*)(in + 900 + i);
+    *(vbool64_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool64_t v = *(vbool64_t*)(in + 900 + i);
+    *(vbool64_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool64_t v = *(vbool64_t*)(in + 900 + i);
+    *(vbool64_t*)(out + 900 + i) = v;
+  }
+
+}
+
+int f2 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool32_t v = *(vbool32_t*)(in + 900 + i);
+    *(vbool32_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool32_t v = *(vbool32_t*)(in + 900 + i);
+    *(vbool32_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool32_t v = *(vbool32_t*)(in + 900 + i);
+    *(vbool32_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool32_t v = *(vbool32_t*)(in + 900 + i);
+    *(vbool32_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool32_t v = *(vbool32_t*)(in + 900 + i);
+    *(vbool32_t*)(out + 900 + i) = v;
+  }
+
+}
+
+int f3 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool16_t v = *(vbool16_t*)(in + 900 + i);
+    *(vbool16_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool16_t v = *(vbool16_t*)(in + 900 + i);
+    *(vbool16_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool16_t v = *(vbool16_t*)(in + 900 + i);
+    *(vbool16_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool16_t v = *(vbool16_t*)(in + 900 + i);
+    *(vbool16_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool16_t v = *(vbool16_t*)(in + 900 + i);
+    *(vbool16_t*)(out + 900 + i) = v;
+  }
+
+}
+
+int f4 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool8_t v = *(vbool8_t*)(in + 900 + i);
+    *(vbool8_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool8_t v = *(vbool8_t*)(in + 900 + i);
+    *(vbool8_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool8_t v = *(vbool8_t*)(in + 900 + i);
+    *(vbool8_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool8_t v = *(vbool8_t*)(in + 900 + i);
+    *(vbool8_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool8_t v = *(vbool8_t*)(in + 900 + i);
+    *(vbool8_t*)(out + 900 + i) = v;
+  }
+
+}
+
+int f5 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool4_t v = *(vbool4_t*)(in + 900 + i);
+    *(vbool4_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool4_t v = *(vbool4_t*)(in + 900 + i);
+    *(vbool4_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool4_t v = *(vbool4_t*)(in + 900 + i);
+    *(vbool4_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool4_t v = *(vbool4_t*)(in + 900 + i);
+    *(vbool4_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool4_t v = *(vbool4_t*)(in + 900 + i);
+    *(vbool4_t*)(out + 900 + i) = v;
+  }
+
+}
+
+int f6 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool2_t v = *(vbool2_t*)(in + 900 + i);
+    *(vbool2_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool2_t v = *(vbool2_t*)(in + 900 + i);
+    *(vbool2_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool2_t v = *(vbool2_t*)(in + 900 + i);
+    *(vbool2_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool2_t v = *(vbool2_t*)(in + 900 + i);
+    *(vbool2_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool2_t v = *(vbool2_t*)(in + 900 + i);
+    *(vbool2_t*)(out + 900 + i) = v;
+  }
+
+}
+
+int f7 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool1_t v = *(vbool1_t*)(in + 900 + i);
+    *(vbool1_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool1_t v = *(vbool1_t*)(in + 900 + i);
+    *(vbool1_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool1_t v = *(vbool1_t*)(in + 900 + i);
+    *(vbool1_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool1_t v = *(vbool1_t*)(in + 900 + i);
+    *(vbool1_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vbool1_t v = *(vbool1_t*)(in + 900 + i);
+    *(vbool1_t*)(out + 900 + i) = v;
+  }
+
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+\.L[0-9][0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c
new file mode 100644
index 0000000..930f6f8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c
@@ -0,0 +1,207 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void fn3 (void);
+
+void f (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 900 + i);
+    *(vint8mf8_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 900 + i);
+    *(vint8mf8_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 900 + i);
+    *(vint8mf8_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 900 + i);
+    *(vint8mf8_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*)(in + 900 + i);
+    *(vint8mf8_t*)(out + 900 + i) = v;
+  }
+
+}
+
+void f2 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf4_t v = *(vint8mf4_t*)(in + 900 + i);
+    *(vint8mf4_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf4_t v = *(vint8mf4_t*)(in + 900 + i);
+    *(vint8mf4_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf4_t v = *(vint8mf4_t*)(in + 900 + i);
+    *(vint8mf4_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf4_t v = *(vint8mf4_t*)(in + 900 + i);
+    *(vint8mf4_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf4_t v = *(vint8mf4_t*)(in + 900 + i);
+    *(vint8mf4_t*)(out + 900 + i) = v;
+  }
+
+}
+
+void f3 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf2_t v = *(vint8mf2_t*)(in + 900 + i);
+    *(vint8mf2_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf2_t v = *(vint8mf2_t*)(in + 900 + i);
+    *(vint8mf2_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf2_t v = *(vint8mf2_t*)(in + 900 + i);
+    *(vint8mf2_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf2_t v = *(vint8mf2_t*)(in + 900 + i);
+    *(vint8mf2_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint8mf2_t v = *(vint8mf2_t*)(in + 900 + i);
+    *(vint8mf2_t*)(out + 900 + i) = v;
+  }
+
+}
+
+void f4 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint16mf4_t v = *(vint16mf4_t*)(in + 900 + i);
+    *(vint16mf4_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint16mf4_t v = *(vint16mf4_t*)(in + 900 + i);
+    *(vint16mf4_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint16mf4_t v = *(vint16mf4_t*)(in + 900 + i);
+    *(vint16mf4_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint16mf4_t v = *(vint16mf4_t*)(in + 900 + i);
+    *(vint16mf4_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint16mf4_t v = *(vint16mf4_t*)(in + 900 + i);
+    *(vint16mf4_t*)(out + 900 + i) = v;
+  }
+
+}
+
+void f5 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint16mf2_t v = *(vint16mf2_t*)(in + 900 + i);
+    *(vint16mf2_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint16mf2_t v = *(vint16mf2_t*)(in + 900 + i);
+    *(vint16mf2_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint16mf2_t v = *(vint16mf2_t*)(in + 900 + i);
+    *(vint16mf2_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint16mf2_t v = *(vint16mf2_t*)(in + 900 + i);
+    *(vint16mf2_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint16mf2_t v = *(vint16mf2_t*)(in + 900 + i);
+    *(vint16mf2_t*)(out + 900 + i) = v;
+  }
+
+}
+
+void f6 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 900 + i);
+    *(vint32mf2_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 900 + i);
+    *(vint32mf2_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 900 + i);
+    *(vint32mf2_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 900 + i);
+    *(vint32mf2_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vint32mf2_t v = *(vint32mf2_t*)(in + 900 + i);
+    *(vint32mf2_t*)(out + 900 + i) = v;
+  }
+
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c
new file mode 100644
index 0000000..e8b92e0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c
@@ -0,0 +1,207 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void fn3 (void);
+
+void f (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 900 + i);
+    *(vuint8mf8_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 900 + i);
+    *(vuint8mf8_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 900 + i);
+    *(vuint8mf8_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 900 + i);
+    *(vuint8mf8_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 900 + i);
+    *(vuint8mf8_t*)(out + 900 + i) = v;
+  }
+
+}
+
+void f2 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint8mf4_t v = *(vuint8mf4_t*)(in + 900 + i);
+    *(vuint8mf4_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint8mf4_t v = *(vuint8mf4_t*)(in + 900 + i);
+    *(vuint8mf4_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint8mf4_t v = *(vuint8mf4_t*)(in + 900 + i);
+    *(vuint8mf4_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint8mf4_t v = *(vuint8mf4_t*)(in + 900 + i);
+    *(vuint8mf4_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint8mf4_t v = *(vuint8mf4_t*)(in + 900 + i);
+    *(vuint8mf4_t*)(out + 900 + i) = v;
+  }
+
+}
+
+void f3 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint8mf2_t v = *(vuint8mf2_t*)(in + 900 + i);
+    *(vuint8mf2_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint8mf2_t v = *(vuint8mf2_t*)(in + 900 + i);
+    *(vuint8mf2_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint8mf2_t v = *(vuint8mf2_t*)(in + 900 + i);
+    *(vuint8mf2_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint8mf2_t v = *(vuint8mf2_t*)(in + 900 + i);
+    *(vuint8mf2_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint8mf2_t v = *(vuint8mf2_t*)(in + 900 + i);
+    *(vuint8mf2_t*)(out + 900 + i) = v;
+  }
+
+}
+
+void f4 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint16mf4_t v = *(vuint16mf4_t*)(in + 900 + i);
+    *(vuint16mf4_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint16mf4_t v = *(vuint16mf4_t*)(in + 900 + i);
+    *(vuint16mf4_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint16mf4_t v = *(vuint16mf4_t*)(in + 900 + i);
+    *(vuint16mf4_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint16mf4_t v = *(vuint16mf4_t*)(in + 900 + i);
+    *(vuint16mf4_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint16mf4_t v = *(vuint16mf4_t*)(in + 900 + i);
+    *(vuint16mf4_t*)(out + 900 + i) = v;
+  }
+
+}
+
+void f5 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint16mf2_t v = *(vuint16mf2_t*)(in + 900 + i);
+    *(vuint16mf2_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint16mf2_t v = *(vuint16mf2_t*)(in + 900 + i);
+    *(vuint16mf2_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint16mf2_t v = *(vuint16mf2_t*)(in + 900 + i);
+    *(vuint16mf2_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint16mf2_t v = *(vuint16mf2_t*)(in + 900 + i);
+    *(vuint16mf2_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint16mf2_t v = *(vuint16mf2_t*)(in + 900 + i);
+    *(vuint16mf2_t*)(out + 900 + i) = v;
+  }
+
+}
+
+void f6 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint32mf2_t v = *(vuint32mf2_t*)(in + 900 + i);
+    *(vuint32mf2_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint32mf2_t v = *(vuint32mf2_t*)(in + 900 + i);
+    *(vuint32mf2_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint32mf2_t v = *(vuint32mf2_t*)(in + 900 + i);
+    *(vuint32mf2_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint32mf2_t v = *(vuint32mf2_t*)(in + 900 + i);
+    *(vuint32mf2_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vuint32mf2_t v = *(vuint32mf2_t*)(in + 900 + i);
+    *(vuint32mf2_t*)(out + 900 + i) = v;
+  }
+
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-4.c
new file mode 100644
index 0000000..27f11a8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-4.c
@@ -0,0 +1,39 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void fn3 (void);
+
+void f6 (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 900 + i);
+    *(vfloat32mf2_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 900 + i);
+    *(vfloat32mf2_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 900 + i);
+    *(vfloat32mf2_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 900 + i);
+    *(vfloat32mf2_t*)(out + 900 + i) = v;
+  }
+  fn3 ();
+  for (int i = 0 ; i < n * n * n * n; i++) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 900 + i);
+    *(vfloat32mf2_t*)(out + 900 + i) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 5 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c
new file mode 100644
index 0000000..c5962e5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c
@@ -0,0 +1,52 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int32_t * restrict in, int32_t * restrict out, size_t n, size_t m, int cond)
+{
+  for (size_t i = 0; i < n; i++)
+    {
+      if (i % 2) {
+        
+        if (cond) {
+          vfloat32mf2_t v = *(vfloat32mf2_t*)(in + i + 2000);
+          *(vfloat32mf2_t*)out = v;
+        } else {
+          vfloat32mf2_t v = *(vfloat32mf2_t*)(in + i + 3000);
+          *(vfloat32mf2_t*)out = v;
+        }
+        
+        for (size_t j = 0; j < m; j += 1) {
+          if (j % 2 == 0) {
+            vint8mf8_t v = *(vint8mf8_t*)(in + i + j + 100);
+            *(vint8mf8_t*)out = v;
+          } else {
+            vint8mf8_t v = *(vint8mf8_t*)(in + i + j + 200);
+            *(vint8mf8_t*)out = v;
+          }
+        }
+        
+        if (cond) {
+          vuint16mf4_t v = *(vuint16mf4_t*)(in + i + 7000);
+          *(vuint16mf4_t*)out = v;
+        } else {
+          vuint16mf4_t v = *(vuint16mf4_t*)(in + i + 8000);
+          *(vuint16mf4_t*)out = v;
+        }
+      } else {
+        if (cond) {
+          vint8mf8_t v = *(vint8mf8_t*)(in + i + 4000);
+          *(vint8mf8_t*)out = v;
+        } else {
+          vint8mf8_t v = *(vint8mf8_t*)(in + i + 5000);
+          *(vint8mf8_t*)out = v;
+        }
+        
+        vbool64_t v = *(vbool64_t*)(in + i + 300);
+        *(vbool64_t*)out = v;
+      }
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.c
new file mode 100644
index 0000000..8fa2bd8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.c
@@ -0,0 +1,56 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int32_t * restrict in, int32_t * restrict out, size_t n, size_t m, int cond)
+{
+  for (size_t i = 0; i < n; i++)
+    {
+      if (i % 2) {
+        
+        if (cond) {
+          vfloat32mf2_t v = *(vfloat32mf2_t*)(in + i + 2000);
+          *(vfloat32mf2_t*)(out + i + 2000) = v;
+        } else {
+          vfloat32mf2_t v = *(vfloat32mf2_t*)(in + i + 3000);
+          *(vfloat32mf2_t*)(out + i + 3000) = v;
+        }
+        
+        for (size_t j = 0; j < m; j += 1) {
+          if (j % 2 == 0) {
+            vint8mf8_t v = *(vint8mf8_t*)(in + i + j + 100);
+            *(vint8mf8_t*)(out + i + j + 100) = v;
+          } else {
+            vint8mf8_t v = *(vint8mf8_t*)(in + i + j + 200);
+            *(vint8mf8_t*)(out + i + j + 200) = v;
+          }
+        }
+        
+        if (cond) {
+          vuint16mf4_t v = *(vuint16mf4_t*)(in + i + 7000);
+          *(vuint16mf4_t*)(out + i + 7000) = v;
+        } else {
+          vuint16mf4_t v = *(vuint16mf4_t*)(in + i + 8000);
+          *(vuint16mf4_t*)(out + i + 8000) = v;
+        }
+      } else {
+        if (cond) {
+          vuint16mf2_t v = *(vuint16mf2_t*)(in + i + 4000);
+          *(vuint16mf2_t*)(out + i + 4000) = v;
+        } else {
+          vuint16mf2_t v = *(vuint16mf2_t*)(in + i + 5000);
+          *(vuint16mf2_t*)(out + i + 5000) = v;
+        }
+        
+        vbool1_t v = *(vbool1_t*)(in + i + 300);
+        *(vbool1_t*)(out + i + 300) = v;
+      }
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 5 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-not {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c
new file mode 100644
index 0000000..34ac4a5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int32_t * restrict in, int32_t * restrict out, size_t n, size_t cond, size_t cond2)
+{
+  for (size_t i = 0; i < n; i++)
+    {
+      if (i != cond) {
+        vint8mf8_t v = *(vint8mf8_t*)(in + i + 100);
+        *(vint8mf8_t*)(out + i + 100) = v;
+      } else {
+        vbool1_t v = *(vbool1_t*)(in + i + 400);
+        *(vbool1_t*)(out + i + 400) = v;
+      }
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {\.L[0-9]+:\s+vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]+} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+j\s+\.L[0-9]+} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.c
new file mode 100644
index 0000000..697b093
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int32_t * restrict in, int32_t * restrict out, size_t n, size_t m, size_t cond, size_t cond2)
+{
+  for (size_t i = 0; i < n; i++)
+    {
+      if (i != cond) {
+        vbool16_t v = *(vbool16_t*)(in + i + 400);
+        *(vbool16_t*)(out + i + 400) = v;
+        for (int j = 0; j < m; j++) {
+          vuint8mf2_t v = *(vuint8mf2_t*)(in + i + 100 + j);
+          *(vuint8mf2_t*)(out + i + 100 + j) = v;
+        }
+      } else if (i == cond2) {
+        vuint16mf2_t v = *(vuint16mf2_t*)(in + i + 200);
+        *(vuint16mf2_t*)(out + i + 200) = v;
+      } else {
+        vint8mf8_t v = *(vint8mf8_t*)(in + i + 100);
+        *(vint8mf8_t*)(out + i + 100) = v;
+      }
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 5 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c
new file mode 100644
index 0000000..1dab5ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int32_t * restrict in, int32_t * restrict out, size_t n, size_t m, size_t cond, size_t cond2)
+{
+  for (int i = 0; i < n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*) (in + i + 1);
+    *(vint8mf8_t*) (out + i + 1) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat32mf2_t v = *(vfloat32mf2_t*) (in + i + 2);
+    *(vfloat32mf2_t*) (out + i + 2) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat32mf2_t v;
+    *(vfloat32mf2_t*) (out + i + 3) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c
new file mode 100644
index 0000000..38828bc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c
@@ -0,0 +1,39 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f2 (int32_t * restrict in, int32_t * restrict in2, int32_t * restrict out, int32_t * restrict out2, size_t n, size_t m, size_t cond, size_t cond2)
+{
+  for (int i = 0; i < n; i++){
+    out2[i] = in2[i] + out[i];
+  }
+  for (int i = 0; i < n; i++){
+    out[i] = in[i] & out2[i];
+  }
+  for (int i = 0; i < n; i++){
+    out2[i] = out[i] * out2[i];
+  }
+  for (size_t i = 0; i < n; i++)
+    {
+      if (i > cond) {
+        if (cond2) {
+          for (int j = 0; j < m; j++) {
+            vint8mf8_t v2 = *(vint8mf8_t*)(in2 + i + 100 + j);
+            *(vint8mf8_t*)(out2 + i + 100 + j) = v2;
+          }
+        } else {
+          for (int j = 0; j < m; j++) {
+            vfloat32mf2_t v3 = *(vfloat32mf2_t*)(in2 + i + 300 + j);
+            *(vfloat32mf2_t*)(out2 + i + 100 + j) = v3;
+          }
+        }
+      } else {
+        vbool64_t v = *(vbool64_t*)(in + i + 400);
+        *(vbool64_t*)(out + i + 400) = v;
+      }
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c
new file mode 100644
index 0000000..cd01c9f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int32_t * restrict in, int32_t * restrict out, size_t n, size_t cond, size_t cond2)
+{
+  for (size_t i = 0; i < n; i++)
+    {
+      if (i == cond) {
+        vint8mf8_t v = *(vint8mf8_t*)(in + i + 100);
+        *(vint8mf8_t*)(out + i + 100) = v;
+      } else {
+        vbool1_t v = *(vbool1_t*)(in + i + 400);
+        *(vbool1_t*)(out + i + 400) = v;
+      }
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+\.L[0-9]+} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+j\s+\.L[0-9]+} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c
new file mode 100644
index 0000000..d79e83a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f2 (int32_t * restrict in, int32_t * restrict in2, int32_t * restrict out, int32_t * restrict out2, size_t n, size_t m, size_t cond, size_t cond2)
+{
+  for (size_t i = 0; i < n; i++)
+    {
+      if (i > cond) {
+        if (cond2) {
+          for (int j = 0; j < m; j++) {
+            vint8mf8_t v2 = *(vint8mf8_t*)(in2 + i + 100 + j);
+            *(vint8mf8_t*)(out2 + i + 100 + j) = v2;
+          }
+        } else {
+          for (int j = 0; j < m; j++) {
+            vfloat32mf2_t v3 = *(vfloat32mf2_t*)(in2 + i + 300 + j);
+            *(vfloat32mf2_t*)(out2 + i + 100 + j) = v3;
+          }
+        }
+      } else {
+        vbool64_t v = *(vbool64_t*)(in + i + 400);
+        *(vbool64_t*)(out + i + 400) = v;
+      }
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c
new file mode 100644
index 0000000..44bd4d8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int32_t * restrict in, int32_t * restrict out, size_t n, size_t cond, size_t cond2)
+{
+  for (size_t i = 0; i < n; i++)
+    {
+      if (i == cond) {
+        vint8mf8_t v = *(vint8mf8_t*)(in + i + 100);
+        *(vint8mf8_t*)(out + i + 100) = v;
+      } else if (i == cond2) {
+        vfloat32mf2_t v = *(vfloat32mf2_t*)(in + i + 200);
+        *(vfloat32mf2_t*)(out + i + 200) = v;
+      } else {
+        vbool1_t v = *(vbool1_t*)(in + i + 400);
+        *(vbool1_t*)(out + i + 400) = v;
+      }
+    }
+}
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+\.L[0-9]:+} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 5 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c
new file mode 100644
index 0000000..12f40f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int32_t * restrict in, int32_t * restrict out, size_t n, size_t cond, size_t cond2)
+{
+  for (size_t i = 0; i < n; i++)
+    {
+      if (i == cond) {
+        vint8mf8_t v = *(vint8mf8_t*)(in + i + 100);
+        *(vint8mf8_t*)(out + i + 100) = v;
+      } else if (i == cond2) {
+        vfloat32mf2_t v = *(vfloat32mf2_t*)(in + i + 200);
+        *(vfloat32mf2_t*)(out + i + 200) = v;
+      } else if (i == (cond2 - 1)) {
+        vuint16mf2_t v = *(vuint16mf2_t*)(in + i + 300);
+        *(vuint16mf2_t*)(out + i + 300) = v;
+      } else {
+        vbool1_t v = *(vbool1_t*)(in + i + 400);
+        *(vbool1_t*)(out + i + 400) = v;
+      }
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+\.L[0-9]:+} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 7 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c
new file mode 100644
index 0000000..217ce11
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int32_t * in, int32_t * out, int n, int cond)
+{
+  if (cond) {
+    vint32mf2_t v = *(vint32mf2_t*) (in + 100);
+    *(vint32mf2_t*) (out + 100) = v;
+  } else {
+    vint16mf2_t v = *(vint16mf2_t*) (in + 200);
+    *(vint16mf2_t*) (out + 200) = v;
+  }
+  
+  for (int i = 0; i < n; i++) {
+    vint8mf8_t v = *(vint8mf8_t*) (in + 300 + i);
+    *(vint8mf8_t*) (out + 300 + i) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {\.L[0-9]+:\s+vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]+:} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {\.L[0-9]+:\s+vle8\.v} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c
new file mode 100644
index 0000000..05058b8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int32_t * restrict in, int32_t * restrict out, size_t n, size_t cond, size_t cond2)
+{
+  for (size_t i = 0; i < n; i++)
+    {
+      if (i != cond) {
+        vbool1_t v = *(vbool1_t*)(in + i + 400);
+        *(vbool1_t*)(out + i + 400) = v;
+      } else if (i == cond2) {
+        vfloat32mf2_t v = *(vfloat32mf2_t*)(in + i + 200);
+        *(vfloat32mf2_t*)(out + i + 200) = v;
+      } else {
+        vint8mf8_t v = *(vint8mf8_t*)(in + i + 100);
+        *(vint8mf8_t*)(out + i + 100) = v;
+      }
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 4 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {j\s+\.L[0-9]+\s+\.L[0-9]+:\s+vlm\.v} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c
new file mode 100644
index 0000000..79a02e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int32_t * restrict in, int32_t * restrict out, size_t n, size_t cond, size_t cond2)
+{
+  for (size_t i = 0; i < n; i++)
+    {
+      if (i != cond) {
+        vbool1_t v = *(vbool1_t*)(in + i + 400);
+        *(vbool1_t*)(out + i + 400) = v;
+      } else if (i == cond2) {
+        vuint16mf2_t v = *(vuint16mf2_t*)(in + i + 200);
+        *(vuint16mf2_t*)(out + i + 200) = v;
+      } else {
+        vint8mf8_t v = *(vint8mf8_t*)(in + i + 100);
+        *(vint8mf8_t*)(out + i + 100) = v;
+      }
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 5 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {j\s+\.L[0-9]+\s+\.L[0-9]+:\s+vlm\.v} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c
new file mode 100644
index 0000000..bd6d552
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void f (int32_t * restrict in, int32_t * restrict out, size_t n, size_t m, size_t cond, size_t cond2)
+{
+  for (size_t i = 0; i < n; i++)
+    {
+      if (i != cond) {
+        vbool1_t v = *(vbool1_t*)(in + i + 400);
+        *(vbool1_t*)(out + i + 400) = v;
+        for (int j = 0; j < m; j++) {
+          vint32mf2_t v = *(vint32mf2_t*)(in + i + 100 + j);
+          *(vint32mf2_t*)(out + i + 100 + j) = v;
+        }
+      } else if (i == cond2) {
+        vuint16mf2_t v = *(vuint16mf2_t*)(in + i + 200);
+        *(vuint16mf2_t*)(out + i + 200) = v;
+      } else {
+        vint8mf8_t v = *(vint8mf8_t*)(in + i + 100);
+        *(vint8mf8_t*)(out + i + 100) = v;
+      }
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 7 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c
new file mode 100644
index 0000000..db5f64f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vint8mf8_t v = *(vint8mf8_t*)(in + 100);
+      *(vint8mf8_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vint8mf8_t v = *(vint8mf8_t*)(in + 200);
+      *(vint8mf8_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vint8mf8_t v = *(vint8mf8_t*)(in + 300);
+      *(vint8mf8_t*)(out + 300) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf8_t v = *(vint8mf8_t*)(in + i);
+      *(vint8mf8_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c
new file mode 100644
index 0000000..d5c108c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vuint16mf2_t v = *(vuint16mf2_t*)(in + 100);
+      *(vuint16mf2_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vuint16mf2_t v = *(vuint16mf2_t*)(in + 200);
+      *(vuint16mf2_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vuint16mf2_t v = *(vuint16mf2_t*)(in + 300);
+      *(vuint16mf2_t*)(out + 300) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vuint16mf2_t v = *(vuint16mf2_t*)(in + i);
+      *(vuint16mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c
new file mode 100644
index 0000000..2c8e0ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vint32mf2_t v = *(vint32mf2_t*)(in + 100);
+      *(vint32mf2_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vint32mf2_t v = *(vint32mf2_t*)(in + 200);
+      *(vint32mf2_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vint32mf2_t v = *(vint32mf2_t*)(in + 300);
+      *(vint32mf2_t*)(out + 300) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vint32mf2_t v = *(vint32mf2_t*)(in + i);
+      *(vint32mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c
new file mode 100644
index 0000000..50807ad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vuint32mf2_t v = *(vuint32mf2_t*)(in + 100);
+      *(vuint32mf2_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vuint32mf2_t v = *(vuint32mf2_t*)(in + 200);
+      *(vuint32mf2_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vuint32mf2_t v = *(vuint32mf2_t*)(in + 300);
+      *(vuint32mf2_t*)(out + 300) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vuint32mf2_t v = *(vuint32mf2_t*)(in + i);
+      *(vuint32mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c
new file mode 100644
index 0000000..b9e0d20
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 100);
+      *(vfloat32mf2_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 200);
+      *(vfloat32mf2_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 300);
+      *(vfloat32mf2_t*)(out + 300) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vfloat32mf2_t v = *(vfloat32mf2_t*)(in + i);
+      *(vfloat32mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c
new file mode 100644
index 0000000..efe51b2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c
@@ -0,0 +1,189 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vbool64_t v = *(vbool64_t*)(in + 100);
+      *(vbool64_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vbool64_t v = *(vbool64_t*)(in + 200);
+      *(vbool64_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vbool64_t v = *(vbool64_t*)(in + 300);
+      *(vbool64_t*)(out + 300) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vbool64_t v = *(vbool64_t*)(in + i);
+      *(vbool64_t*)(out + i) = v;
+    }
+}
+
+void f2 (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vbool32_t v = *(vbool32_t*)(in + 100);
+      *(vbool32_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vbool32_t v = *(vbool32_t*)(in + 200);
+      *(vbool32_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vbool32_t v = *(vbool32_t*)(in + 300);
+      *(vbool32_t*)(out + 300) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vbool32_t v = *(vbool32_t*)(in + i);
+      *(vbool32_t*)(out + i) = v;
+    }
+}
+
+void f3 (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vbool16_t v = *(vbool16_t*)(in + 100);
+      *(vbool16_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vbool16_t v = *(vbool16_t*)(in + 200);
+      *(vbool16_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vbool16_t v = *(vbool16_t*)(in + 300);
+      *(vbool16_t*)(out + 300) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vbool16_t v = *(vbool16_t*)(in + i);
+      *(vbool16_t*)(out + i) = v;
+    }
+}
+
+void f4 (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vbool8_t v = *(vbool8_t*)(in + 100);
+      *(vbool8_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vbool8_t v = *(vbool8_t*)(in + 200);
+      *(vbool8_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vbool8_t v = *(vbool8_t*)(in + 300);
+      *(vbool8_t*)(out + 300) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vbool8_t v = *(vbool8_t*)(in + i);
+      *(vbool8_t*)(out + i) = v;
+    }
+}
+
+void f5 (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vbool4_t v = *(vbool4_t*)(in + 100);
+      *(vbool4_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vbool4_t v = *(vbool4_t*)(in + 200);
+      *(vbool4_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vbool4_t v = *(vbool4_t*)(in + 300);
+      *(vbool4_t*)(out + 300) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vbool4_t v = *(vbool4_t*)(in + i);
+      *(vbool4_t*)(out + i) = v;
+    }
+}
+
+void f6 (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vbool2_t v = *(vbool2_t*)(in + 100);
+      *(vbool2_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vbool2_t v = *(vbool2_t*)(in + 200);
+      *(vbool2_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vbool2_t v = *(vbool2_t*)(in + 300);
+      *(vbool2_t*)(out + 300) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vbool2_t v = *(vbool2_t*)(in + i);
+      *(vbool2_t*)(out + i) = v;
+    }
+}
+
+void f7 (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vbool1_t v = *(vbool1_t*)(in + 100);
+      *(vbool1_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vbool1_t v = *(vbool1_t*)(in + 200);
+      *(vbool1_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vbool1_t v = *(vbool1_t*)(in + 300);
+      *(vbool1_t*)(out + 300) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vbool1_t v = *(vbool1_t*)(in + i);
+      *(vbool1_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c
new file mode 100644
index 0000000..3d4568e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vint8mf8_t v = *(vint8mf8_t*)(in + 100);
+    *(vint8mf8_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vint8mf8_t v = *(vint8mf8_t*)(in + 200);
+    *(vint8mf8_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vint8mf8_t v = *(vint8mf8_t*)(in + 300);
+    *(vint8mf8_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf8_t v = *(vint8mf8_t*)(in + i);
+      *(vint8mf8_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c
new file mode 100644
index 0000000..1b70c90
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 100);
+    *(vuint8mf8_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 200);
+    *(vuint8mf8_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 300);
+    *(vuint8mf8_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vuint8mf8_t v = *(vuint8mf8_t*)(in + i);
+      *(vuint8mf8_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c
new file mode 100644
index 0000000..b32b561
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vint8mf4_t v = *(vint8mf4_t*)(in + 100);
+    *(vint8mf4_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vint8mf4_t v = *(vint8mf4_t*)(in + 200);
+    *(vint8mf4_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vint8mf4_t v = *(vint8mf4_t*)(in + 300);
+    *(vint8mf4_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf4_t v = *(vint8mf4_t*)(in + i);
+      *(vint8mf4_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c
new file mode 100644
index 0000000..bbbf40f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vuint8mf4_t v = *(vuint8mf4_t*)(in + 100);
+    *(vuint8mf4_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vuint8mf4_t v = *(vuint8mf4_t*)(in + 200);
+    *(vuint8mf4_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vuint8mf4_t v = *(vuint8mf4_t*)(in + 300);
+    *(vuint8mf4_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vuint8mf4_t v = *(vuint8mf4_t*)(in + i);
+      *(vuint8mf4_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c
new file mode 100644
index 0000000..36197ff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vint8mf2_t v = *(vint8mf2_t*)(in + 100);
+    *(vint8mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vint8mf2_t v = *(vint8mf2_t*)(in + 200);
+    *(vint8mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vint8mf2_t v = *(vint8mf2_t*)(in + 300);
+    *(vint8mf2_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf2_t v = *(vint8mf2_t*)(in + i);
+      *(vint8mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c
new file mode 100644
index 0000000..ab6c1b1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vuint8mf8_t v = *(vuint8mf8_t*)(in + 100);
+      *(vuint8mf8_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vuint8mf8_t v = *(vuint8mf8_t*)(in + 200);
+      *(vuint8mf8_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vuint8mf8_t v = *(vuint8mf8_t*)(in + 300);
+      *(vuint8mf8_t*)(out + 300) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vuint8mf8_t v = *(vuint8mf8_t*)(in + i);
+      *(vuint8mf8_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c
new file mode 100644
index 0000000..4d5d55c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vuint8mf2_t v = *(vuint8mf2_t*)(in + 100);
+    *(vuint8mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vuint8mf2_t v = *(vuint8mf2_t*)(in + 200);
+    *(vuint8mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vuint8mf2_t v = *(vuint8mf2_t*)(in + 300);
+    *(vuint8mf2_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vuint8mf2_t v = *(vuint8mf2_t*)(in + i);
+      *(vuint8mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c
new file mode 100644
index 0000000..87e34bc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vint16mf4_t v = *(vint16mf4_t*)(in + 100);
+    *(vint16mf4_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vint16mf4_t v = *(vint16mf4_t*)(in + 200);
+    *(vint16mf4_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vint16mf4_t v = *(vint16mf4_t*)(in + 300);
+    *(vint16mf4_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vint16mf4_t v = *(vint16mf4_t*)(in + i);
+      *(vint16mf4_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c
new file mode 100644
index 0000000..b9ebf57
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vuint16mf4_t v = *(vuint16mf4_t*)(in + 100);
+    *(vuint16mf4_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vuint16mf4_t v = *(vuint16mf4_t*)(in + 200);
+    *(vuint16mf4_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vuint16mf4_t v = *(vuint16mf4_t*)(in + 300);
+    *(vuint16mf4_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vuint16mf4_t v = *(vuint16mf4_t*)(in + i);
+      *(vuint16mf4_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c
new file mode 100644
index 0000000..12415de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vint16mf2_t v = *(vint16mf2_t*)(in + 100);
+    *(vint16mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vint16mf2_t v = *(vint16mf2_t*)(in + 200);
+    *(vint16mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vint16mf2_t v = *(vint16mf2_t*)(in + 300);
+    *(vint16mf2_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vint16mf2_t v = *(vint16mf2_t*)(in + i);
+      *(vint16mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c
new file mode 100644
index 0000000..ee08fa8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vuint16mf2_t v = *(vuint16mf2_t*)(in + 100);
+    *(vuint16mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vuint16mf2_t v = *(vuint16mf2_t*)(in + 200);
+    *(vuint16mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vuint16mf2_t v = *(vuint16mf2_t*)(in + 300);
+    *(vuint16mf2_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vuint16mf2_t v = *(vuint16mf2_t*)(in + i);
+      *(vuint16mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c
new file mode 100644
index 0000000..1f83d69
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vint32mf2_t v = *(vint32mf2_t*)(in + 100);
+    *(vint32mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vint32mf2_t v = *(vint32mf2_t*)(in + 200);
+    *(vint32mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vint32mf2_t v = *(vint32mf2_t*)(in + 300);
+    *(vint32mf2_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vint32mf2_t v = *(vint32mf2_t*)(in + i);
+      *(vint32mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c
new file mode 100644
index 0000000..8498754
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vuint32mf2_t v = *(vuint32mf2_t*)(in + 100);
+    *(vuint32mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vuint32mf2_t v = *(vuint32mf2_t*)(in + 200);
+    *(vuint32mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vuint32mf2_t v = *(vuint32mf2_t*)(in + 300);
+    *(vuint32mf2_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vuint32mf2_t v = *(vuint32mf2_t*)(in + i);
+      *(vuint32mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c
new file mode 100644
index 0000000..7506819
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 100);
+    *(vfloat32mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 200);
+    *(vfloat32mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 300);
+    *(vfloat32mf2_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vfloat32mf2_t v = *(vfloat32mf2_t*)(in + i);
+      *(vfloat32mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c
new file mode 100644
index 0000000..17758e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c
@@ -0,0 +1,231 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vbool64_t v = *(vbool64_t*)(in + 100);
+    *(vbool64_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vbool64_t v = *(vbool64_t*)(in + 200);
+    *(vbool64_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vbool64_t v = *(vbool64_t*)(in + 300);
+    *(vbool64_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vbool64_t v = *(vbool64_t*)(in + i);
+      *(vbool64_t*)(out + i) = v;
+    }
+}
+
+void f2 (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vbool32_t v = *(vbool32_t*)(in + 100);
+    *(vbool32_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vbool32_t v = *(vbool32_t*)(in + 200);
+    *(vbool32_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vbool32_t v = *(vbool32_t*)(in + 300);
+    *(vbool32_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vbool32_t v = *(vbool32_t*)(in + i);
+      *(vbool32_t*)(out + i) = v;
+    }
+}
+
+void f3 (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vbool16_t v = *(vbool16_t*)(in + 100);
+    *(vbool16_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vbool16_t v = *(vbool16_t*)(in + 200);
+    *(vbool16_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vbool16_t v = *(vbool16_t*)(in + 300);
+    *(vbool16_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vbool16_t v = *(vbool16_t*)(in + i);
+      *(vbool16_t*)(out + i) = v;
+    }
+}
+
+void f4 (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vbool8_t v = *(vbool8_t*)(in + 100);
+    *(vbool8_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vbool8_t v = *(vbool8_t*)(in + 200);
+    *(vbool8_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vbool8_t v = *(vbool8_t*)(in + 300);
+    *(vbool8_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vbool8_t v = *(vbool8_t*)(in + i);
+      *(vbool8_t*)(out + i) = v;
+    }
+}
+
+void f5 (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vbool4_t v = *(vbool4_t*)(in + 100);
+    *(vbool4_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vbool4_t v = *(vbool4_t*)(in + 200);
+    *(vbool4_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vbool4_t v = *(vbool4_t*)(in + 300);
+    *(vbool4_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vbool4_t v = *(vbool4_t*)(in + i);
+      *(vbool4_t*)(out + i) = v;
+    }
+}
+
+void f6 (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vbool2_t v = *(vbool2_t*)(in + 100);
+    *(vbool2_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vbool2_t v = *(vbool2_t*)(in + 200);
+    *(vbool2_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vbool2_t v = *(vbool2_t*)(in + 300);
+    *(vbool2_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vbool2_t v = *(vbool2_t*)(in + i);
+      *(vbool2_t*)(out + i) = v;
+    }
+}
+
+void f7 (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vbool1_t v = *(vbool1_t*)(in + 100);
+    *(vbool1_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vbool1_t v = *(vbool1_t*)(in + 200);
+    *(vbool1_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vbool1_t v = *(vbool1_t*)(in + 300);
+    *(vbool1_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vbool1_t v = *(vbool1_t*)(in + i);
+      *(vbool1_t*)(out + i) = v;
+    }
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+\.L[0-9]+\:} 1 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c
new file mode 100644
index 0000000..eb1afa5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vint8mf4_t v = *(vint8mf4_t*)(in + 100);
+      *(vint8mf4_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vint8mf4_t v = *(vint8mf4_t*)(in + 200);
+      *(vint8mf4_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vint8mf4_t v = *(vint8mf4_t*)(in + 300);
+      *(vint8mf4_t*)(out + 300) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf4_t v = *(vint8mf4_t*)(in + i);
+      *(vint8mf4_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c
new file mode 100644
index 0000000..535f326
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vuint8mf4_t v = *(vuint8mf4_t*)(in + 100);
+      *(vuint8mf4_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vuint8mf4_t v = *(vuint8mf4_t*)(in + 200);
+      *(vuint8mf4_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vuint8mf4_t v = *(vuint8mf4_t*)(in + 300);
+      *(vuint8mf4_t*)(out + 300) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vuint8mf4_t v = *(vuint8mf4_t*)(in + i);
+      *(vuint8mf4_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c
new file mode 100644
index 0000000..ea7f4e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vint8mf2_t v = *(vint8mf2_t*)(in + 100);
+      *(vint8mf2_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vint8mf2_t v = *(vint8mf2_t*)(in + 200);
+      *(vint8mf2_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vint8mf2_t v = *(vint8mf2_t*)(in + 300);
+      *(vint8mf2_t*)(out + 300) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf2_t v = *(vint8mf2_t*)(in + i);
+      *(vint8mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c
new file mode 100644
index 0000000..f340b44
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vuint8mf2_t v = *(vuint8mf2_t*)(in + 100);
+      *(vuint8mf2_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vuint8mf2_t v = *(vuint8mf2_t*)(in + 200);
+      *(vuint8mf2_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vuint8mf2_t v = *(vuint8mf2_t*)(in + 300);
+      *(vuint8mf2_t*)(out + 300) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vuint8mf2_t v = *(vuint8mf2_t*)(in + i);
+      *(vuint8mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c
new file mode 100644
index 0000000..70aea4e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vint16mf4_t v = *(vint16mf4_t*)(in + 100);
+      *(vint16mf4_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vint16mf4_t v = *(vint16mf4_t*)(in + 200);
+      *(vint16mf4_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vint16mf4_t v = *(vint16mf4_t*)(in + 300);
+      *(vint16mf4_t*)(out + 300) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vint16mf4_t v = *(vint16mf4_t*)(in + i);
+      *(vint16mf4_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c
new file mode 100644
index 0000000..697d5fa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vuint16mf4_t v = *(vuint16mf4_t*)(in + 100);
+      *(vuint16mf4_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vuint16mf4_t v = *(vuint16mf4_t*)(in + 200);
+      *(vuint16mf4_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vuint16mf4_t v = *(vuint16mf4_t*)(in + 300);
+      *(vuint16mf4_t*)(out + 300) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vuint16mf4_t v = *(vuint16mf4_t*)(in + i);
+      *(vuint16mf4_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c
new file mode 100644
index 0000000..f1edf8f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vint16mf2_t v = *(vint16mf2_t*)(in + 100);
+      *(vint16mf2_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vint16mf2_t v = *(vint16mf2_t*)(in + 200);
+      *(vint16mf2_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vint16mf2_t v = *(vint16mf2_t*)(in + 300);
+      *(vint16mf2_t*)(out + 300) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vint16mf2_t v = *(vint16mf2_t*)(in + i);
+      *(vint16mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"   no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0"    no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c
new file mode 100644
index 0000000..cd58e53
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vint8mf8_t v = *(vint8mf8_t*)(in + 100);
+      *(vint8mf8_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vint8mf8_t v = *(vint8mf8_t*)(in + 200);
+      *(vint8mf8_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vint8mf8_t v = *(vint8mf8_t*)(in + 300);
+      *(vint8mf8_t*)(out + 300) = v;
+    }
+  else
+    {
+      vint8mf8_t v = *(vint8mf8_t*)(in + 400);
+      *(vint8mf8_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf8_t v = *(vint8mf8_t*)(in + i);
+      *(vint8mf8_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,\.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c
new file mode 100644
index 0000000..1aaebdf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vuint16mf2_t v = *(vuint16mf2_t*)(in + 100);
+      *(vuint16mf2_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vuint16mf2_t v = *(vuint16mf2_t*)(in + 200);
+      *(vuint16mf2_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vuint16mf2_t v = *(vuint16mf2_t*)(in + 300);
+      *(vuint16mf2_t*)(out + 300) = v;
+    }
+  else
+    {
+      vuint16mf2_t v = *(vuint16mf2_t*)(in + 400);
+      *(vuint16mf2_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vuint16mf2_t v = *(vuint16mf2_t*)(in + i);
+      *(vuint16mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c
new file mode 100644
index 0000000..813ea49
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vint32mf2_t v = *(vint32mf2_t*)(in + 100);
+      *(vint32mf2_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vint32mf2_t v = *(vint32mf2_t*)(in + 200);
+      *(vint32mf2_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vint32mf2_t v = *(vint32mf2_t*)(in + 300);
+      *(vint32mf2_t*)(out + 300) = v;
+    }
+  else
+    {
+      vint32mf2_t v = *(vint32mf2_t*)(in + 400);
+      *(vint32mf2_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vint32mf2_t v = *(vint32mf2_t*)(in + i);
+      *(vint32mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c
new file mode 100644
index 0000000..9b59df9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vuint32mf2_t v = *(vuint32mf2_t*)(in + 100);
+      *(vuint32mf2_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vuint32mf2_t v = *(vuint32mf2_t*)(in + 200);
+      *(vuint32mf2_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vuint32mf2_t v = *(vuint32mf2_t*)(in + 300);
+      *(vuint32mf2_t*)(out + 300) = v;
+    }
+  else
+    {
+      vuint32mf2_t v = *(vuint32mf2_t*)(in + 400);
+      *(vuint32mf2_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vuint32mf2_t v = *(vuint32mf2_t*)(in + i);
+      *(vuint32mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c
new file mode 100644
index 0000000..35e4fd1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 100);
+      *(vfloat32mf2_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 200);
+      *(vfloat32mf2_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 300);
+      *(vfloat32mf2_t*)(out + 300) = v;
+    }
+  else
+    {
+      vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 400);
+      *(vfloat32mf2_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vfloat32mf2_t v = *(vfloat32mf2_t*)(in + i);
+      *(vfloat32mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c
new file mode 100644
index 0000000..2330d34
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c
@@ -0,0 +1,217 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vbool64_t v = *(vbool64_t*)(in + 100);
+      *(vbool64_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vbool64_t v = *(vbool64_t*)(in + 200);
+      *(vbool64_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vbool64_t v = *(vbool64_t*)(in + 300);
+      *(vbool64_t*)(out + 300) = v;
+    }
+  else
+    {
+      vbool64_t v = *(vbool64_t*)(in + 400);
+      *(vbool64_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vbool64_t v = *(vbool64_t*)(in + i);
+      *(vbool64_t*)(out + i) = v;
+    }
+}
+
+void f2 (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vbool32_t v = *(vbool32_t*)(in + 100);
+      *(vbool32_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vbool32_t v = *(vbool32_t*)(in + 200);
+      *(vbool32_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vbool32_t v = *(vbool32_t*)(in + 300);
+      *(vbool32_t*)(out + 300) = v;
+    }
+  else
+    {
+      vbool32_t v = *(vbool32_t*)(in + 400);
+      *(vbool32_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vbool32_t v = *(vbool32_t*)(in + i);
+      *(vbool32_t*)(out + i) = v;
+    }
+}
+
+void f3 (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vbool16_t v = *(vbool16_t*)(in + 100);
+      *(vbool16_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vbool16_t v = *(vbool16_t*)(in + 200);
+      *(vbool16_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vbool16_t v = *(vbool16_t*)(in + 300);
+      *(vbool16_t*)(out + 300) = v;
+    }
+  else
+    {
+      vbool16_t v = *(vbool16_t*)(in + 400);
+      *(vbool16_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vbool16_t v = *(vbool16_t*)(in + i);
+      *(vbool16_t*)(out + i) = v;
+    }
+}
+
+void f4 (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vbool8_t v = *(vbool8_t*)(in + 100);
+      *(vbool8_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vbool8_t v = *(vbool8_t*)(in + 200);
+      *(vbool8_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vbool8_t v = *(vbool8_t*)(in + 300);
+      *(vbool8_t*)(out + 300) = v;
+    }
+  else
+    {
+      vbool8_t v = *(vbool8_t*)(in + 400);
+      *(vbool8_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vbool8_t v = *(vbool8_t*)(in + i);
+      *(vbool8_t*)(out + i) = v;
+    }
+}
+
+void f5 (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vbool4_t v = *(vbool4_t*)(in + 100);
+      *(vbool4_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vbool4_t v = *(vbool4_t*)(in + 200);
+      *(vbool4_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vbool4_t v = *(vbool4_t*)(in + 300);
+      *(vbool4_t*)(out + 300) = v;
+    }
+  else
+    {
+      vbool4_t v = *(vbool4_t*)(in + 400);
+      *(vbool4_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vbool4_t v = *(vbool4_t*)(in + i);
+      *(vbool4_t*)(out + i) = v;
+    }
+}
+
+void f6 (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vbool2_t v = *(vbool2_t*)(in + 100);
+      *(vbool2_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vbool2_t v = *(vbool2_t*)(in + 200);
+      *(vbool2_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vbool2_t v = *(vbool2_t*)(in + 300);
+      *(vbool2_t*)(out + 300) = v;
+    }
+  else
+    {
+      vbool2_t v = *(vbool2_t*)(in + 400);
+      *(vbool2_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vbool2_t v = *(vbool2_t*)(in + i);
+      *(vbool2_t*)(out + i) = v;
+    }
+}
+
+void f7 (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vbool1_t v = *(vbool1_t*)(in + 100);
+      *(vbool1_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vbool1_t v = *(vbool1_t*)(in + 200);
+      *(vbool1_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vbool1_t v = *(vbool1_t*)(in + 300);
+      *(vbool1_t*)(out + 300) = v;
+    }
+  else
+    {
+      vbool1_t v = *(vbool1_t*)(in + 400);
+      *(vbool1_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vbool1_t v = *(vbool1_t*)(in + i);
+      *(vbool1_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s+\.L[0-9]+\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 7 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c
new file mode 100644
index 0000000..687ecdf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vint8mf8_t v = *(vint8mf8_t*)(in + 100);
+    *(vint8mf8_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vint8mf8_t v = *(vint8mf8_t*)(in + 200);
+    *(vint8mf8_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vint8mf8_t v = *(vint8mf8_t*)(in + 300);
+    *(vint8mf8_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vint8mf8_t v = *(vint8mf8_t*)(in + 400);
+    *(vint8mf8_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf8_t v = *(vint8mf8_t*)(in + i);
+      *(vint8mf8_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c
new file mode 100644
index 0000000..d644fb6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 100);
+    *(vuint8mf8_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 200);
+    *(vuint8mf8_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 300);
+    *(vuint8mf8_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vuint8mf8_t v = *(vuint8mf8_t*)(in + 400);
+    *(vuint8mf8_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vuint8mf8_t v = *(vuint8mf8_t*)(in + i);
+      *(vuint8mf8_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c
new file mode 100644
index 0000000..ea4d955
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vint8mf4_t v = *(vint8mf4_t*)(in + 100);
+    *(vint8mf4_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vint8mf4_t v = *(vint8mf4_t*)(in + 200);
+    *(vint8mf4_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vint8mf4_t v = *(vint8mf4_t*)(in + 300);
+    *(vint8mf4_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vint8mf4_t v = *(vint8mf4_t*)(in + 400);
+    *(vint8mf4_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf4_t v = *(vint8mf4_t*)(in + i);
+      *(vint8mf4_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c
new file mode 100644
index 0000000..cbbffb7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vuint8mf4_t v = *(vuint8mf4_t*)(in + 100);
+    *(vuint8mf4_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vuint8mf4_t v = *(vuint8mf4_t*)(in + 200);
+    *(vuint8mf4_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vuint8mf4_t v = *(vuint8mf4_t*)(in + 300);
+    *(vuint8mf4_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vuint8mf4_t v = *(vuint8mf4_t*)(in + 400);
+    *(vuint8mf4_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vuint8mf4_t v = *(vuint8mf4_t*)(in + i);
+      *(vuint8mf4_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c
new file mode 100644
index 0000000..21d5cc9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vint8mf2_t v = *(vint8mf2_t*)(in + 100);
+    *(vint8mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vint8mf2_t v = *(vint8mf2_t*)(in + 200);
+    *(vint8mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vint8mf2_t v = *(vint8mf2_t*)(in + 300);
+    *(vint8mf2_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vint8mf2_t v = *(vint8mf2_t*)(in + 400);
+    *(vint8mf2_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf2_t v = *(vint8mf2_t*)(in + i);
+      *(vint8mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"   } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s+\.L[0-9]+\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"   } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c
new file mode 100644
index 0000000..39d523b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vuint8mf8_t v = *(vuint8mf8_t*)(in + 100);
+      *(vuint8mf8_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vuint8mf8_t v = *(vuint8mf8_t*)(in + 200);
+      *(vuint8mf8_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vuint8mf8_t v = *(vuint8mf8_t*)(in + 300);
+      *(vuint8mf8_t*)(out + 300) = v;
+    }
+  else
+    {
+      vuint8mf8_t v = *(vuint8mf8_t*)(in + 400);
+      *(vuint8mf8_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vuint8mf8_t v = *(vuint8mf8_t*)(in + i);
+      *(vuint8mf8_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g"  no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c
new file mode 100644
index 0000000..29dd2d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vuint8mf2_t v = *(vuint8mf2_t*)(in + 100);
+    *(vuint8mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vuint8mf2_t v = *(vuint8mf2_t*)(in + 200);
+    *(vuint8mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vuint8mf2_t v = *(vuint8mf2_t*)(in + 300);
+    *(vuint8mf2_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vuint8mf2_t v = *(vuint8mf2_t*)(in + 400);
+    *(vuint8mf2_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vuint8mf2_t v = *(vuint8mf2_t*)(in + i);
+      *(vuint8mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s+\.L[0-9]+\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c
new file mode 100644
index 0000000..286a743
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vint16mf4_t v = *(vint16mf4_t*)(in + 100);
+    *(vint16mf4_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vint16mf4_t v = *(vint16mf4_t*)(in + 200);
+    *(vint16mf4_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vint16mf4_t v = *(vint16mf4_t*)(in + 300);
+    *(vint16mf4_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vint16mf4_t v = *(vint16mf4_t*)(in + 400);
+    *(vint16mf4_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vint16mf4_t v = *(vint16mf4_t*)(in + i);
+      *(vint16mf4_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s+\.L[0-9]+\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c
new file mode 100644
index 0000000..4cd8a5d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vuint16mf4_t v = *(vuint16mf4_t*)(in + 100);
+    *(vuint16mf4_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vuint16mf4_t v = *(vuint16mf4_t*)(in + 200);
+    *(vuint16mf4_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vuint16mf4_t v = *(vuint16mf4_t*)(in + 300);
+    *(vuint16mf4_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vuint16mf4_t v = *(vuint16mf4_t*)(in + 400);
+    *(vuint16mf4_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vuint16mf4_t v = *(vuint16mf4_t*)(in + i);
+      *(vuint16mf4_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c
new file mode 100644
index 0000000..5825f12
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vint16mf2_t v = *(vint16mf2_t*)(in + 100);
+    *(vint16mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vint16mf2_t v = *(vint16mf2_t*)(in + 200);
+    *(vint16mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vint16mf2_t v = *(vint16mf2_t*)(in + 300);
+    *(vint16mf2_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vint16mf2_t v = *(vint16mf2_t*)(in + 400);
+    *(vint16mf2_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vint16mf2_t v = *(vint16mf2_t*)(in + i);
+      *(vint16mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c
new file mode 100644
index 0000000..e2b5331
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vuint16mf2_t v = *(vuint16mf2_t*)(in + 100);
+    *(vuint16mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vuint16mf2_t v = *(vuint16mf2_t*)(in + 200);
+    *(vuint16mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vuint16mf2_t v = *(vuint16mf2_t*)(in + 300);
+    *(vuint16mf2_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vuint16mf2_t v = *(vuint16mf2_t*)(in + 400);
+    *(vuint16mf2_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vuint16mf2_t v = *(vuint16mf2_t*)(in + i);
+      *(vuint16mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c
new file mode 100644
index 0000000..f40ff57
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vint32mf2_t v = *(vint32mf2_t*)(in + 100);
+    *(vint32mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vint32mf2_t v = *(vint32mf2_t*)(in + 200);
+    *(vint32mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vint32mf2_t v = *(vint32mf2_t*)(in + 300);
+    *(vint32mf2_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vint32mf2_t v = *(vint32mf2_t*)(in + 400);
+    *(vint32mf2_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vint32mf2_t v = *(vint32mf2_t*)(in + i);
+      *(vint32mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c
new file mode 100644
index 0000000..26a9933
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vuint32mf2_t v = *(vuint32mf2_t*)(in + 100);
+    *(vuint32mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vuint32mf2_t v = *(vuint32mf2_t*)(in + 200);
+    *(vuint32mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vuint32mf2_t v = *(vuint32mf2_t*)(in + 300);
+    *(vuint32mf2_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vuint32mf2_t v = *(vuint32mf2_t*)(in + 400);
+    *(vuint32mf2_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vuint32mf2_t v = *(vuint32mf2_t*)(in + i);
+      *(vuint32mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c
new file mode 100644
index 0000000..7028d91
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 100);
+    *(vfloat32mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 200);
+    *(vfloat32mf2_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 300);
+    *(vfloat32mf2_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 400);
+    *(vfloat32mf2_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vfloat32mf2_t v = *(vfloat32mf2_t*)(in + i);
+      *(vfloat32mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c
new file mode 100644
index 0000000..aa4c1a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c
@@ -0,0 +1,237 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vbool64_t v = *(vbool64_t*)(in + 100);
+    *(vbool64_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vbool64_t v = *(vbool64_t*)(in + 200);
+    *(vbool64_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vbool64_t v = *(vbool64_t*)(in + 300);
+    *(vbool64_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vbool64_t v = *(vbool64_t*)(in + 400);
+    *(vbool64_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vbool64_t v = *(vbool64_t*)(in + i);
+      *(vbool64_t*)(out + i) = v;
+    }
+}
+
+void f2 (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vbool32_t v = *(vbool32_t*)(in + 100);
+    *(vbool32_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vbool32_t v = *(vbool32_t*)(in + 200);
+    *(vbool32_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vbool32_t v = *(vbool32_t*)(in + 300);
+    *(vbool32_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vbool32_t v = *(vbool32_t*)(in + 400);
+    *(vbool32_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vbool32_t v = *(vbool32_t*)(in + i);
+      *(vbool32_t*)(out + i) = v;
+    }
+}
+
+void f3 (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vbool16_t v = *(vbool16_t*)(in + 100);
+    *(vbool16_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vbool16_t v = *(vbool16_t*)(in + 200);
+    *(vbool16_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vbool16_t v = *(vbool16_t*)(in + 300);
+    *(vbool16_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vbool16_t v = *(vbool16_t*)(in + 400);
+    *(vbool16_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vbool16_t v = *(vbool16_t*)(in + i);
+      *(vbool16_t*)(out + i) = v;
+    }
+}
+
+void f4 (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vbool8_t v = *(vbool8_t*)(in + 100);
+    *(vbool8_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vbool8_t v = *(vbool8_t*)(in + 200);
+    *(vbool8_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vbool8_t v = *(vbool8_t*)(in + 300);
+    *(vbool8_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vbool8_t v = *(vbool8_t*)(in + 400);
+    *(vbool8_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vbool8_t v = *(vbool8_t*)(in + i);
+      *(vbool8_t*)(out + i) = v;
+    }
+}
+
+void f5 (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vbool4_t v = *(vbool4_t*)(in + 100);
+    *(vbool4_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vbool4_t v = *(vbool4_t*)(in + 200);
+    *(vbool4_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vbool4_t v = *(vbool4_t*)(in + 300);
+    *(vbool4_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vbool4_t v = *(vbool4_t*)(in + 400);
+    *(vbool4_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vbool4_t v = *(vbool4_t*)(in + i);
+      *(vbool4_t*)(out + i) = v;
+    }
+}
+
+void f6 (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vbool2_t v = *(vbool2_t*)(in + 100);
+    *(vbool2_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vbool2_t v = *(vbool2_t*)(in + 200);
+    *(vbool2_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vbool2_t v = *(vbool2_t*)(in + 300);
+    *(vbool2_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vbool2_t v = *(vbool2_t*)(in + 400);
+    *(vbool2_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vbool2_t v = *(vbool2_t*)(in + i);
+      *(vbool2_t*)(out + i) = v;
+    }
+}
+
+void f7 (void * restrict in, void * restrict out, int n, int cond)
+{
+  switch (cond)
+  {
+  case 1:{
+    vbool1_t v = *(vbool1_t*)(in + 100);
+    *(vbool1_t*)(out + 100) = v;
+    break;
+  }
+  case 2:{
+    vbool1_t v = *(vbool1_t*)(in + 200);
+    *(vbool1_t*)(out + 100) = v;
+    break;
+  }
+  case 3:{
+    vbool1_t v = *(vbool1_t*)(in + 300);
+    *(vbool1_t*)(out + 100) = v;
+    break;
+  }
+  default:{
+    vbool1_t v = *(vbool1_t*)(in + 400);
+    *(vbool1_t*)(out + 400) = v;
+    break;
+  }
+  }
+  for (int i = 0; i < n; i++)
+    {
+      vbool1_t v = *(vbool1_t*)(in + i);
+      *(vbool1_t*)(out + i) = v;
+    }
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vlm\.v\s*(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 7 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c
new file mode 100644
index 0000000..41585d0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vint8mf4_t v = *(vint8mf4_t*)(in + 100);
+      *(vint8mf4_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vint8mf4_t v = *(vint8mf4_t*)(in + 200);
+      *(vint8mf4_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vint8mf4_t v = *(vint8mf4_t*)(in + 300);
+      *(vint8mf4_t*)(out + 300) = v;
+    }
+  else
+    {
+      vint8mf4_t v = *(vint8mf4_t*)(in + 400);
+      *(vint8mf4_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf4_t v = *(vint8mf4_t*)(in + i);
+      *(vint8mf4_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g"   no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g"   no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c
new file mode 100644
index 0000000..d4890e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vuint8mf4_t v = *(vuint8mf4_t*)(in + 100);
+      *(vuint8mf4_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vuint8mf4_t v = *(vuint8mf4_t*)(in + 200);
+      *(vuint8mf4_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vuint8mf4_t v = *(vuint8mf4_t*)(in + 300);
+      *(vuint8mf4_t*)(out + 300) = v;
+    }
+  else
+    {
+      vuint8mf4_t v = *(vuint8mf4_t*)(in + 400);
+      *(vuint8mf4_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vuint8mf4_t v = *(vuint8mf4_t*)(in + i);
+      *(vuint8mf4_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g"  no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g"  no-opts "-flto"  } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c
new file mode 100644
index 0000000..53905fc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vint8mf2_t v = *(vint8mf2_t*)(in + 100);
+      *(vint8mf2_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vint8mf2_t v = *(vint8mf2_t*)(in + 200);
+      *(vint8mf2_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vint8mf2_t v = *(vint8mf2_t*)(in + 300);
+      *(vint8mf2_t*)(out + 300) = v;
+    }
+  else
+    {
+      vint8mf2_t v = *(vint8mf2_t*)(in + 400);
+      *(vint8mf2_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf2_t v = *(vint8mf2_t*)(in + i);
+      *(vint8mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c
new file mode 100644
index 0000000..4d56ec5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vuint8mf2_t v = *(vuint8mf2_t*)(in + 100);
+      *(vuint8mf2_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vuint8mf2_t v = *(vuint8mf2_t*)(in + 200);
+      *(vuint8mf2_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vuint8mf2_t v = *(vuint8mf2_t*)(in + 300);
+      *(vuint8mf2_t*)(out + 300) = v;
+    }
+  else
+    {
+      vuint8mf2_t v = *(vuint8mf2_t*)(in + 400);
+      *(vuint8mf2_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vuint8mf2_t v = *(vuint8mf2_t*)(in + i);
+      *(vuint8mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c
new file mode 100644
index 0000000..f722ec4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vint16mf4_t v = *(vint16mf4_t*)(in + 100);
+      *(vint16mf4_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vint16mf4_t v = *(vint16mf4_t*)(in + 200);
+      *(vint16mf4_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vint16mf4_t v = *(vint16mf4_t*)(in + 300);
+      *(vint16mf4_t*)(out + 300) = v;
+    }
+  else
+    {
+      vint16mf4_t v = *(vint16mf4_t*)(in + 400);
+      *(vint16mf4_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vint16mf4_t v = *(vint16mf4_t*)(in + i);
+      *(vint16mf4_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c
new file mode 100644
index 0000000..69bd0be
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vuint16mf4_t v = *(vuint16mf4_t*)(in + 100);
+      *(vuint16mf4_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vuint16mf4_t v = *(vuint16mf4_t*)(in + 200);
+      *(vuint16mf4_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vuint16mf4_t v = *(vuint16mf4_t*)(in + 300);
+      *(vuint16mf4_t*)(out + 300) = v;
+    }
+  else
+    {
+      vuint16mf4_t v = *(vuint16mf4_t*)(in + 400);
+      *(vuint16mf4_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vuint16mf4_t v = *(vuint16mf4_t*)(in + i);
+      *(vuint16mf4_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c
new file mode 100644
index 0000000..208173f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* The for loop body should not have vsetvl instruction.  */
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+  if (cond == 1)
+    {
+      vint16mf2_t v = *(vint16mf2_t*)(in + 100);
+      *(vint16mf2_t*)(out + 100) = v;
+    }
+  else if (cond == 2)
+    {
+      vint16mf2_t v = *(vint16mf2_t*)(in + 200);
+      *(vint16mf2_t*)(out + 200) = v;
+    }
+  else if (cond == 3)
+    {
+      vint16mf2_t v = *(vint16mf2_t*)(in + 300);
+      *(vint16mf2_t*)(out + 300) = v;
+    }
+  else
+    {
+      vint16mf2_t v = *(vint16mf2_t*)(in + 400);
+      *(vint16mf2_t*)(out + 400) = v;
+    }
+  for (int i = 0; i < n; i++)
+    {
+      vint16mf2_t v = *(vint16mf2_t*)(in + i);
+      *(vint16mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\tra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7],zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c
new file mode 100644
index 0000000..fb1258f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c
@@ -0,0 +1,154 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+/* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */
+
+#include "riscv_vector.h"
+
+void foo1 (void * restrict in, void * restrict out)
+{
+  vbool64_t v1 = *(vbool64_t*)(in + 1);
+  vbool64_t v2 = *(vbool64_t*)(in + 2);
+  vbool64_t v3 = *(vbool64_t*)(in + 3);
+  vbool64_t v4 = *(vbool64_t*)(in + 4);
+  vbool64_t v5 = *(vbool64_t*)(in + 5);
+  vbool64_t v6 = *(vbool64_t*)(in + 6);
+  vbool64_t v7 = *(vbool64_t*)(in + 7);
+  vbool64_t v8 = *(vbool64_t*)(in + 8);
+  *(vbool64_t*)(out + 1) = v1;
+  *(vbool64_t*)(out + 2) = v2;
+  *(vbool64_t*)(out + 3) = v3;
+  *(vbool64_t*)(out + 4) = v4;
+  *(vbool64_t*)(out + 5) = v5;
+  *(vbool64_t*)(out + 6) = v6;
+  *(vbool64_t*)(out + 7) = v7;
+  *(vbool64_t*)(out + 8) = v8;
+}
+
+void foo2 (void * restrict in, void * restrict out)
+{
+  vbool32_t v1 = *(vbool32_t*)(in + 1);
+  vbool32_t v2 = *(vbool32_t*)(in + 2);
+  vbool32_t v3 = *(vbool32_t*)(in + 3);
+  vbool32_t v4 = *(vbool32_t*)(in + 4);
+  vbool32_t v5 = *(vbool32_t*)(in + 5);
+  vbool32_t v6 = *(vbool32_t*)(in + 6);
+  vbool32_t v7 = *(vbool32_t*)(in + 7);
+  vbool32_t v8 = *(vbool32_t*)(in + 8);
+  *(vbool32_t*)(out + 1) = v1;
+  *(vbool32_t*)(out + 2) = v2;
+  *(vbool32_t*)(out + 3) = v3;
+  *(vbool32_t*)(out + 4) = v4;
+  *(vbool32_t*)(out + 5) = v5;
+  *(vbool32_t*)(out + 6) = v6;
+  *(vbool32_t*)(out + 7) = v7;
+  *(vbool32_t*)(out + 8) = v8;
+}
+
+void foo3 (void * restrict in, void * restrict out)
+{
+  vbool16_t v1 = *(vbool16_t*)(in + 1);
+  vbool16_t v2 = *(vbool16_t*)(in + 2);
+  vbool16_t v3 = *(vbool16_t*)(in + 3);
+  vbool16_t v4 = *(vbool16_t*)(in + 4);
+  vbool16_t v5 = *(vbool16_t*)(in + 5);
+  vbool16_t v6 = *(vbool16_t*)(in + 6);
+  vbool16_t v7 = *(vbool16_t*)(in + 7);
+  vbool16_t v8 = *(vbool16_t*)(in + 8);
+  *(vbool16_t*)(out + 1) = v1;
+  *(vbool16_t*)(out + 2) = v2;
+  *(vbool16_t*)(out + 3) = v3;
+  *(vbool16_t*)(out + 4) = v4;
+  *(vbool16_t*)(out + 5) = v5;
+  *(vbool16_t*)(out + 6) = v6;
+  *(vbool16_t*)(out + 7) = v7;
+  *(vbool16_t*)(out + 8) = v8;
+}
+
+void foo4 (void * restrict in, void * restrict out)
+{
+  vbool8_t v1 = *(vbool8_t*)(in + 1);
+  vbool8_t v2 = *(vbool8_t*)(in + 2);
+  vbool8_t v3 = *(vbool8_t*)(in + 3);
+  vbool8_t v4 = *(vbool8_t*)(in + 4);
+  vbool8_t v5 = *(vbool8_t*)(in + 5);
+  vbool8_t v6 = *(vbool8_t*)(in + 6);
+  vbool8_t v7 = *(vbool8_t*)(in + 7);
+  vbool8_t v8 = *(vbool8_t*)(in + 8);
+  *(vbool8_t*)(out + 1) = v1;
+  *(vbool8_t*)(out + 2) = v2;
+  *(vbool8_t*)(out + 3) = v3;
+  *(vbool8_t*)(out + 4) = v4;
+  *(vbool8_t*)(out + 5) = v5;
+  *(vbool8_t*)(out + 6) = v6;
+  *(vbool8_t*)(out + 7) = v7;
+  *(vbool8_t*)(out + 8) = v8;
+}
+
+void foo5 (void * restrict in, void * restrict out)
+{
+  vbool4_t v1 = *(vbool4_t*)(in + 1);
+  vbool4_t v2 = *(vbool4_t*)(in + 2);
+  vbool4_t v3 = *(vbool4_t*)(in + 3);
+  vbool4_t v4 = *(vbool4_t*)(in + 4);
+  vbool4_t v5 = *(vbool4_t*)(in + 5);
+  vbool4_t v6 = *(vbool4_t*)(in + 6);
+  vbool4_t v7 = *(vbool4_t*)(in + 7);
+  vbool4_t v8 = *(vbool4_t*)(in + 8);
+  *(vbool4_t*)(out + 1) = v1;
+  *(vbool4_t*)(out + 2) = v2;
+  *(vbool4_t*)(out + 3) = v3;
+  *(vbool4_t*)(out + 4) = v4;
+  *(vbool4_t*)(out + 5) = v5;
+  *(vbool4_t*)(out + 6) = v6;
+  *(vbool4_t*)(out + 7) = v7;
+  *(vbool4_t*)(out + 8) = v8;
+}
+
+void foo6 (void * restrict in, void * restrict out)
+{
+  vbool2_t v1 = *(vbool2_t*)(in + 1);
+  vbool2_t v2 = *(vbool2_t*)(in + 2);
+  vbool2_t v3 = *(vbool2_t*)(in + 3);
+  vbool2_t v4 = *(vbool2_t*)(in + 4);
+  vbool2_t v5 = *(vbool2_t*)(in + 5);
+  vbool2_t v6 = *(vbool2_t*)(in + 6);
+  vbool2_t v7 = *(vbool2_t*)(in + 7);
+  vbool2_t v8 = *(vbool2_t*)(in + 8);
+  *(vbool2_t*)(out + 1) = v1;
+  *(vbool2_t*)(out + 2) = v2;
+  *(vbool2_t*)(out + 3) = v3;
+  *(vbool2_t*)(out + 4) = v4;
+  *(vbool2_t*)(out + 5) = v5;
+  *(vbool2_t*)(out + 6) = v6;
+  *(vbool2_t*)(out + 7) = v7;
+  *(vbool2_t*)(out + 8) = v8;
+}
+
+void foo7 (void * restrict in, void * restrict out)
+{
+  vbool1_t v1 = *(vbool1_t*)(in + 1);
+  vbool1_t v2 = *(vbool1_t*)(in + 2);
+  vbool1_t v3 = *(vbool1_t*)(in + 3);
+  vbool1_t v4 = *(vbool1_t*)(in + 4);
+  vbool1_t v5 = *(vbool1_t*)(in + 5);
+  vbool1_t v6 = *(vbool1_t*)(in + 6);
+  vbool1_t v7 = *(vbool1_t*)(in + 7);
+  vbool1_t v8 = *(vbool1_t*)(in + 8);
+  *(vbool1_t*)(out + 1) = v1;
+  *(vbool1_t*)(out + 2) = v2;
+  *(vbool1_t*)(out + 3) = v3;
+  *(vbool1_t*)(out + 4) = v4;
+  *(vbool1_t*)(out + 5) = v5;
+  *(vbool1_t*)(out + 6) = v6;
+  *(vbool1_t*)(out + 7) = v7;
+  *(vbool1_t*)(out + 8) = v8;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c
new file mode 100644
index 0000000..bdfb964
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c
@@ -0,0 +1,143 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f1 (void * restrict in, void * restrict out)
+{
+  vint16mf4_t v1 = *(vint16mf4_t*)(in + 1);
+  vint8mf8_t v2;
+  *(vint16mf4_t*)(out + 1) = v1;
+  *(vint8mf8_t*)(out + 2) = v2;
+}
+
+void f2 (void * restrict in, void * restrict out)
+{
+  vint16mf4_t v1 = *(vint16mf4_t*)(in + 1);
+  vint32mf2_t v2;
+  *(vint16mf4_t*)(out + 1) = v1;
+  *(vint32mf2_t*)(out + 2) = v2;
+}
+
+void f3 (void * restrict in, void * restrict out)
+{
+  vint16mf4_t v1 = *(vint16mf4_t*)(in + 1);
+  vint64m1_t v2;
+  *(vint16mf4_t*)(out + 1) = v1;
+  *(vint64m1_t*)(out + 2) = v2;
+}
+
+void f4 (void * restrict in, void * restrict out)
+{
+  vint16mf2_t v1 = *(vint16mf2_t*)(in + 1);
+  vint8mf4_t v2;
+  *(vint16mf2_t*)(out + 1) = v1;
+  *(vint8mf4_t*)(out + 2) = v2;
+}
+
+void f5 (void * restrict in, void * restrict out)
+{
+  vint16mf2_t v1 = *(vint16mf2_t*)(in + 1);
+  vint32m1_t v2;
+  *(vint16mf2_t*)(out + 1) = v1;
+  *(vint32m1_t*)(out + 2) = v2;
+}
+
+void f6 (void * restrict in, void * restrict out)
+{
+  vint16mf2_t v1 = *(vint16mf2_t*)(in + 1);
+  vint64m2_t v2;
+  *(vint16mf2_t*)(out + 1) = v1;
+  *(vint64m2_t*)(out + 2) = v2;
+}
+
+void f7 (void * restrict in, void * restrict out)
+{
+  vint16m1_t v1 = *(vint16m1_t*)(in + 1);
+  vint8mf2_t v2;
+  *(vint16m1_t*)(out + 1) = v1;
+  *(vint8mf2_t*)(out + 2) = v2;
+}
+
+void f8 (void * restrict in, void * restrict out)
+{
+  vint16m1_t v1 = *(vint16m1_t*)(in + 1);
+  vint32m2_t v2;
+  *(vint16m1_t*)(out + 1) = v1;
+  *(vint32m2_t*)(out + 2) = v2;
+}
+
+void f9 (void * restrict in, void * restrict out)
+{
+  vint16m1_t v1 = *(vint16m1_t*)(in + 1);
+  vint64m4_t v2;
+  *(vint16m1_t*)(out + 1) = v1;
+  *(vint64m4_t*)(out + 2) = v2;
+}
+
+void f10 (void * restrict in, void * restrict out)
+{
+  vint16m2_t v1 = *(vint16m2_t*)(in + 1);
+  vint8m1_t v2;
+  *(vint16m2_t*)(out + 1) = v1;
+  *(vint8m1_t*)(out + 2) = v2;
+}
+
+void f11 (void * restrict in, void * restrict out)
+{
+  vint16m2_t v1 = *(vint16m2_t*)(in + 1);
+  vint32m4_t v2;
+  *(vint16m2_t*)(out + 1) = v1;
+  *(vint32m4_t*)(out + 2) = v2;
+}
+
+void f12 (void * restrict in, void * restrict out)
+{
+  vint16m2_t v1 = *(vint16m2_t*)(in + 1);
+  vint64m8_t v2;
+  *(vint16m2_t*)(out + 1) = v1;
+  *(vint64m8_t*)(out + 2) = v2;
+}
+
+void f13 (void * restrict in, void * restrict out)
+{
+  vint16m4_t v1 = *(vint16m4_t*)(in + 1);
+  vint8m2_t v2;
+  *(vint16m4_t*)(out + 1) = v1;
+  *(vint8m2_t*)(out + 2) = v2;
+}
+
+void f14 (void * restrict in, void * restrict out)
+{
+  vint16m4_t v1 = *(vint16m4_t*)(in + 1);
+  vint32m8_t v2;
+  *(vint16m4_t*)(out + 1) = v1;
+  *(vint32m8_t*)(out + 2) = v2;
+}
+
+void f15 (void * restrict in, void * restrict out)
+{
+  vint16m8_t v1 = *(vint16m8_t*)(in + 1);
+  vint8m4_t v2;
+  *(vint16m8_t*)(out + 1) = v1;
+  *(vint8m4_t*)(out + 2) = v2;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli} 15 { target { no-opts "-O0" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c
new file mode 100644
index 0000000..17055f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f1 (void * restrict in, void * restrict out)
+{
+  vint32mf2_t v1 = *(vint32mf2_t*)(in + 1);
+  vint8mf8_t v2;
+  *(vint32mf2_t*)(out + 1) = v1;
+  *(vint8mf8_t*)(out + 2) = v2;
+}
+
+void f2 (void * restrict in, void * restrict out)
+{
+  vint32mf2_t v1 = *(vint32mf2_t*)(in + 1);
+  vint16mf4_t v2;
+  *(vint32mf2_t*)(out + 1) = v1;
+  *(vint16mf4_t*)(out + 2) = v2;
+}
+
+void f3 (void * restrict in, void * restrict out)
+{
+  vint32mf2_t v1 = *(vint32mf2_t*)(in + 1);
+  vint64m1_t v2;
+  *(vint32mf2_t*)(out + 1) = v1;
+  *(vint64m1_t*)(out + 2) = v2;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c
new file mode 100644
index 0000000..1383995
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c
@@ -0,0 +1,92 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f1 (void * restrict in, void * restrict out)
+{
+  vint8mf8_t v1 = *(vint8mf8_t*)(in + 1);
+  vfloat32mf2_t v2;
+  *(vint8mf8_t*)(out + 1) = v1;
+  *(vfloat32mf2_t*)(out + 2) = v2;
+}
+
+void f2 (void * restrict in, void * restrict out)
+{
+  vint8mf8_t v1 = *(vint8mf8_t*)(in + 1);
+  vfloat64m1_t v2;
+  *(vint8mf8_t*)(out + 1) = v1;
+  *(vfloat64m1_t*)(out + 2) = v2;
+}
+
+void f3 (void * restrict in, void * restrict out)
+{
+  vint8mf4_t v1 = *(vint8mf4_t*)(in + 1);
+  vfloat32m1_t v2;
+  *(vint8mf4_t*)(out + 1) = v1;
+  *(vfloat32m1_t*)(out + 2) = v2;
+}
+
+void f4 (void * restrict in, void * restrict out)
+{
+  vint8mf4_t v1 = *(vint8mf4_t*)(in + 1);
+  vfloat64m2_t v2;
+  *(vint8mf4_t*)(out + 1) = v1;
+  *(vfloat64m2_t*)(out + 2) = v2;
+}
+
+void f5 (void * restrict in, void * restrict out)
+{
+  vint8mf2_t v1 = *(vint8mf2_t*)(in + 1);
+  vfloat32m2_t v2;
+  *(vint8mf2_t*)(out + 1) = v1;
+  *(vfloat32m2_t*)(out + 2) = v2;
+}
+
+void f6 (void * restrict in, void * restrict out)
+{
+  vint8mf2_t v1 = *(vint8mf2_t*)(in + 1);
+  vfloat64m4_t v2;
+  *(vint8mf2_t*)(out + 1) = v1;
+  *(vfloat64m4_t*)(out + 2) = v2;
+}
+
+void f7 (void * restrict in, void * restrict out)
+{
+  vint8m1_t v1 = *(vint8m1_t*)(in + 1);
+  vfloat32m4_t v2;
+  *(vint8m1_t*)(out + 1) = v1;
+  *(vfloat32m4_t*)(out + 2) = v2;
+}
+
+void f8 (void * restrict in, void * restrict out)
+{
+  vint8m1_t v1 = *(vint8m1_t*)(in + 1);
+  vfloat64m8_t v2;
+  *(vint8m1_t*)(out + 1) = v1;
+  *(vfloat64m8_t*)(out + 2) = v2;
+}
+
+void f9 (void * restrict in, void * restrict out)
+{
+  vint8m2_t v1 = *(vint8m2_t*)(in + 1);
+  vfloat32m8_t v2;
+  *(vint8m2_t*)(out + 1) = v1;
+  *(vfloat32m8_t*)(out + 2) = v2;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli} 9 { target { no-opts "-O0" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c
new file mode 100644
index 0000000..ba4b5ef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c
@@ -0,0 +1,89 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f1 (void * restrict in, void * restrict out)
+{
+  vint16mf4_t v1 = *(vint16mf4_t*)(in + 1);
+  vfloat32mf2_t v2;
+  *(vint16mf4_t*)(out + 1) = v1;
+  *(vfloat32mf2_t*)(out + 2) = v2;
+}
+
+void f2 (void * restrict in, void * restrict out)
+{
+  vint16mf4_t v1 = *(vint16mf4_t*)(in + 1);
+  vfloat64m1_t v2;
+  *(vint16mf4_t*)(out + 1) = v1;
+  *(vfloat64m1_t*)(out + 2) = v2;
+}
+
+void f3 (void * restrict in, void * restrict out)
+{
+  vint16mf2_t v1 = *(vint16mf2_t*)(in + 1);
+  vfloat32m1_t v2;
+  *(vint16mf2_t*)(out + 1) = v1;
+  *(vfloat32m1_t*)(out + 2) = v2;
+}
+
+void f4 (void * restrict in, void * restrict out)
+{
+  vint16mf2_t v1 = *(vint16mf2_t*)(in + 1);
+  vfloat64m2_t v2;
+  *(vint16mf2_t*)(out + 1) = v1;
+  *(vfloat64m2_t*)(out + 2) = v2;
+}
+
+void f5 (void * restrict in, void * restrict out)
+{
+  vint16m1_t v1 = *(vint16m1_t*)(in + 1);
+  vfloat32m2_t v2;
+  *(vint16m1_t*)(out + 1) = v1;
+  *(vfloat32m2_t*)(out + 2) = v2;
+}
+
+void f6 (void * restrict in, void * restrict out)
+{
+  vint16m1_t v1 = *(vint16m1_t*)(in + 1);
+  vfloat64m4_t v2;
+  *(vint16m1_t*)(out + 1) = v1;
+  *(vfloat64m4_t*)(out + 2) = v2;
+}
+
+void f7 (void * restrict in, void * restrict out)
+{
+  vint16m2_t v1 = *(vint16m2_t*)(in + 1);
+  vfloat32m4_t v2;
+  *(vint16m2_t*)(out + 1) = v1;
+  *(vfloat32m4_t*)(out + 2) = v2;
+}
+
+void f8 (void * restrict in, void * restrict out)
+{
+  vint16m2_t v1 = *(vint16m2_t*)(in + 1);
+  vfloat64m8_t v2;
+  *(vint16m2_t*)(out + 1) = v1;
+  *(vfloat64m8_t*)(out + 2) = v2;
+}
+
+void f9 (void * restrict in, void * restrict out)
+{
+  vint16m4_t v1 = *(vint16m4_t*)(in + 1);
+  vfloat32m8_t v2;
+  *(vint16m4_t*)(out + 1) = v1;
+  *(vfloat32m8_t*)(out + 2) = v2;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli} 9 { target { no-opts "-O0" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c
new file mode 100644
index 0000000..5f04c19
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f3 (void * restrict in, void * restrict out)
+{
+  vint32mf2_t v1 = *(vint32mf2_t*)(in + 1);
+  vfloat64m1_t v2;
+  *(vint32mf2_t*)(out + 1) = v1;
+  *(vfloat64m1_t*)(out + 2) = v2;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c
new file mode 100644
index 0000000..8debc17
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c
@@ -0,0 +1,42 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f1 (void * restrict in, void * restrict out)
+{
+  vfloat32mf2_t v1 = *(vfloat32mf2_t*)(in + 1);
+  vint8mf8_t v2;
+  *(vfloat32mf2_t*)(out + 1) = v1;
+  *(vint8mf8_t*)(out + 2) = v2;
+}
+
+void f2 (void * restrict in, void * restrict out)
+{
+  vfloat32mf2_t v1 = *(vfloat32mf2_t*)(in + 1);
+  vint16mf4_t v2;
+  *(vfloat32mf2_t*)(out + 1) = v1;
+  *(vint16mf4_t*)(out + 2) = v2;
+}
+
+void f3 (void * restrict in, void * restrict out)
+{
+  vfloat32mf2_t v1 = *(vfloat32mf2_t*)(in + 1);
+  vint64m1_t v2;
+  *(vfloat32mf2_t*)(out + 1) = v1;
+  *(vint64m1_t*)(out + 2) = v2;
+}
+
+void f4 (void * restrict in, void * restrict out)
+{
+  vfloat32mf2_t v1 = *(vfloat32mf2_t*)(in + 1);
+  vfloat64m1_t v2;
+  *(vfloat32mf2_t*)(out + 1) = v1;
+  *(vfloat64m1_t*)(out + 2) = v2;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli} 4 { target { no-opts "-O0" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c
new file mode 100644
index 0000000..c8913d8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c
@@ -0,0 +1,147 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f1 (void * restrict in, void * restrict out)
+{
+  vbool64_t v1 = *(vbool64_t*)(in + 1);
+  vint16mf4_t v2;
+  *(vbool64_t*)(out + 1) = v1;
+  *(vint16mf4_t*)(out + 2) = v2;
+}
+
+void f2 (void * restrict in, void * restrict out)
+{
+  vbool64_t v1 = *(vbool64_t*)(in + 1);
+  vint32mf2_t v2;
+  *(vbool64_t*)(out + 1) = v1;
+  *(vint32mf2_t*)(out + 2) = v2;
+}
+
+void f3 (void * restrict in, void * restrict out)
+{
+  vbool64_t v1 = *(vbool64_t*)(in + 1);
+  vint64m1_t v2;
+  *(vbool64_t*)(out + 1) = v1;
+  *(vint64m1_t*)(out + 2) = v2;
+}
+
+void f4 (void * restrict in, void * restrict out)
+{
+  vbool32_t v1 = *(vbool32_t*)(in + 1);
+  vint16mf2_t v2;
+  *(vbool32_t*)(out + 1) = v1;
+  *(vint16mf2_t*)(out + 2) = v2;
+}
+
+void f5 (void * restrict in, void * restrict out)
+{
+  vbool32_t v1 = *(vbool32_t*)(in + 1);
+  vint32m1_t v2;
+  *(vbool32_t*)(out + 1) = v1;
+  *(vint32m1_t*)(out + 2) = v2;
+}
+
+void f6 (void * restrict in, void * restrict out)
+{
+  vbool32_t v1 = *(vbool32_t*)(in + 1);
+  vint64m2_t v2;
+  *(vbool32_t*)(out + 1) = v1;
+  *(vint64m2_t*)(out + 2) = v2;
+}
+
+void f7 (void * restrict in, void * restrict out)
+{
+  vbool16_t v1 = *(vbool16_t*)(in + 1);
+  vint16m1_t v2;
+  *(vbool16_t*)(out + 1) = v1;
+  *(vint16m1_t*)(out + 2) = v2;
+}
+
+void f8 (void * restrict in, void * restrict out)
+{
+  vbool16_t v1 = *(vbool16_t*)(in + 1);
+  vint32m2_t v2;
+  *(vbool16_t*)(out + 1) = v1;
+  *(vint32m2_t*)(out + 2) = v2;
+}
+
+void f9 (void * restrict in, void * restrict out)
+{
+  vbool16_t v1 = *(vbool16_t*)(in + 1);
+  vint64m4_t v2;
+  *(vbool16_t*)(out + 1) = v1;
+  *(vint64m4_t*)(out + 2) = v2;
+}
+
+void f10 (void * restrict in, void * restrict out)
+{
+  vbool8_t v1 = *(vbool8_t*)(in + 1);
+  vint16m2_t v2;
+  *(vbool8_t*)(out + 1) = v1;
+  *(vint16m2_t*)(out + 2) = v2;
+}
+
+void f11 (void * restrict in, void * restrict out)
+{
+  vbool8_t v1 = *(vbool8_t*)(in + 1);
+  vint32m4_t v2;
+  *(vbool8_t*)(out + 1) = v1;
+  *(vint32m4_t*)(out + 2) = v2;
+}
+
+void f12 (void * restrict in, void * restrict out)
+{
+  vbool8_t v1 = *(vbool8_t*)(in + 1);
+  vint64m8_t v2;
+  *(vbool8_t*)(out + 1) = v1;
+  *(vint64m8_t*)(out + 2) = v2;
+}
+
+void f13 (void * restrict in, void * restrict out)
+{
+  vbool4_t v1 = *(vbool4_t*)(in + 1);
+  vint16m4_t v2;
+  *(vbool4_t*)(out + 1) = v1;
+  *(vint16m4_t*)(out + 2) = v2;
+}
+
+void f14 (void * restrict in, void * restrict out)
+{
+  vbool4_t v1 = *(vbool4_t*)(in + 1);
+  vint32m8_t v2;
+  *(vbool4_t*)(out + 1) = v1;
+  *(vint32m8_t*)(out + 2) = v2;
+}
+
+void f15 (void * restrict in, void * restrict out)
+{
+  vbool2_t v1 = *(vbool2_t*)(in + 1);
+  vint16m8_t v2;
+  *(vbool2_t*)(out + 1) = v1;
+  *(vint16m8_t*)(out + 2) = v2;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli} 15 { target { no-opts "-O0" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c
new file mode 100644
index 0000000..edb9421
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void foo7 (void * restrict in, void * restrict out)
+{
+  vbool1_t v1 = *(vbool1_t*)(in + 1);
+  vbool2_t v2 = *(vbool2_t*)(in + 2);
+  vbool4_t v3 = *(vbool4_t*)(in + 3);
+  vbool8_t v4 = *(vbool8_t*)(in + 4);
+  vbool16_t v5 = *(vbool16_t*)(in + 5);
+  vbool32_t v6 = *(vbool32_t*)(in + 6);
+  vbool64_t v7 = *(vbool64_t*)(in + 7);
+  *(vbool1_t*)(out + 1) = v1;
+  *(vbool2_t*)(out + 2) = v2;
+  *(vbool4_t*)(out + 3) = v3;
+  *(vbool8_t*)(out + 4) = v4;
+  *(vbool16_t*)(out + 5) = v5;
+  *(vbool32_t*)(out + 6) = v6;
+  *(vbool64_t*)(out + 7) = v7;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" } } } } */
+/* { dg-final { scan-assembler-times {vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 7 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" } } } } */
+/* { dg-final { scan-assembler-times {vsm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 7 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c
new file mode 100644
index 0000000..e547b94
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out)
+{
+  vint8mf8_t v1 = *(vint8mf8_t*)(in + 1);
+  vint16mf4_t v2 = *(vint16mf4_t*)(in + 2);
+  vint32mf2_t v3 = *(vint32mf2_t*)(in + 3);
+  vfloat32mf2_t v4 = *(vfloat32mf2_t*)(in + 4);
+  
+  vint8mf4_t v5 = *(vint8mf4_t*)(in + 5);
+  vint16mf2_t v6 = *(vint16mf2_t*)(in + 6);
+  
+  vint8mf2_t v7 = *(vint8mf2_t*)(in + 7);
+  
+  *(vint8mf8_t*)(out + 1) = v1;
+  *(vint16mf4_t*)(out + 2) = v2;
+  *(vint32mf2_t*)(out + 3) = v3;
+  *(vfloat32mf2_t*)(out + 4) = v4;
+  
+  *(vint8mf4_t*)(out + 5) = v5;
+  *(vint16mf2_t*)(out + 6) = v6;
+  
+  *(vint8mf2_t*)(out + 7) = v7;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c
new file mode 100644
index 0000000..819e582
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c
@@ -0,0 +1,105 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out)
+{
+  vint8mf8_t v1 = *(vint8mf8_t*)(in + 1);
+  vint16mf4_t v2;
+  *(vint8mf8_t*)(out + 1) = v1;
+  *(vint16mf4_t*)(out + 2) = v2;
+  
+  vint8mf8_t v3 = *(vint8mf8_t*)(in + 3);
+  vint32mf2_t v4;
+  *(vint8mf8_t*)(out + 3) = v3;
+  *(vint32mf2_t*)(out + 4) = v4;
+  
+  vint8mf8_t v5 = *(vint8mf8_t*)(in + 5);
+  vint64m1_t v6;
+  *(vint8mf8_t*)(out + 5) = v5;
+  *(vint64m1_t*)(out + 6) = v6;
+  
+  vint8mf4_t v7 = *(vint8mf4_t*)(in + 7);
+  vint16mf2_t v8;
+  *(vint8mf4_t*)(out + 7) = v7;
+  *(vint16mf2_t*)(out + 8) = v8;
+  
+  vint8mf4_t v9 = *(vint8mf4_t*)(in + 9);
+  vint32m1_t v10;
+  *(vint8mf4_t*)(out + 9) = v9;
+  *(vint32m1_t*)(out + 10) = v10;
+  
+  vint8mf4_t v11 = *(vint8mf4_t*)(in + 11);
+  vint64m2_t v12;
+  *(vint8mf4_t*)(out + 11) = v11;
+  *(vint64m2_t*)(out + 12) = v12;
+  
+  vint8mf2_t v13 = *(vint8mf2_t*)(in + 13);
+  vint16m1_t v14;
+  *(vint8mf2_t*)(out + 13) = v13;
+  *(vint16m1_t*)(out + 14) = v14;
+  
+  vint8mf2_t v15 = *(vint8mf2_t*)(in + 15);
+  vint32m2_t v16;
+  *(vint8mf2_t*)(out + 15) = v15;
+  *(vint32m2_t*)(out + 16) = v16;
+  
+  vint8mf2_t v17 = *(vint8mf2_t*)(in + 17);
+  vint64m4_t v18;
+  *(vint8mf2_t*)(out + 17) = v17;
+  *(vint64m4_t*)(out + 18) = v18;
+  
+  vint8m1_t v19 = *(vint8m1_t*)(in + 19);
+  vint16m2_t v20;
+  *(vint8m1_t*)(out + 19) = v19;
+  *(vint16m2_t*)(out + 20) = v20;
+  
+  vint8m1_t v21 = *(vint8m1_t*)(in + 20);
+  vint32m4_t v22;
+  *(vint8m1_t*)(out + 20) = v21;
+  *(vint32m4_t*)(out + 21) = v22;
+  
+  vint8m1_t v23 = *(vint8m1_t*)(in + 23);
+  vint64m8_t v24;
+  *(vint8m1_t*)(out + 21) = v23;
+  *(vint64m8_t*)(out + 22) = v24;
+  
+  vint8m2_t v25 = *(vint8m2_t*)(in + 25);
+  vint16m4_t v26;
+  *(vint8m2_t*)(out + 25) = v25;
+  *(vint16m4_t*)(out + 26) = v26;
+  
+  vint8m2_t v27 = *(vint8m2_t*)(in + 27);
+  vint32m8_t v28;
+  *(vint8m2_t*)(out + 27) = v27;
+  *(vint32m8_t*)(out + 28) = v28;
+  
+  vint8m4_t v29 = *(vint8m4_t*)(in + 29);
+  vint16m8_t v30;
+  *(vint8m4_t*)(out + 29) = v29;
+  *(vint16m8_t*)(out + 30) = v30;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-O2" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-O2" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-O2" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-O2" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-O2" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e64,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-O2" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-O2" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e32,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-O2" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e64,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-O2" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-O2" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e32,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-O2" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e64,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-O2" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-O2" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e32,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-O2" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-O2" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli} 15 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-O2" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c
new file mode 100644
index 0000000..5ee37e9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c
@@ -0,0 +1,70 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+/* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */
+
+#include "riscv_vector.h"
+
+void foo1 (void * restrict in, void * restrict out)
+{
+  vint8mf8_t v1 = *(vint8mf8_t*)(in + 1);
+  vint8mf8_t v2 = *(vint8mf8_t*)(in + 2);
+  vint8mf8_t v3 = *(vint8mf8_t*)(in + 3);
+  vint8mf8_t v4 = *(vint8mf8_t*)(in + 4);
+  vint8mf8_t v5 = *(vint8mf8_t*)(in + 5);
+  vint8mf8_t v6 = *(vint8mf8_t*)(in + 6);
+  vint8mf8_t v7 = *(vint8mf8_t*)(in + 7);
+  vint8mf8_t v8 = *(vint8mf8_t*)(in + 8);
+  *(vint8mf8_t*)(out + 1) = v1;
+  *(vint8mf8_t*)(out + 2) = v2;
+  *(vint8mf8_t*)(out + 3) = v3;
+  *(vint8mf8_t*)(out + 4) = v4;
+  *(vint8mf8_t*)(out + 5) = v5;
+  *(vint8mf8_t*)(out + 6) = v6;
+  *(vint8mf8_t*)(out + 7) = v7;
+  *(vint8mf8_t*)(out + 8) = v8;
+}
+
+void foo2 (void * restrict in, void * restrict out)
+{
+  vint8mf4_t v1 = *(vint8mf4_t*)(in + 1);
+  vint8mf4_t v2 = *(vint8mf4_t*)(in + 2);
+  vint8mf4_t v3 = *(vint8mf4_t*)(in + 3);
+  vint8mf4_t v4 = *(vint8mf4_t*)(in + 4);
+  vint8mf4_t v5 = *(vint8mf4_t*)(in + 5);
+  vint8mf4_t v6 = *(vint8mf4_t*)(in + 6);
+  vint8mf4_t v7 = *(vint8mf4_t*)(in + 7);
+  vint8mf4_t v8 = *(vint8mf4_t*)(in + 8);
+  *(vint8mf4_t*)(out + 1) = v1;
+  *(vint8mf4_t*)(out + 2) = v2;
+  *(vint8mf4_t*)(out + 3) = v3;
+  *(vint8mf4_t*)(out + 4) = v4;
+  *(vint8mf4_t*)(out + 5) = v5;
+  *(vint8mf4_t*)(out + 6) = v6;
+  *(vint8mf4_t*)(out + 7) = v7;
+  *(vint8mf4_t*)(out + 8) = v8;
+}
+
+void foo3 (void * restrict in, void * restrict out)
+{
+  vint8mf2_t v1 = *(vint8mf2_t*)(in + 1);
+  vint8mf2_t v2 = *(vint8mf2_t*)(in + 2);
+  vint8mf2_t v3 = *(vint8mf2_t*)(in + 3);
+  vint8mf2_t v4 = *(vint8mf2_t*)(in + 4);
+  vint8mf2_t v5 = *(vint8mf2_t*)(in + 5);
+  vint8mf2_t v6 = *(vint8mf2_t*)(in + 6);
+  vint8mf2_t v7 = *(vint8mf2_t*)(in + 7);
+  vint8mf2_t v8 = *(vint8mf2_t*)(in + 8);
+  *(vint8mf2_t*)(out + 1) = v1;
+  *(vint8mf2_t*)(out + 2) = v2;
+  *(vint8mf2_t*)(out + 3) = v3;
+  *(vint8mf2_t*)(out + 4) = v4;
+  *(vint8mf2_t*)(out + 5) = v5;
+  *(vint8mf2_t*)(out + 6) = v6;
+  *(vint8mf2_t*)(out + 7) = v7;
+  *(vint8mf2_t*)(out + 8) = v8;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c
new file mode 100644
index 0000000..ed38627
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c
@@ -0,0 +1,70 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+/* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */
+
+#include "riscv_vector.h"
+
+void foo1 (void * restrict in, void * restrict out)
+{
+  vuint8mf8_t v1 = *(vuint8mf8_t*)(in + 1);
+  vuint8mf8_t v2 = *(vuint8mf8_t*)(in + 2);
+  vuint8mf8_t v3 = *(vuint8mf8_t*)(in + 3);
+  vuint8mf8_t v4 = *(vuint8mf8_t*)(in + 4);
+  vuint8mf8_t v5 = *(vuint8mf8_t*)(in + 5);
+  vuint8mf8_t v6 = *(vuint8mf8_t*)(in + 6);
+  vuint8mf8_t v7 = *(vuint8mf8_t*)(in + 7);
+  vuint8mf8_t v8 = *(vuint8mf8_t*)(in + 8);
+  *(vuint8mf8_t*)(out + 1) = v1;
+  *(vuint8mf8_t*)(out + 2) = v2;
+  *(vuint8mf8_t*)(out + 3) = v3;
+  *(vuint8mf8_t*)(out + 4) = v4;
+  *(vuint8mf8_t*)(out + 5) = v5;
+  *(vuint8mf8_t*)(out + 6) = v6;
+  *(vuint8mf8_t*)(out + 7) = v7;
+  *(vuint8mf8_t*)(out + 8) = v8;
+}
+
+void foo2 (void * restrict in, void * restrict out)
+{
+  vuint8mf4_t v1 = *(vuint8mf4_t*)(in + 1);
+  vuint8mf4_t v2 = *(vuint8mf4_t*)(in + 2);
+  vuint8mf4_t v3 = *(vuint8mf4_t*)(in + 3);
+  vuint8mf4_t v4 = *(vuint8mf4_t*)(in + 4);
+  vuint8mf4_t v5 = *(vuint8mf4_t*)(in + 5);
+  vuint8mf4_t v6 = *(vuint8mf4_t*)(in + 6);
+  vuint8mf4_t v7 = *(vuint8mf4_t*)(in + 7);
+  vuint8mf4_t v8 = *(vuint8mf4_t*)(in + 8);
+  *(vuint8mf4_t*)(out + 1) = v1;
+  *(vuint8mf4_t*)(out + 2) = v2;
+  *(vuint8mf4_t*)(out + 3) = v3;
+  *(vuint8mf4_t*)(out + 4) = v4;
+  *(vuint8mf4_t*)(out + 5) = v5;
+  *(vuint8mf4_t*)(out + 6) = v6;
+  *(vuint8mf4_t*)(out + 7) = v7;
+  *(vuint8mf4_t*)(out + 8) = v8;
+}
+
+void foo3 (void * restrict in, void * restrict out)
+{
+  vuint8mf2_t v1 = *(vuint8mf2_t*)(in + 1);
+  vuint8mf2_t v2 = *(vuint8mf2_t*)(in + 2);
+  vuint8mf2_t v3 = *(vuint8mf2_t*)(in + 3);
+  vuint8mf2_t v4 = *(vuint8mf2_t*)(in + 4);
+  vuint8mf2_t v5 = *(vuint8mf2_t*)(in + 5);
+  vuint8mf2_t v6 = *(vuint8mf2_t*)(in + 6);
+  vuint8mf2_t v7 = *(vuint8mf2_t*)(in + 7);
+  vuint8mf2_t v8 = *(vuint8mf2_t*)(in + 8);
+  *(vuint8mf2_t*)(out + 1) = v1;
+  *(vuint8mf2_t*)(out + 2) = v2;
+  *(vuint8mf2_t*)(out + 3) = v3;
+  *(vuint8mf2_t*)(out + 4) = v4;
+  *(vuint8mf2_t*)(out + 5) = v5;
+  *(vuint8mf2_t*)(out + 6) = v6;
+  *(vuint8mf2_t*)(out + 7) = v7;
+  *(vuint8mf2_t*)(out + 8) = v8;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c
new file mode 100644
index 0000000..d8f1a0b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c
@@ -0,0 +1,49 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+/* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */
+
+#include "riscv_vector.h"
+
+void foo2 (void * restrict in, void * restrict out)
+{
+  vint16mf4_t v1 = *(vint16mf4_t*)(in + 1);
+  vint16mf4_t v2 = *(vint16mf4_t*)(in + 2);
+  vint16mf4_t v3 = *(vint16mf4_t*)(in + 3);
+  vint16mf4_t v4 = *(vint16mf4_t*)(in + 4);
+  vint16mf4_t v5 = *(vint16mf4_t*)(in + 5);
+  vint16mf4_t v6 = *(vint16mf4_t*)(in + 6);
+  vint16mf4_t v7 = *(vint16mf4_t*)(in + 7);
+  vint16mf4_t v8 = *(vint16mf4_t*)(in + 8);
+  *(vint16mf4_t*)(out + 1) = v1;
+  *(vint16mf4_t*)(out + 2) = v2;
+  *(vint16mf4_t*)(out + 3) = v3;
+  *(vint16mf4_t*)(out + 4) = v4;
+  *(vint16mf4_t*)(out + 5) = v5;
+  *(vint16mf4_t*)(out + 6) = v6;
+  *(vint16mf4_t*)(out + 7) = v7;
+  *(vint16mf4_t*)(out + 8) = v8;
+}
+
+void foo3 (void * restrict in, void * restrict out)
+{
+  vint16mf2_t v1 = *(vint16mf2_t*)(in + 1);
+  vint16mf2_t v2 = *(vint16mf2_t*)(in + 2);
+  vint16mf2_t v3 = *(vint16mf2_t*)(in + 3);
+  vint16mf2_t v4 = *(vint16mf2_t*)(in + 4);
+  vint16mf2_t v5 = *(vint16mf2_t*)(in + 5);
+  vint16mf2_t v6 = *(vint16mf2_t*)(in + 6);
+  vint16mf2_t v7 = *(vint16mf2_t*)(in + 7);
+  vint16mf2_t v8 = *(vint16mf2_t*)(in + 8);
+  *(vint16mf2_t*)(out + 1) = v1;
+  *(vint16mf2_t*)(out + 2) = v2;
+  *(vint16mf2_t*)(out + 3) = v3;
+  *(vint16mf2_t*)(out + 4) = v4;
+  *(vint16mf2_t*)(out + 5) = v5;
+  *(vint16mf2_t*)(out + 6) = v6;
+  *(vint16mf2_t*)(out + 7) = v7;
+  *(vint16mf2_t*)(out + 8) = v8;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c
new file mode 100644
index 0000000..293c818
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c
@@ -0,0 +1,49 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+/* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */
+
+#include "riscv_vector.h"
+
+void foo2 (void * restrict in, void * restrict out)
+{
+  vuint16mf4_t v1 = *(vuint16mf4_t*)(in + 1);
+  vuint16mf4_t v2 = *(vuint16mf4_t*)(in + 2);
+  vuint16mf4_t v3 = *(vuint16mf4_t*)(in + 3);
+  vuint16mf4_t v4 = *(vuint16mf4_t*)(in + 4);
+  vuint16mf4_t v5 = *(vuint16mf4_t*)(in + 5);
+  vuint16mf4_t v6 = *(vuint16mf4_t*)(in + 6);
+  vuint16mf4_t v7 = *(vuint16mf4_t*)(in + 7);
+  vuint16mf4_t v8 = *(vuint16mf4_t*)(in + 8);
+  *(vuint16mf4_t*)(out + 1) = v1;
+  *(vuint16mf4_t*)(out + 2) = v2;
+  *(vuint16mf4_t*)(out + 3) = v3;
+  *(vuint16mf4_t*)(out + 4) = v4;
+  *(vuint16mf4_t*)(out + 5) = v5;
+  *(vuint16mf4_t*)(out + 6) = v6;
+  *(vuint16mf4_t*)(out + 7) = v7;
+  *(vuint16mf4_t*)(out + 8) = v8;
+}
+
+void foo3 (void * restrict in, void * restrict out)
+{
+  vuint16mf2_t v1 = *(vuint16mf2_t*)(in + 1);
+  vuint16mf2_t v2 = *(vuint16mf2_t*)(in + 2);
+  vuint16mf2_t v3 = *(vuint16mf2_t*)(in + 3);
+  vuint16mf2_t v4 = *(vuint16mf2_t*)(in + 4);
+  vuint16mf2_t v5 = *(vuint16mf2_t*)(in + 5);
+  vuint16mf2_t v6 = *(vuint16mf2_t*)(in + 6);
+  vuint16mf2_t v7 = *(vuint16mf2_t*)(in + 7);
+  vuint16mf2_t v8 = *(vuint16mf2_t*)(in + 8);
+  *(vuint16mf2_t*)(out + 1) = v1;
+  *(vuint16mf2_t*)(out + 2) = v2;
+  *(vuint16mf2_t*)(out + 3) = v3;
+  *(vuint16mf2_t*)(out + 4) = v4;
+  *(vuint16mf2_t*)(out + 5) = v5;
+  *(vuint16mf2_t*)(out + 6) = v6;
+  *(vuint16mf2_t*)(out + 7) = v7;
+  *(vuint16mf2_t*)(out + 8) = v8;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c
new file mode 100644
index 0000000..b047370
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+/* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */
+
+#include "riscv_vector.h"
+
+void foo3 (void * restrict in, void * restrict out)
+{
+  vint32mf2_t v1 = *(vint32mf2_t*)(in + 1);
+  vint32mf2_t v2 = *(vint32mf2_t*)(in + 2);
+  vint32mf2_t v3 = *(vint32mf2_t*)(in + 3);
+  vint32mf2_t v4 = *(vint32mf2_t*)(in + 4);
+  vint32mf2_t v5 = *(vint32mf2_t*)(in + 5);
+  vint32mf2_t v6 = *(vint32mf2_t*)(in + 6);
+  vint32mf2_t v7 = *(vint32mf2_t*)(in + 7);
+  vint32mf2_t v8 = *(vint32mf2_t*)(in + 8);
+  *(vint32mf2_t*)(out + 1) = v1;
+  *(vint32mf2_t*)(out + 2) = v2;
+  *(vint32mf2_t*)(out + 3) = v3;
+  *(vint32mf2_t*)(out + 4) = v4;
+  *(vint32mf2_t*)(out + 5) = v5;
+  *(vint32mf2_t*)(out + 6) = v6;
+  *(vint32mf2_t*)(out + 7) = v7;
+  *(vint32mf2_t*)(out + 8) = v8;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c
new file mode 100644
index 0000000..04d1930
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+/* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */
+
+#include "riscv_vector.h"
+
+void foo3 (void * restrict in, void * restrict out)
+{
+  vuint32mf2_t v1 = *(vuint32mf2_t*)(in + 1);
+  vuint32mf2_t v2 = *(vuint32mf2_t*)(in + 2);
+  vuint32mf2_t v3 = *(vuint32mf2_t*)(in + 3);
+  vuint32mf2_t v4 = *(vuint32mf2_t*)(in + 4);
+  vuint32mf2_t v5 = *(vuint32mf2_t*)(in + 5);
+  vuint32mf2_t v6 = *(vuint32mf2_t*)(in + 6);
+  vuint32mf2_t v7 = *(vuint32mf2_t*)(in + 7);
+  vuint32mf2_t v8 = *(vuint32mf2_t*)(in + 8);
+  *(vuint32mf2_t*)(out + 1) = v1;
+  *(vuint32mf2_t*)(out + 2) = v2;
+  *(vuint32mf2_t*)(out + 3) = v3;
+  *(vuint32mf2_t*)(out + 4) = v4;
+  *(vuint32mf2_t*)(out + 5) = v5;
+  *(vuint32mf2_t*)(out + 6) = v6;
+  *(vuint32mf2_t*)(out + 7) = v7;
+  *(vuint32mf2_t*)(out + 8) = v8;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c
new file mode 100644
index 0000000..abfbc1b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+/* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */
+
+#include "riscv_vector.h"
+
+void foo3 (void * restrict in, void * restrict out)
+{
+  vfloat32mf2_t v1 = *(vfloat32mf2_t*)(in + 1);
+  vfloat32mf2_t v2 = *(vfloat32mf2_t*)(in + 2);
+  vfloat32mf2_t v3 = *(vfloat32mf2_t*)(in + 3);
+  vfloat32mf2_t v4 = *(vfloat32mf2_t*)(in + 4);
+  vfloat32mf2_t v5 = *(vfloat32mf2_t*)(in + 5);
+  vfloat32mf2_t v6 = *(vfloat32mf2_t*)(in + 6);
+  vfloat32mf2_t v7 = *(vfloat32mf2_t*)(in + 7);
+  vfloat32mf2_t v8 = *(vfloat32mf2_t*)(in + 8);
+  *(vfloat32mf2_t*)(out + 1) = v1;
+  *(vfloat32mf2_t*)(out + 2) = v2;
+  *(vfloat32mf2_t*)(out + 3) = v3;
+  *(vfloat32mf2_t*)(out + 4) = v4;
+  *(vfloat32mf2_t*)(out + 5) = v5;
+  *(vfloat32mf2_t*)(out + 6) = v6;
+  *(vfloat32mf2_t*)(out + 7) = v7;
+  *(vfloat32mf2_t*)(out + 8) = v8;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c
new file mode 100644
index 0000000..6528c11
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c
@@ -0,0 +1,147 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f1 (void * restrict in, void * restrict out)
+{
+  vint8mf8_t v1 = *(vint8mf8_t*)(in + 1);
+  vint16mf4_t v2;
+  *(vint8mf8_t*)(out + 1) = v1;
+  *(vint16mf4_t*)(out + 2) = v2;
+}
+
+void f2 (void * restrict in, void * restrict out)
+{
+  vint8mf8_t v1 = *(vint8mf8_t*)(in + 1);
+  vint32mf2_t v2;
+  *(vint8mf8_t*)(out + 1) = v1;
+  *(vint32mf2_t*)(out + 2) = v2;
+}
+
+void f3 (void * restrict in, void * restrict out)
+{
+  vint8mf8_t v1 = *(vint8mf8_t*)(in + 1);
+  vint64m1_t v2;
+  *(vint8mf8_t*)(out + 1) = v1;
+  *(vint64m1_t*)(out + 2) = v2;
+}
+
+void f4 (void * restrict in, void * restrict out)
+{
+  vint8mf4_t v1 = *(vint8mf4_t*)(in + 1);
+  vint16mf2_t v2;
+  *(vint8mf4_t*)(out + 1) = v1;
+  *(vint16mf2_t*)(out + 2) = v2;
+}
+
+void f5 (void * restrict in, void * restrict out)
+{
+  vint8mf4_t v1 = *(vint8mf4_t*)(in + 1);
+  vint32m1_t v2;
+  *(vint8mf4_t*)(out + 1) = v1;
+  *(vint32m1_t*)(out + 2) = v2;
+}
+
+void f6 (void * restrict in, void * restrict out)
+{
+  vint8mf4_t v1 = *(vint8mf4_t*)(in + 1);
+  vint64m2_t v2;
+  *(vint8mf4_t*)(out + 1) = v1;
+  *(vint64m2_t*)(out + 2) = v2;
+}
+
+void f7 (void * restrict in, void * restrict out)
+{
+  vint8mf2_t v1 = *(vint8mf2_t*)(in + 1);
+  vint16m1_t v2;
+  *(vint8mf2_t*)(out + 1) = v1;
+  *(vint16m1_t*)(out + 2) = v2;
+}
+
+void f8 (void * restrict in, void * restrict out)
+{
+  vint8mf2_t v1 = *(vint8mf2_t*)(in + 1);
+  vint32m2_t v2;
+  *(vint8mf2_t*)(out + 1) = v1;
+  *(vint32m2_t*)(out + 2) = v2;
+}
+
+void f9 (void * restrict in, void * restrict out)
+{
+  vint8mf2_t v1 = *(vint8mf2_t*)(in + 1);
+  vint64m4_t v2;
+  *(vint8mf2_t*)(out + 1) = v1;
+  *(vint64m4_t*)(out + 2) = v2;
+}
+
+void f10 (void * restrict in, void * restrict out)
+{
+  vint8m1_t v1 = *(vint8m1_t*)(in + 1);
+  vint16m2_t v2;
+  *(vint8m1_t*)(out + 1) = v1;
+  *(vint16m2_t*)(out + 2) = v2;
+}
+
+void f11 (void * restrict in, void * restrict out)
+{
+  vint8m1_t v1 = *(vint8m1_t*)(in + 1);
+  vint32m4_t v2;
+  *(vint8m1_t*)(out + 1) = v1;
+  *(vint32m4_t*)(out + 2) = v2;
+}
+
+void f12 (void * restrict in, void * restrict out)
+{
+  vint8m1_t v1 = *(vint8m1_t*)(in + 1);
+  vint64m8_t v2;
+  *(vint8m1_t*)(out + 1) = v1;
+  *(vint64m8_t*)(out + 2) = v2;
+}
+
+void f13 (void * restrict in, void * restrict out)
+{
+  vint8m2_t v1 = *(vint8m2_t*)(in + 1);
+  vint16m4_t v2;
+  *(vint8m2_t*)(out + 1) = v1;
+  *(vint16m4_t*)(out + 2) = v2;
+}
+
+void f14 (void * restrict in, void * restrict out)
+{
+  vint8m2_t v1 = *(vint8m2_t*)(in + 1);
+  vint32m8_t v2;
+  *(vint8m2_t*)(out + 1) = v1;
+  *(vint32m8_t*)(out + 2) = v2;
+}
+
+void f15 (void * restrict in, void * restrict out)
+{
+  vint8m4_t v1 = *(vint8m4_t*)(in + 1);
+  vint16m8_t v2;
+  *(vint8m4_t*)(out + 1) = v1;
+  *(vint16m8_t*)(out + 2) = v2;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli} 15 { target { no-opts "-O0" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c
new file mode 100644
index 0000000..09f87d1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c
@@ -0,0 +1,86 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+
+#include "riscv_vector.h"
+
+/* Check vsetvl instruction is hoisted outside the loop, so it should
+   stay before label.  */
+
+void foo1 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vbool64_t v = *(vbool64_t*)(in + i);
+      *(vbool64_t*)(out + i) = v;
+    }
+}
+
+void foo2 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vbool32_t v = *(vbool32_t*)(in + i);
+      *(vbool32_t*)(out + i) = v;
+    }
+}
+
+void foo3 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vbool16_t v = *(vbool16_t*)(in + i);
+      *(vbool16_t*)(out + i) = v;
+    }
+}
+
+void foo4 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vbool8_t v = *(vbool8_t*)(in + i);
+      *(vbool8_t*)(out + i) = v;
+    }
+}
+
+void foo5 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vbool4_t v = *(vbool4_t*)(in + i);
+      *(vbool4_t*)(out + i) = v;
+    }
+}
+
+void foo6 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vbool2_t v = *(vbool2_t*)(in + i);
+      *(vbool2_t*)(out + i) = v;
+    }
+}
+
+void foo7 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vbool1_t v = *(vbool1_t*)(in + i);
+      *(vbool1_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c
new file mode 100644
index 0000000..48ac624
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c
@@ -0,0 +1,42 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* Check vsetvl instruction is hoisted outside the loop, so it should
+   stay before label.  */
+
+void foo1 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf8_t v = *(vint8mf8_t*)(in + i);
+      *(vint8mf8_t*)(out + i) = v;
+    }
+}
+
+void foo2 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf4_t v = *(vint8mf4_t*)(in + i);
+      *(vint8mf4_t*)(out + i) = v;
+    }
+}
+
+void foo3 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf2_t v = *(vint8mf2_t*)(in + i);
+      *(vint8mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c
new file mode 100644
index 0000000..4349280
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* Check vsetvl instruction is hoisted outside the loop, so it should
+   stay before label.  */
+
+void foo1 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vuint8mf8_t v = *(vuint8mf8_t*)(in + i);
+      *(vuint8mf8_t*)(out + i) = v;
+    }
+}
+
+void foo2 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vuint8mf4_t v = *(vuint8mf4_t*)(in + i);
+      *(vuint8mf4_t*)(out + i) = v;
+    }
+}
+
+void foo3 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vuint8mf2_t v = *(vuint8mf2_t*)(in + i);
+      *(vuint8mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c
new file mode 100644
index 0000000..08c06b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* Check vsetvl instruction is hoisted outside the loop, so it should
+   stay before label.  */
+
+void foo2 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vint16mf4_t v = *(vint16mf4_t*)(in + i);
+      *(vint16mf4_t*)(out + i) = v;
+    }
+}
+
+void foo3 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vint16mf2_t v = *(vint16mf2_t*)(in + i);
+      *(vint16mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c
new file mode 100644
index 0000000..d3c71a0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* Check vsetvl instruction is hoisted outside the loop, so it should
+   stay before label.  */
+
+void foo2 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vuint16mf4_t v = *(vuint16mf4_t*)(in + i);
+      *(vuint16mf4_t*)(out + i) = v;
+    }
+}
+
+void foo3 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vuint16mf2_t v = *(vuint16mf2_t*)(in + i);
+      *(vuint16mf2_t*)(out + i) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c
new file mode 100644
index 0000000..5986265
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* Check vsetvl instruction is hoisted outside the loop, so it should
+   stay before label.  */
+
+void foo2 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vint32mf2_t v = *(vint32mf2_t*)(in + i);
+      *(vint32mf2_t*)(out + i) = v;
+    }
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c
new file mode 100644
index 0000000..61728cf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* Check vsetvl instruction is hoisted outside the loop, so it should
+   stay before label.  */
+
+void foo2 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vuint32mf2_t v = *(vuint32mf2_t*)(in + i);
+      *(vuint32mf2_t*)(out + i) = v;
+    }
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c
new file mode 100644
index 0000000..82ce35b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+/* Check vsetvl instruction is hoisted outside the loop, so it should
+   stay before label.  */
+
+void foo2 (void * restrict in, void * restrict out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      vfloat32mf2_t v = *(vfloat32mf2_t*)(in + i);
+      *(vfloat32mf2_t*)(out + i) = v;
+    }
+}
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c
new file mode 100644
index 0000000..c8601a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int n)
+{
+  vint8mf8_t v1 = *(vint8mf8_t*)(in + 1);
+  vint16mf4_t v2 = *(vint16mf4_t*)(in + 2);
+  vint32mf2_t v3 = *(vint32mf2_t*)(in + 3);
+  vfloat32mf2_t v4 = *(vfloat32mf2_t*)(in + 4);
+  
+  *(vint8mf8_t*)(out + 1) = v1;
+  *(vint16mf4_t*)(out + 2) = v2;
+  *(vint32mf2_t*)(out + 3) = v3;
+  *(vfloat32mf2_t*)(out + 4) = v4;
+  
+  for (int i = 0; i < n; i++)
+    {
+      vint8mf8_t v = *(vint8mf8_t*)(in + i + 5);
+      *(vint8mf8_t*)(out + i + 5) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c
new file mode 100644
index 0000000..b68932a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c
@@ -0,0 +1,47 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void foo (int8_t * restrict in, int8_t * restrict out, int n, int cond)
+{
+  vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 10000);
+  *(vfloat32mf2_t*)(out + 10000) = v;
+
+  if (cond)
+    {
+      vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 30000);
+      *(vfloat32mf2_t*)(out + 30000) = v;
+    }
+  else
+    {
+      vint16mf2_t v = *(vint16mf2_t*)(in + 20000);
+      *(vint16mf2_t*)(out + 20000) = v;
+    }
+
+  for (int i = 0; i < n; i++)
+    {
+      vint32mf2_t v0 = *(vint32mf2_t*)(in + i + 100);
+      
+      vint16mf2_t v1 = *(vint16mf2_t*)(in + i + 200);
+      vint8mf2_t v2 = *(vint8mf2_t*)(in + i + 300);
+      vint8mf4_t v3 = *(vint8mf4_t*)(in + i + 400);
+      vint8mf8_t v4 = *(vint8mf8_t*)(in + i + 500);
+      vbool1_t v5 = *(vbool1_t*)(in + i + 600);
+
+      vint32mf2_t v6 = *(vint32mf2_t*)(in + i + 700);
+
+      *(vint32mf2_t*)(out + i + 100) = v0;
+      *(vint16mf2_t*)(out + i + 200) = v1;
+      *(vint8mf2_t*)(out + i + 300) = v2;
+      *(vint8mf4_t*)(out + i + 400) = v3;
+      *(vint8mf8_t*)(out + i + 500) = v4;
+      *(vbool1_t*)(out + i + 600) = v5;
+      *(vint32mf2_t*)(out + i + 700) = v6;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 9 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {\s*\.L[0-9]+:\s*vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]+} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c
new file mode 100644
index 0000000..a6530a2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void foo (int8_t * restrict in, int8_t * restrict out, int n, int cond1, int cond2)
+{
+  vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 10000);
+  *(vfloat32mf2_t*)(out + 10000) = v;
+
+  if (cond1)
+    {
+      vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 30000);
+      *(vfloat32mf2_t*)(out + 30000) = v;
+    }
+  else
+    {
+      vint8mf8_t v = *(vint8mf8_t*)(in + 20000);
+      *(vint8mf8_t*)(out + 20000) = v;
+    }
+
+  for (int i = 0; i < n; i++)
+    {
+      vint32mf2_t v0 = *(vint32mf2_t*)(in + i + 100);
+      
+      vint16mf2_t v1 = *(vint16mf2_t*)(in + i + 200);
+      vint8mf2_t v2 = *(vint8mf2_t*)(in + i + 300);
+      vint8mf4_t v3 = *(vint8mf4_t*)(in + i + 400);
+      vint8mf8_t v4 = *(vint8mf8_t*)(in + i + 500);
+      vbool1_t v5 = *(vbool1_t*)(in + i + 600);
+
+      vint32mf2_t v6 = *(vint32mf2_t*)(in + i + 700);
+
+      *(vint32mf2_t*)(out + i + 100) = v0;
+      *(vint16mf2_t*)(out + i + 200) = v1;
+      *(vint8mf2_t*)(out + i + 300) = v2;
+      *(vint8mf4_t*)(out + i + 400) = v3;
+      *(vint8mf8_t*)(out + i + 500) = v4;
+      *(vbool1_t*)(out + i + 600) = v5;
+      *(vint32mf2_t*)(out + i + 700) = v6;
+    }
+  
+  if (cond2)
+    {
+      vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 40000);
+      *(vfloat32mf2_t*)(out + 40000) = v;
+    }
+  else
+    {
+      vint16mf4_t v = *(vint16mf4_t*)(in + 30000);
+      *(vint16mf4_t*)(out + 30000) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 7 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c
new file mode 100644
index 0000000..eaf6992
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void foo (int8_t * restrict in, int8_t * restrict out, int n, int cond1, int cond2)
+{
+  vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 10000);
+  *(vfloat32mf2_t*)(out + 10000) = v;
+
+  if (cond1)
+    {
+      vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 30000);
+      *(vfloat32mf2_t*)(out + 30000) = v;
+    }
+  else
+    {
+      vint8mf2_t v = *(vint8mf2_t*)(in + 20000);
+      *(vint8mf2_t*)(out + 20000) = v;
+    }
+
+  for (int i = 0; i < n; i++)
+    {
+      vint32mf2_t v0 = *(vint32mf2_t*)(in + i + 100);
+      
+      vint16mf2_t v1 = *(vint16mf2_t*)(in + i + 200);
+      vint8mf2_t v2 = *(vint8mf2_t*)(in + i + 300);
+      vint8mf4_t v3 = *(vint8mf4_t*)(in + i + 400);
+      vint8mf8_t v4 = *(vint8mf8_t*)(in + i + 500);
+      vbool1_t v5 = *(vbool1_t*)(in + i + 600);
+
+      vint32mf2_t v6 = *(vint32mf2_t*)(in + i + 700);
+
+      *(vint32mf2_t*)(out + i + 100) = v0;
+      *(vint16mf2_t*)(out + i + 200) = v1;
+      *(vint8mf2_t*)(out + i + 300) = v2;
+      *(vint8mf4_t*)(out + i + 400) = v3;
+      *(vint8mf8_t*)(out + i + 500) = v4;
+      *(vbool1_t*)(out + i + 600) = v5;
+      *(vint32mf2_t*)(out + i + 700) = v6;
+    }
+  
+  if (cond2)
+    {
+      vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 40000);
+      *(vfloat32mf2_t*)(out + 40000) = v;
+    }
+  else
+    {
+      vint16mf4_t v = *(vint16mf4_t*)(in + 30000);
+      *(vint16mf4_t*)(out + 30000) = v;
+    }
+}
+/* { dg-final { scan-assembler-times {vsetvli} 9 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+j\s+\.L[0-9]+} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c
new file mode 100644
index 0000000..1f6ed17
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int n)
+{
+  vint8mf8_t v1;
+  vint16mf4_t v2;
+  
+  *(vint8mf8_t*)(out + 1) = v1;
+  *(vint16mf4_t*)(out + 2) = v2;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c
new file mode 100644
index 0000000..291916f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c
@@ -0,0 +1,39 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int32_t * a, int32_t * b, int n, int cond)
+{
+  for (int i = 0; i < n; i++) {
+    vint16mf4_t v;
+    *(vint16mf4_t*)(out + i + 700) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    a[i] = a[i] + b[i];
+  }
+  for (int i = 0; i < n; i++) {
+    a[i] = a[i] * b[i];
+  }
+  for (int i = 0; i < n; i++) {
+    a[i] = a[i] - b[i];
+  }
+  for (int i = 0; i < n; i++) {
+    vint32mf2_t v;
+    *(vint32mf2_t*)(out + i + 7000) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint64m1_t v;
+    *(vint64m1_t*)(out + i + 8000) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint8mf8_t v;
+    *(vint8mf8_t*)(out + i + 9000) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 4 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c
new file mode 100644
index 0000000..42930b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c
@@ -0,0 +1,52 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int32_t * a, int32_t * b, int n, int cond)
+{
+  for (int i = 0; i < n; i++) {
+    vint16mf4_t v;
+    *(vint16mf4_t*)(out + i + 700) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    a[i] = a[i] + b[i];
+  }
+  for (int i = 0; i < n; i++) {
+    a[i] = a[i] * b[i];
+  }
+  for (int i = 0; i < n; i++) {
+    a[i] = a[i] - b[i];
+  }
+  for (int i = 0; i < n; i++) {
+    vint32mf2_t v;
+    *(vint32mf2_t*)(out + i + 7000) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint16mf2_t v;
+    *(vint16mf2_t*)(out + i + 777) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint64m1_t v;
+    *(vint64m1_t*)(out + i + 8000) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat32mf2_t v;
+    *(vfloat32mf2_t*)(out + i + 7777) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vuint16mf2_t v;
+    *(vuint16mf2_t*)(out + i + 888) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint8mf8_t v;
+    *(vint8mf8_t*)(out + i + 9000) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0"  no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 7 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c
new file mode 100644
index 0000000..087d97c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c
@@ -0,0 +1,60 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int32_t * a, int32_t * b, int n, int cond)
+{
+  for (int i = 0; i < n; i++) {
+    vint16mf4_t v;
+    *(vint16mf4_t*)(out + i + 700) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    a[i] = a[i] + b[i];
+  }
+  for (int i = 0; i < n; i++) {
+    a[i] = a[i] * b[i];
+  }
+  for (int i = 0; i < n; i++) {
+    a[i] = a[i] - b[i];
+  }
+  for (int i = 0; i < n; i++) {
+    vint32mf2_t v;
+    *(vint32mf2_t*)(out + i + 7000) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint16mf2_t v;
+    *(vint16mf2_t*)(out + i + 777) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint64m1_t v;
+    *(vint64m1_t*)(out + i + 8000) = v;
+  }
+  if (cond == 0) {
+    vbool64_t v;
+    *(vbool64_t*)(out + 1234) = v;
+  } else {
+    vuint8mf8_t v;
+    *(vuint8mf8_t*)(out + 5432) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vfloat32mf2_t v;
+    *(vfloat32mf2_t*)(out + i + 7777) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vuint16mf2_t v;
+    *(vuint16mf2_t*)(out + i + 888) = v;
+  }
+  for (int i = 0; i < n; i++) {
+    vint8mf8_t v;
+    *(vint8mf8_t*)(out + i + 9000) = v;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0"  no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0"  no-opts "-funroll-loops" no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 10 { target { no-opts "-O0" no-opts "-O1" no-opts "-funroll-loops" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c
new file mode 100644
index 0000000..8bb6cbe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int n)
+{
+  vint8mf8_t v1 = *(vint8mf8_t*)(in + 1);
+  vint16mf4_t v2 = *(vint16mf4_t*)(in + 2);
+  vint32mf2_t v3 = *(vint32mf2_t*)(in + 3);
+  vfloat32mf2_t v4 = *(vfloat32mf2_t*)(in + 4);
+  
+  *(vint8mf8_t*)(out + 1) = v1;
+  *(vint16mf4_t*)(out + 2) = v2;
+  *(vint32mf2_t*)(out + 3) = v3;
+  *(vfloat32mf2_t*)(out + 4) = v4;
+  
+  for (int i = 0; i < n; i++)
+    {
+      vint16mf4_t v = *(vint16mf4_t*)(in + i + 5);
+      *(vint16mf4_t*)(out + i + 5) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-O1" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-Os" no-opts "-flto" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c
new file mode 100644
index 0000000..30c2e06
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int n)
+{
+  vint8mf8_t v1 = *(vint8mf8_t*)(in + 1);
+  vint16mf4_t v2 = *(vint16mf4_t*)(in + 2);
+  vint32mf2_t v3 = *(vint32mf2_t*)(in + 3);
+  vfloat32mf2_t v4 = *(vfloat32mf2_t*)(in + 4);
+  
+  *(vint8mf8_t*)(out + 1) = v1;
+  *(vint16mf4_t*)(out + 2) = v2;
+  *(vint32mf2_t*)(out + 3) = v3;
+  *(vfloat32mf2_t*)(out + 4) = v4;
+  
+  for (int i = 0; i < n; i++)
+    {
+      vint16mf2_t v = *(vint16mf2_t*)(in + i + 5);
+      *(vint16mf2_t*)(out + i + 5) = v;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-flto" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c
new file mode 100644
index 0000000..7258f3f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int n)
+{
+  vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 10000);
+  *(vfloat32mf2_t*)(out + 10000) = v;
+  for (int i = 0; i < n; i++)
+    {
+      vint16mf2_t v1 = *(vint16mf2_t*)(in + i + 1);
+      vint32mf2_t v2 = *(vint32mf2_t*)(in + i + 2);
+      *(vint16mf2_t*)(out + i + 1) = v1;
+      *(vint32mf2_t*)(out + i + 2) = v2;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-flto" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-flto" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c
new file mode 100644
index 0000000..7258f3f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int n)
+{
+  vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 10000);
+  *(vfloat32mf2_t*)(out + 10000) = v;
+  for (int i = 0; i < n; i++)
+    {
+      vint16mf2_t v1 = *(vint16mf2_t*)(in + i + 1);
+      vint32mf2_t v2 = *(vint32mf2_t*)(in + i + 2);
+      *(vint16mf2_t*)(out + i + 1) = v1;
+      *(vint32mf2_t*)(out + i + 2) = v2;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-flto" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-flto" no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c
new file mode 100644
index 0000000..3271659
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32" } */
+
+#include "riscv_vector.h"
+
+void foo (void * restrict in, void * restrict out, int n)
+{
+  vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 10000);
+  *(vfloat32mf2_t*)(out + 10000) = v;
+  for (int i = 0; i < n; i++)
+    {
+      vint32mf2_t v0 = *(vint32mf2_t*)(in + i + 100);
+      
+      vint16mf2_t v1 = *(vint16mf2_t*)(in + i + 200);
+      vint8mf2_t v2 = *(vint8mf2_t*)(in + i + 300);
+      vint8mf4_t v3 = *(vint8mf4_t*)(in + i + 400);
+      vint8mf8_t v4 = *(vint8mf8_t*)(in + i + 500);
+      vbool1_t v5 = *(vbool1_t*)(in + i + 600);
+
+      vint32mf2_t v6 = *(vint32mf2_t*)(in + i + 700);
+
+      *(vint32mf2_t*)(out + i + 100) = v0;
+      *(vint16mf2_t*)(out + i + 200) = v1;
+      *(vint8mf2_t*)(out + i + 300) = v2;
+      *(vint8mf4_t*)(out + i + 400) = v3;
+      *(vint8mf8_t*)(out + i + 500) = v4;
+      *(vbool1_t*)(out + i + 600) = v5;
+      *(vint32mf2_t*)(out + i + 700) = v6;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 7 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c
new file mode 100644
index 0000000..ea91f0e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c
@@ -0,0 +1,43 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void foo (int8_t * restrict in, int8_t * restrict out, int n)
+{
+  vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 10000);
+  *(vfloat32mf2_t*)(out + 10000) = v;
+
+  for (int i = 0 ; i < n * n; i++)
+    out[i] = out[i] + out[i];
+  
+  for (int i = 0 ; i < n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0 ; i < n * n * n * n; i++)
+    out[i] = out[i] * out[i];
+
+  for (int i = 0; i < n; i++)
+    {
+      vint32mf2_t v0 = *(vint32mf2_t*)(in + i + 100);
+      
+      vint16mf2_t v1 = *(vint16mf2_t*)(in + i + 200);
+      vint8mf2_t v2 = *(vint8mf2_t*)(in + i + 300);
+      vint8mf4_t v3 = *(vint8mf4_t*)(in + i + 400);
+      vint8mf8_t v4 = *(vint8mf8_t*)(in + i + 500);
+      vbool1_t v5 = *(vbool1_t*)(in + i + 600);
+
+      vint32mf2_t v6 = *(vint32mf2_t*)(in + i + 700);
+
+      *(vint32mf2_t*)(out + i + 100) = v0;
+      *(vint16mf2_t*)(out + i + 200) = v1;
+      *(vint8mf2_t*)(out + i + 300) = v2;
+      *(vint8mf4_t*)(out + i + 400) = v3;
+      *(vint8mf8_t*)(out + i + 500) = v4;
+      *(vbool1_t*)(out + i + 600) = v5;
+      *(vint32mf2_t*)(out + i + 700) = v6;
+    }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli} 7 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c
new file mode 100644
index 0000000..7537bfe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c
@@ -0,0 +1,45 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void foo (int8_t * restrict in, int8_t * restrict out, int n, int cond)
+{
+  vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 10000);
+  *(vfloat32mf2_t*)(out + 10000) = v;
+
+  if (cond)
+    {
+      vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 20000);
+      *(vfloat32mf2_t*)(out + 20000) = v;
+    }
+  else
+    {
+      vint16mf4_t v = *(vint16mf4_t*)(in + 20000);
+      *(vint16mf4_t*)(out + 20000) = v;
+    }
+
+  for (int i = 0; i < n; i++)
+    {
+      vint32mf2_t v0 = *(vint32mf2_t*)(in + i + 100);
+      
+      vint16mf2_t v1 = *(vint16mf2_t*)(in + i + 200);
+      vint8mf2_t v2 = *(vint8mf2_t*)(in + i + 300);
+      vint8mf4_t v3 = *(vint8mf4_t*)(in + i + 400);
+      vint8mf8_t v4 = *(vint8mf8_t*)(in + i + 500);
+      vbool1_t v5 = *(vbool1_t*)(in + i + 600);
+
+      vint32mf2_t v6 = *(vint32mf2_t*)(in + i + 700);
+
+      *(vint32mf2_t*)(out + i + 100) = v0;
+      *(vint16mf2_t*)(out + i + 200) = v1;
+      *(vint8mf2_t*)(out + i + 300) = v2;
+      *(vint8mf4_t*)(out + i + 400) = v3;
+      *(vint8mf8_t*)(out + i + 500) = v4;
+      *(vbool1_t*)(out + i + 600) = v5;
+      *(vint32mf2_t*)(out + i + 700) = v6;
+    }
+}
+/* { dg-final { scan-assembler-times {vsetvli} 7 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-not {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16\s*mf4,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c
new file mode 100644
index 0000000..7537bfe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c
@@ -0,0 +1,45 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void foo (int8_t * restrict in, int8_t * restrict out, int n, int cond)
+{
+  vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 10000);
+  *(vfloat32mf2_t*)(out + 10000) = v;
+
+  if (cond)
+    {
+      vfloat32mf2_t v = *(vfloat32mf2_t*)(in + 20000);
+      *(vfloat32mf2_t*)(out + 20000) = v;
+    }
+  else
+    {
+      vint16mf4_t v = *(vint16mf4_t*)(in + 20000);
+      *(vint16mf4_t*)(out + 20000) = v;
+    }
+
+  for (int i = 0; i < n; i++)
+    {
+      vint32mf2_t v0 = *(vint32mf2_t*)(in + i + 100);
+      
+      vint16mf2_t v1 = *(vint16mf2_t*)(in + i + 200);
+      vint8mf2_t v2 = *(vint8mf2_t*)(in + i + 300);
+      vint8mf4_t v3 = *(vint8mf4_t*)(in + i + 400);
+      vint8mf8_t v4 = *(vint8mf8_t*)(in + i + 500);
+      vbool1_t v5 = *(vbool1_t*)(in + i + 600);
+
+      vint32mf2_t v6 = *(vint32mf2_t*)(in + i + 700);
+
+      *(vint32mf2_t*)(out + i + 100) = v0;
+      *(vint16mf2_t*)(out + i + 200) = v1;
+      *(vint8mf2_t*)(out + i + 300) = v2;
+      *(vint8mf4_t*)(out + i + 400) = v3;
+      *(vint8mf8_t*)(out + i + 500) = v4;
+      *(vbool1_t*)(out + i + 600) = v5;
+      *(vint32mf2_t*)(out + i + 700) = v6;
+    }
+}
+/* { dg-final { scan-assembler-times {vsetvli} 7 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-not {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16\s*mf4,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gfortran.dg/pr107397.f90 b/gcc/testsuite/gfortran.dg/pr107397.f90
new file mode 100644
index 0000000..fd59bf1
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr107397.f90
@@ -0,0 +1,9 @@
+!{ dg-do compile }
+!
+program p
+  type t
+    real :: a = 1.0
+  end type
+  type(t), parameter :: x = z'1' ! { dg-error "incompatible with a BOZ" }
+  x%a = x%a + 2 ! { dg-error "has no IMPLICIT type" }
+end
diff --git a/gcc/testsuite/gm2/pimcoroutines/run/pass/testtime.mod b/gcc/testsuite/gm2/pimcoroutines/run/pass/testtime.mod
index fa43163..2e770ae 100644
--- a/gcc/testsuite/gm2/pimcoroutines/run/pass/testtime.mod
+++ b/gcc/testsuite/gm2/pimcoroutines/run/pass/testtime.mod
@@ -1,4 +1,4 @@
-(* Copyright (C) 2005-2020
+(* Copyright (C) 2005-2022
                  Free Software Foundation, Inc. *)
 (* This file is part of GNU Modula-2.
 
@@ -31,54 +31,58 @@ FROM SYSTEM IMPORT ADR ;
 FROM libc IMPORT write, printf ;
 
 
+CONST
+   TicksPerTimeUnit = 1 ;
+
+
 (*
-   OneSecond -
+   OneUnit -
 *)
 
-PROCEDURE OneSecond ;
+PROCEDURE OneUnit ;
 VAR
    n: CARDINAL ;
 BEGIN
    OldInts := TurnInterrupts (MIN (PROTECTION)) ;
-   printf ("1 second process has come to life\n");
+   printf ("1 unit process has come to life\n");
    n := 0 ;
    LOOP
-      Sleep (1*TicksPerSecond) ;
+      Sleep (1*TicksPerTimeUnit) ;
       INC (n) ;
-      printf ("%d seconds\n", n);
+      printf ("%d units\n", n);
    END
-END OneSecond ;
+END OneUnit ;
 
 
 (*
-   FourSeconds -
+   FourUnits -
 *)
 
-PROCEDURE FourSeconds ;
+PROCEDURE FourUnits ;
 VAR
    n: CARDINAL ;
 BEGIN
    OldInts := TurnInterrupts (MIN (PROTECTION)) ;
-   printf ("4 seconds process has come to life\n");
+   printf ("4 units process has come to life\n");
    n := 0 ;
    LOOP
-      Sleep (4*TicksPerSecond) ;
+      Sleep (4*TicksPerTimeUnit) ;
       INC (n) ;
-      printf ("4 second alarm (%d occurance)\n", n);
+      printf ("4 units alarm (%d occurance)\n", n);
    END
-END FourSeconds ;
+END FourUnits ;
 
 
 (*
-   SixSeconds -
+   SixUnits -
 *)
 
-PROCEDURE SixSeconds ;
+PROCEDURE SixUnits ;
 VAR
    n: CARDINAL ;
 BEGIN
    OldInts := TurnInterrupts (MAX (PROTECTION)) ;
-   printf ("6 seconds process has come to life\n");
+   printf ("6 units process has come to life\n");
    n := 0 ;
    LOOP
       Timeout := ArmEvent (6*TicksPerSecond) ;
@@ -87,10 +91,10 @@ BEGIN
          WriteString ('...someone cancelled it...')
       ELSE
          INC (n) ;
-         printf ("6 second alarm (%d occurance)\n", n)
+         printf ("6 unit alarm (%d occurance)\n", n)
       END
    END
-END SixSeconds ;
+END SixUnits ;
 
 
 CONST
@@ -107,10 +111,10 @@ BEGIN
 
    printf ("now to create three processes...\n") ;
 
-   p1 := Resume (InitProcess (OneSecond  , StackSize, '1')) ;
-   p4 := Resume (InitProcess (FourSeconds, StackSize, '4')) ;
-   p6 := Resume (InitProcess (SixSeconds , StackSize, '6')) ;
+   p1 := Resume (InitProcess (OneUnit  , StackSize, '1')) ;
+   p4 := Resume (InitProcess (FourUnits, StackSize, '4')) ;
+   p6 := Resume (InitProcess (SixUnits , StackSize, '6')) ;
 
-   Sleep (20*TicksPerSecond) ;
+   Sleep (20*TicksPerTimeUnit) ;
    printf ("successfully completed, finishing now.\n")
 END testtime.
diff --git a/gcc/tree-vect-loop-manip.cc b/gcc/tree-vect-loop-manip.cc
index 1d96130..5ec739e 100644
--- a/gcc/tree-vect-loop-manip.cc
+++ b/gcc/tree-vect-loop-manip.cc
@@ -1576,14 +1576,16 @@ vect_update_ivs_after_vectorizer (loop_vec_info loop_vinfo,
 
       if (induction_type == vect_step_op_add)
 	{
-	  off = fold_build2 (MULT_EXPR, TREE_TYPE (step_expr),
-			     fold_convert (TREE_TYPE (step_expr), niters),
-			     step_expr);
+	  tree stype = TREE_TYPE (step_expr);
+	  off = fold_build2 (MULT_EXPR, stype,
+			     fold_convert (stype, niters), step_expr);
 	  if (POINTER_TYPE_P (type))
 	    ni = fold_build_pointer_plus (init_expr, off);
 	  else
-	    ni = fold_build2 (PLUS_EXPR, type,
-			      init_expr, fold_convert (type, off));
+	    ni = fold_convert (type,
+			       fold_build2 (PLUS_EXPR, stype,
+					    fold_convert (stype, init_expr),
+					    off));
 	}
       /* Don't bother call vect_peel_nonlinear_iv_init.  */
       else if (induction_type == vect_step_op_neg)