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authorSergey Shalnov <Sergey.Shalnov@intel.com>2017-12-01 06:40:27 +0000
committerKirill Yukhin <kyukhin@gcc.gnu.org>2017-12-01 06:40:27 +0000
commit663c725aa25da254c55873810c801526ae1af836 (patch)
tree62d5fa3996da7495c4b0c3e22428c34c0aa624d3 /gcc
parentbddb9bb1c7c4b7c7973ddde13c4f52121db923ea (diff)
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Fix movdi_internal to return MODE_TI with AVX512
gcc/ * config/i386/i386.md: Fix AVX512 register width in AVX512 instruction. From-SVN: r255293
Diffstat (limited to 'gcc')
-rw-r--r--gcc/ChangeLog4
-rw-r--r--gcc/config/i386/i386.md9
2 files changed, 10 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 8e7e844..e38b73f 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,9 @@
2017-12-01 Sergey Shalnov <Sergey.Shalnov@intel.com>
+ * config/i386/i386.md: Fix AVX512 register width in AVX512 instruction.
+
+2017-12-01 Sergey Shalnov <Sergey.Shalnov@intel.com>
+
* config/i386/i386.c (standard_sse_constant_opcode): Fix wrong form for
vpcmpeqd instruction.
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index a14efc8..b4d73db 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -2254,10 +2254,13 @@
&& (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1])))
return "%vmovd\t{%1, %0|%0, %1}";
return "%vmovq\t{%1, %0|%0, %1}";
+
case MODE_TI:
+ /* Handle AVX512 registers set. */
+ if (EXT_REX_SSE_REG_P (operands[0])
+ || EXT_REX_SSE_REG_P (operands[1]))
+ return "vmovdqa64\t{%1, %0|%0, %1}";
return "%vmovdqa\t{%1, %0|%0, %1}";
- case MODE_XI:
- return "vmovdqa64\t{%g1, %g0|%g0, %g1}";
case MODE_V2SF:
gcc_assert (!TARGET_AVX);
@@ -2349,7 +2352,7 @@
(eq_attr "alternative" "12,13")
(cond [(ior (match_operand 0 "ext_sse_reg_operand")
(match_operand 1 "ext_sse_reg_operand"))
- (const_string "XI")
+ (const_string "TI")
(ior (not (match_test "TARGET_SSE2"))
(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL"))
(const_string "V4SF")