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| author | Robin Dapp <rdapp@ventanamicro.com> | 2023-05-12 10:26:51 +0200 |
|---|---|---|
| committer | Robin Dapp <rdapp@ventanamicro.com> | 2023-05-19 13:39:16 +0200 |
| commit | 64d6a4dfd983377c6a91f1711ead71dc59aaefac (patch) | |
| tree | ae71aca69beda5545fd9f78e9f3ce28d2a339439 /gcc | |
| parent | 0a78bc26dadcb6f4c8b59b41858d70bb5432fadd (diff) | |
| download | gcc-64d6a4dfd983377c6a91f1711ead71dc59aaefac.zip gcc-64d6a4dfd983377c6a91f1711ead71dc59aaefac.tar.gz gcc-64d6a4dfd983377c6a91f1711ead71dc59aaefac.tar.bz2 | |
RISC-V: Allow more loading of const vectors.
This patch fixes the recent vmv patch in order to allow loading
of constants via vmv.vi with the "fixed-vlmax" vectorization flavor.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_const_insns): Remove else.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c: New test.
* gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c: New test.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/riscv/riscv.cc | 2 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c | 6 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c | 6 |
3 files changed, 13 insertions, 1 deletions
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 235be75..8320069 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -1295,7 +1295,7 @@ riscv_const_insns (rtx x) The Wc0, Wc1 constraints are already covered by the vi constraint so we do not need to check them here separately. */ - else if (TARGET_VECTOR && satisfies_constraint_vi (x)) + if (TARGET_VECTOR && satisfies_constraint_vi (x)) return 1; /* TODO: We may support more const vector in the future. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c new file mode 100644 index 0000000..631ea3b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv -mabi=ilp32d -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -fno-builtin" } */ + +#include "vmv-imm-template.h" + +/* { dg-final { scan-assembler-times "vmv.v.i" 32 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c new file mode 100644 index 0000000..7ded6cc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -march=rv64gcv -mabi=lp64d -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -fno-builtin" } */ + +#include "vmv-imm-template.h" + +/* { dg-final { scan-assembler-times "vmv.v.i" 32 } } */ |