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| author | Alex Coplan <alex.coplan@arm.com> | 2020-09-24 17:22:44 +0100 |
|---|---|---|
| committer | Alex Coplan <alex.coplan@arm.com> | 2020-09-24 17:22:44 +0100 |
| commit | 637ad78cdf4026234308973bb87839f10f3d39cf (patch) | |
| tree | 48683191aae3ad1fc574ddcf820c5f4d0741a621 /gcc | |
| parent | 50d9db203bc3b05c781a0da91be5ba21a1256f21 (diff) | |
| download | gcc-637ad78cdf4026234308973bb87839f10f3d39cf.zip gcc-637ad78cdf4026234308973bb87839f10f3d39cf.tar.gz gcc-637ad78cdf4026234308973bb87839f10f3d39cf.tar.bz2 | |
arm: Add support for Neoverse N2 CPU
This adds support for Arm's Neoverse N2 CPU to the AArch32 backend.
Neoverse N2 builds AArch32 at EL0 and therefore needs support in AArch32
GCC.
gcc/ChangeLog:
* config/arm/arm-cpus.in (neoverse-n2): New.
* config/arm/arm-tables.opt: Regenerate.
* config/arm/arm-tune.md: Regenerate.
* doc/invoke.texi: Document support for Neoverse N2.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/arm/arm-cpus.in | 11 | ||||
| -rw-r--r-- | gcc/config/arm/arm-tables.opt | 3 | ||||
| -rw-r--r-- | gcc/config/arm/arm-tune.md | 7 | ||||
| -rw-r--r-- | gcc/doc/invoke.texi | 6 |
4 files changed, 21 insertions, 6 deletions
diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index 4550694..be563b7 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -1459,6 +1459,17 @@ begin cpu neoverse-n1 part d0c end cpu neoverse-n1 +begin cpu neoverse-n2 + cname neoversen2 + tune for cortex-a57 + tune flags LDSCHED + architecture armv8.5-a+fp16+bf16+i8mm + option crypto add FP_ARMv8 CRYPTO + costs cortex_a57 + vendor 41 + part 0xd49 +end cpu neoverse-n2 + # ARMv8.2 A-profile ARM DynamIQ big.LITTLE implementations begin cpu cortex-a75.cortex-a55 cname cortexa75cortexa55 diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index 1a7c319..b572063 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -244,6 +244,9 @@ EnumValue Enum(processor_type) String(neoverse-n1) Value( TARGET_CPU_neoversen1) EnumValue +Enum(processor_type) String(neoverse-n2) Value( TARGET_CPU_neoversen2) + +EnumValue Enum(processor_type) String(cortex-a75.cortex-a55) Value( TARGET_CPU_cortexa75cortexa55) EnumValue diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md index 3874f42..2377037 100644 --- a/gcc/config/arm/arm-tune.md +++ b/gcc/config/arm/arm-tune.md @@ -45,7 +45,8 @@ cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35, cortexa73cortexa53,cortexa55,cortexa75, cortexa76,cortexa76ae,cortexa77, - neoversen1,cortexa75cortexa55,cortexa76cortexa55, - neoversev1,cortexm23,cortexm33, - cortexm35p,cortexm55,cortexr52" + neoversen1,neoversen2,cortexa75cortexa55, + cortexa76cortexa55,neoversev1,cortexm23, + cortexm33,cortexm35p,cortexm55, + cortexr52" (const (symbol_ref "((enum attr_tune) arm_tune)"))) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 3dc2553..2091e0c 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -19385,9 +19385,9 @@ Permissible names are: @samp{arm7tdmi}, @samp{arm7tdmi-s}, @samp{arm710t}, @samp{cortex-m35p}, @samp{cortex-m55}, @samp{cortex-m1.small-multiply}, @samp{cortex-m0.small-multiply}, @samp{cortex-m0plus.small-multiply}, @samp{exynos-m1}, @samp{marvell-pj4}, -@samp{neoverse-n1}, @samp{neoverse-v1}, @samp{xscale}, @samp{iwmmxt}, -@samp{iwmmxt2}, @samp{ep9312}, @samp{fa526}, @samp{fa626}, @samp{fa606te}, -@samp{fa626te}, @samp{fmp626}, @samp{fa726te}, @samp{xgene1}. +@samp{neoverse-n1}, @samp{neoverse-n2}, @samp{neoverse-v1}, @samp{xscale}, +@samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}, @samp{fa526}, @samp{fa626}, +@samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te}, @samp{xgene1}. Additionally, this option can specify that GCC should tune the performance of the code for a big.LITTLE system. Permissible names are: |