md.texi: (reduc_smin, reduc_umin, reduc_splus, reduc_uplus):

        * doc/md.texi: (reduc_smin, reduc_umin, reduc_splus, reduc_uplus):
        (vec_shl, vec_shr): Document new operations.
        * tree.def (VEC_RSHIFT_EXPR, VEC_LSHIFT_EXPR): Fix comment.

From-SVN: r102951

3 files changed, 44 insertions, 1 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 567c492..e13b94e 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2005-08-10  Dorit Nuzman  <dorit@il.ibm.com>
+
+	* doc/md.texi: (reduc_smin, reduc_umin, reduc_splus, reduc_uplus):
+	(vec_shl, vec_shr): Document new operations.
+	* tree.def (VEC_RSHIFT_EXPR, VEC_LSHIFT_EXPR): Fix comment.
+
 2005-08-10  David Edelsohn  <edelsohn@gnu.org>
 
 	* config/rs6000/predicates.md (indexed_or_indirect_address): New.
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 0d0e517..819ec70 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3039,6 +3039,43 @@ Signed minimum and maximum operations.  When used with floating point,
 if both operands are zeros, or if either operand is @code{NaN}, then
 it is unspecified which of the two operands is returned as the result.
 
+@cindex @code{reduc_smin_@var{m}} instruction pattern
+@cindex @code{reduc_smax_@var{m}} instruction pattern
+@item @samp{reduc_smin_@var{m}}, @samp{reduc_smax_@var{m}}
+Find the signed minimum/maximum of the elements of a vector. The vector is
+operand 1, and the scalar result is stored in the least significant bits of 
+operand 0 (also a vector). The output and input vector should have the same 
+modes.
+
+@cindex @code{reduc_umin_@var{m}} instruction pattern
+@cindex @code{reduc_umax_@var{m}} instruction pattern
+@item @samp{reduc_umin_@var{m}}, @samp{reduc_umax_@var{m}}
+Find the unsigned minimum/maximum of the elements of a vector. The vector is
+operand 1, and the scalar result is stored in the least significant bits of 
+operand 0 (also a vector). The output and input vector should have the same 
+modes.
+
+@cindex @code{reduc_splus_@var{m}} instruction pattern
+@item @samp{reduc_splus_@var{m}}
+Compute the sum of the signed elements of a vector. The vector is opernad 1, 
+and the scalar result is stored in the least significant bits of opernad 0 
+(also a vector). The output and input vector should have the same modes.
+
+@cindex @code{reduc_uplus_@var{m}} instruction pattern
+@item @samp{reduc_uplus_@var{m}}
+Compute the sum of the unsigned elements of a vector. The vector is opernad 1, 
+and the scalar result is stored in the least significant bits of opernad 0 
+(also a vector). The output and input vector should have the same modes.
+
+@cindex @code{vec_shl_@var{m}} instruction pattern
+@cindex @code{vec_shr_@var{m}} instruction pattern
+@item @samp{vec_shl_@var{m}}, @samp{vec_shr_@var{m}}
+Whole vector left/right shift in bits.
+Operand 1 is a vector to be shifted.
+Operand 2 is an integer shift amount in bits. 
+Operand 0 is where the resulting shifted vector is stored.
+The output and input vectors should have the same modes.
+
 @cindex @code{mulhisi3} instruction pattern
 @item @samp{mulhisi3}
 Multiply operands 1 and 2, which have mode @code{HImode}, and store
diff --git a/gcc/tree.def b/gcc/tree.def
index 00b130f..c1348aa 100644
--- a/gcc/tree.def
+++ b/gcc/tree.def
@@ -957,7 +957,7 @@ DEFTREECODE (REDUC_MAX_EXPR, "reduc_max_expr", tcc_unary, 1)
 DEFTREECODE (REDUC_MIN_EXPR, "reduc_min_expr", tcc_unary, 1)
 DEFTREECODE (REDUC_PLUS_EXPR, "reduc_plus_expr", tcc_unary, 1)
 
-/* Whole vector left/right shift in bytes.
+/* Whole vector left/right shift in bits.
    Operand 0 is a vector to be shifted.
    Operand 1 is an integer shift amount in bits.  */
 DEFTREECODE (VEC_LSHIFT_EXPR, "vec_lshift_expr", tcc_binary, 2)