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| author | Richard Sandiford <richard.sandiford@arm.com> | 2018-08-01 16:03:13 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2018-08-01 16:03:13 +0000 |
| commit | 616fc41ca2e3eb90c6e870d72d54277546c62a4d (patch) | |
| tree | 4179f0c4cbdd38c937a9280d494396fbeedb40d6 /gcc | |
| parent | f811f141c3d9f7fbbf5f7a0b6e2276c9784e2cda (diff) | |
| download | gcc-616fc41ca2e3eb90c6e870d72d54277546c62a4d.zip gcc-616fc41ca2e3eb90c6e870d72d54277546c62a4d.tar.gz gcc-616fc41ca2e3eb90c6e870d72d54277546c62a4d.tar.bz2 | |
[AArch64] Update expected output for sve/var_stride_[24].c
After Segher's recent combine change, these tests now use a single
instruction to do the "and" and "lsl 10". This is a good thing,
so the patch updates the expected output accordingly.
2018-08-01 Richard Sandiford <richard.sandiford@arm.com>
gcc/testsuite/
* gcc.target/aarch64/sve/var_stride_2.c: Update expected form
of range check.
* gcc.target/aarch64/sve/var_stride_4.c: Likewise.
From-SVN: r263228
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/testsuite/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/sve/var_stride_2.c | 3 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/sve/var_stride_4.c | 3 |
3 files changed, 10 insertions, 2 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 4f4084c..93fc807f 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,11 @@ 2018-08-01 Richard Sandiford <richard.sandiford@arm.com> + * gcc.target/aarch64/sve/var_stride_2.c: Update expected form + of range check. + * gcc.target/aarch64/sve/var_stride_4.c: Likewise. + +2018-08-01 Richard Sandiford <richard.sandiford@arm.com> + PR target/86753 * gcc.target/aarch64/sve/vcond_4.c: XFAIL positive tests. * gcc.target/aarch64/sve/vcond_5.c: Likewise. diff --git a/gcc/testsuite/gcc.target/aarch64/sve/var_stride_2.c b/gcc/testsuite/gcc.target/aarch64/sve/var_stride_2.c index 112e84f..30f6d26 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/var_stride_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/var_stride_2.c @@ -16,7 +16,8 @@ f (TYPE *x, TYPE *y, unsigned short n, unsigned short m) /* { dg-final { scan-assembler {\tldr\tw[0-9]+} } } */ /* { dg-final { scan-assembler {\tstr\tw[0-9]+} } } */ /* Should multiply by (257-1)*4 rather than (VF-1)*4. */ -/* { dg-final { scan-assembler-times {\tadd\tx[0-9]+, x[0-9]+, x[0-9]+, lsl 10\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tubfiz\tx[0-9]+, x2, 10, 16\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tubfiz\tx[0-9]+, x3, 10, 16\n} 1 } } */ /* { dg-final { scan-assembler-not {\tcmp\tx[0-9]+, 0} } } */ /* { dg-final { scan-assembler-not {\tcmp\tw[0-9]+, 0} } } */ /* { dg-final { scan-assembler-not {\tcsel\tx[0-9]+} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/var_stride_4.c b/gcc/testsuite/gcc.target/aarch64/sve/var_stride_4.c index 4bcdb5d..d2e74f9 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/var_stride_4.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/var_stride_4.c @@ -16,7 +16,8 @@ f (TYPE *x, TYPE *y, int n, int m) /* { dg-final { scan-assembler {\tldr\tw[0-9]+} } } */ /* { dg-final { scan-assembler {\tstr\tw[0-9]+} } } */ /* Should multiply by (257-1)*4 rather than (VF-1)*4. */ -/* { dg-final { scan-assembler-times {\tlsl\tx[0-9]+, x[0-9]+, 10\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tsbfiz\tx[0-9]+, x2, 10, 32\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tsbfiz\tx[0-9]+, x3, 10, 32\n} 1 } } */ /* { dg-final { scan-assembler {\tcmp\tw2, 0} } } */ /* { dg-final { scan-assembler {\tcmp\tw3, 0} } } */ /* { dg-final { scan-assembler-times {\tcsel\tx[0-9]+} 4 } } */ |