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| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-05-26 08:59:29 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-05-26 08:59:29 +0800 |
| commit | 5bd67d7abddca87198b11efccedee42f82e9f3a9 (patch) | |
| tree | a8dc3351bc17a39f2e34efa5f8bf5a6fabef1fe5 /gcc | |
| parent | 47c4245b973c8fd136e443f2e90d2b2d08877822 (diff) | |
| download | gcc-5bd67d7abddca87198b11efccedee42f82e9f3a9.zip gcc-5bd67d7abddca87198b11efccedee42f82e9f3a9.tar.gz gcc-5bd67d7abddca87198b11efccedee42f82e9f3a9.tar.bz2 | |
RISC-V: Fix zero-scratch-regs-3.c fail
gcc/ChangeLog:
* config/riscv/riscv.cc (vector_zero_call_used_regs): Add
explict VL and drop VL in ops.
Signed-off-by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/riscv/riscv.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 09fc9e5..b16c60d 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -7396,9 +7396,9 @@ vector_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs) emitted_vlmax_vsetvl = true; } - rtx ops[] = {target, CONST0_RTX (mode), vl}; + rtx ops[] = {target, CONST0_RTX (mode)}; riscv_vector::emit_vlmax_insn (code_for_pred_mov (mode), - riscv_vector::RVV_UNOP, ops); + riscv_vector::RVV_UNOP, ops, vl); SET_HARD_REG_BIT (zeroed_hardregs, regno); } |