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| author | Segher Boessenkool <segher@kernel.crashing.org> | 2014-09-21 20:03:52 +0200 |
|---|---|---|
| committer | Segher Boessenkool <segher@gcc.gnu.org> | 2014-09-21 20:03:52 +0200 |
| commit | 5b281c53c79520591674dfcc90b3856f15167ce3 (patch) | |
| tree | c18d91e761c6ad464797746d5acadb29394c53ce /gcc | |
| parent | f4e0b104a60a18ed1512caaae61871afa333e368 (diff) | |
| download | gcc-5b281c53c79520591674dfcc90b3856f15167ce3.zip gcc-5b281c53c79520591674dfcc90b3856f15167ce3.tar.gz gcc-5b281c53c79520591674dfcc90b3856f15167ce3.tar.bz2 | |
2014-09-21 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/rs6000.md (ashr<mode>3, *ashr<mode>3, *ashrsi3_64,
*ashr<mode>3_dot, *ashr<mode>3_dot2): Clobber CA_REGNO.
(floatdisf2_internal2): Ditto.
(ashrdi3_no_power): Ditto. Fix formatting.
From-SVN: r215436
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 44 |
2 files changed, 33 insertions, 18 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index fbbf00f..96e5094 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,12 @@ 2014-09-21 Segher Boessenkool <segher@kernel.crashing.org> + * config/rs6000/rs6000.md (ashr<mode>3, *ashr<mode>3, *ashrsi3_64, + *ashr<mode>3_dot, *ashr<mode>3_dot2): Clobber CA_REGNO. + (floatdisf2_internal2): Ditto. + (ashrdi3_no_power): Ditto. Fix formatting. + +2014-09-21 Segher Boessenkool <segher@kernel.crashing.org> + * config/rs6000/rs6000.md (ctz<mode>2, ffs<mode>2, popcount<mode>2, popcntb<mode>2, popcntd<mode>2, parity<mode>2, parity<mode>2_cmpb): Tidy. diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 059dd99..91bdb7d 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -4634,9 +4634,10 @@ (define_expand "ashr<mode>3" - [(set (match_operand:GPR 0 "gpc_reg_operand" "") - (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")))] + [(parallel [(set (match_operand:GPR 0 "gpc_reg_operand" "") + (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "") + (match_operand:SI 2 "reg_or_cint_operand" ""))) + (clobber (reg:GPR CA_REGNO))])] "" { /* The generic code does not generate optimal code for the low word @@ -4658,7 +4659,8 @@ (define_insn "*ashr<mode>3" [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") - (match_operand:SI 2 "reg_or_cint_operand" "rn")))] + (match_operand:SI 2 "reg_or_cint_operand" "rn"))) + (clobber (reg:GPR CA_REGNO))] "" "sra<wd>%I2 %0,%1,%<hH>2" [(set_attr "type" "shift") @@ -4668,7 +4670,8 @@ [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (sign_extend:DI (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") - (match_operand:SI 2 "reg_or_cint_operand" "rn"))))] + (match_operand:SI 2 "reg_or_cint_operand" "rn")))) + (clobber (reg:SI CA_REGNO))] "TARGET_POWERPC64" "sraw%I2 %0,%1,%h2" [(set_attr "type" "shift") @@ -4679,15 +4682,17 @@ (compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) (const_int 0))) - (clobber (match_scratch:GPR 0 "=r,r"))] + (clobber (match_scratch:GPR 0 "=r,r")) + (clobber (reg:GPR CA_REGNO))] "<MODE>mode == Pmode && rs6000_gen_cell_microcode" "@ sra<wd>%I2. %0,%1,%<hH>2 #" "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)" - [(set (match_dup 0) - (ashiftrt:GPR (match_dup 1) - (match_dup 2))) + [(parallel [(set (match_dup 0) + (ashiftrt:GPR (match_dup 1) + (match_dup 2))) + (clobber (reg:GPR CA_REGNO))]) (set (match_dup 3) (compare:CC (match_dup 0) (const_int 0)))] @@ -4704,15 +4709,17 @@ (const_int 0))) (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") (ashiftrt:GPR (match_dup 1) - (match_dup 2)))] + (match_dup 2))) + (clobber (reg:GPR CA_REGNO))] "<MODE>mode == Pmode && rs6000_gen_cell_microcode" "@ sra<wd>%I2. %0,%1,%<hH>2 #" "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)" - [(set (match_dup 0) - (ashiftrt:GPR (match_dup 1) - (match_dup 2))) + [(parallel [(set (match_dup 0) + (ashiftrt:GPR (match_dup 1) + (match_dup 2))) + (clobber (reg:GPR CA_REGNO))]) (set (match_dup 3) (compare:CC (match_dup 0) (const_int 0)))] @@ -6153,8 +6160,9 @@ ;; by a bit that won't be lost at that stage, but is below the SFmode ;; rounding position. (define_expand "floatdisf2_internal2" - [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "") - (const_int 53))) + [(parallel [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "") + (const_int 53))) + (clobber (reg:DI CA_REGNO))]) (set (match_operand:DI 0 "" "") (and:DI (match_dup 1) (const_int 2047))) (set (match_dup 3) (plus:DI (match_dup 3) @@ -6317,9 +6325,9 @@ (define_insn "ashrdi3_no_power" [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "const_int_operand" "M,i")))] + (match_operand:SI 2 "const_int_operand" "M,i"))) + (clobber (reg:SI CA_REGNO))] "!TARGET_POWERPC64" - "* { switch (which_alternative) { @@ -6336,7 +6344,7 @@ else return \"srwi %0,%1,%h2\;insrwi %0,%L1,%h2,0\;srawi %L0,%L1,%h2\"; } -}" +} [(set_attr "type" "two,three") (set_attr "length" "8,12")]) |