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| author | Ju-Zhe Zhong <juzhe.zhong@rivai.ai> | 2023-01-18 11:03:47 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2023-01-27 17:37:20 +0800 |
| commit | 5aa486e7740a0bc83168d806806d1149e6e90310 (patch) | |
| tree | ca35a989e29155d14537d0329d71b2b6997e3cbe /gcc | |
| parent | ca8fb0096713a8477614ef874f16ba5bf16c48bc (diff) | |
| download | gcc-5aa486e7740a0bc83168d806806d1149e6e90310.zip gcc-5aa486e7740a0bc83168d806806d1149e6e90310.tar.gz gcc-5aa486e7740a0bc83168d806806d1149e6e90310.tar.bz2 | |
RISC-V: Reorder VSETVL pass location
Insert before dce means we don't invoke DCE by this pass itself, and
also we can leverage the effort of BB reorder.
gcc/ChangeLog:
* config/riscv/riscv-passes.def (INSERT_PASS_BEFORE): Reorder VSETVL
pass.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/riscv/riscv-passes.def | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/config/riscv/riscv-passes.def b/gcc/config/riscv/riscv-passes.def index e68de68..4084122 100644 --- a/gcc/config/riscv/riscv-passes.def +++ b/gcc/config/riscv/riscv-passes.def @@ -18,4 +18,4 @@ <http://www.gnu.org/licenses/>. */ INSERT_PASS_AFTER (pass_rtl_store_motion, 1, pass_shorten_memrefs); -INSERT_PASS_BEFORE (pass_sched2, 1, pass_vsetvl); +INSERT_PASS_BEFORE (pass_fast_rtl_dce, 1, pass_vsetvl); |