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| author | Shaokun Zhang <zhangshaokun@hisilicon.com> | 2018-12-19 10:08:50 +0000 |
|---|---|---|
| committer | Richard Earnshaw <rearnsha@gcc.gnu.org> | 2018-12-19 10:08:50 +0000 |
| commit | 5a8d95cc43f3ff425fa58bf4025a8527320fb46c (patch) | |
| tree | e3f95c34cc0f49950e1ab9641beb9660d0ded8ea /gcc | |
| parent | a62fd9ddaf60decd1dd2016220e142fd5c1d8b73 (diff) | |
| download | gcc-5a8d95cc43f3ff425fa58bf4025a8527320fb46c.zip gcc-5a8d95cc43f3ff425fa58bf4025a8527320fb46c.tar.gz gcc-5a8d95cc43f3ff425fa58bf4025a8527320fb46c.tar.bz2 | |
[aarch64] Correct architecture for tsv110.
For HiSilicon's tsv110 cpu core, it supports some v8_4A features, but
some mandatory features are not implemented.
2018-12-19 Shaokun Zhang <zhangshaokun@hisilicon.com>
* config/aarch64/aarch64-cores.def (tsv110): Fix architecture. This
part is really Armv8.2 with some permitted Armv8.4 extensions.
From-SVN: r267255
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-cores.def | 6 |
2 files changed, 8 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index cdfab54..524ad19 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2018-12-19 Shaokun Zhang <zhangshaokun@hisilicon.com> + + * config/aarch64/aarch64-cores.def (tsv110): Fix architecture. This + part is really Armv8.2 with some permitted Armv8.4 extensions. + 2018-12-19 Jakub Jelinek <jakub@redhat.com> PR target/88541 diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def index 74be5db..20f4924 100644 --- a/gcc/config/aarch64/aarch64-cores.def +++ b/gcc/config/aarch64/aarch64-cores.def @@ -96,10 +96,10 @@ AARCH64_CORE("cortex-a75", cortexa75, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 AARCH64_CORE("cortex-a76", cortexa76, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa72, 0x41, 0xd0b, -1) AARCH64_CORE("ares", ares, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD | AARCH64_FL_PROFILE, cortexa72, 0x41, 0xd0c, -1) -/* ARMv8.4-A Architecture Processors. */ - /* HiSilicon ('H') cores. */ -AARCH64_CORE("tsv110", tsv110, cortexa57, 8_4A, AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_CRYPTO | AARCH64_FL_F16 | AARCH64_FL_AES | AARCH64_FL_SHA2, tsv110, 0x48, 0xd01, -1) +AARCH64_CORE("tsv110", tsv110, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_CRYPTO | AARCH64_FL_F16 | AARCH64_FL_AES | AARCH64_FL_SHA2, tsv110, 0x48, 0xd01, -1) + +/* ARMv8.4-A Architecture Processors. */ /* Qualcomm ('Q') cores. */ AARCH64_CORE("saphira", saphira, saphira, 8_4A, AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_CRYPTO | AARCH64_FL_RCPC, saphira, 0x51, 0xC01, -1) |