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| author | Tamar Christina <tamar.christina@arm.com> | 2022-12-12 15:20:30 +0000 |
|---|---|---|
| committer | Tamar Christina <tamar.christina@arm.com> | 2022-12-12 15:20:30 +0000 |
| commit | 594264e9bcb592b8edc4b50b5d9be5eb34c1d6d7 (patch) | |
| tree | 7578c29ad6b5c26a409c211e96ffbc00c517ca27 /gcc | |
| parent | 17ae956c0fa6baac3d22764019d5dd5ebf5c2b11 (diff) | |
| download | gcc-594264e9bcb592b8edc4b50b5d9be5eb34c1d6d7.zip gcc-594264e9bcb592b8edc4b50b5d9be5eb34c1d6d7.tar.gz gcc-594264e9bcb592b8edc4b50b5d9be5eb34c1d6d7.tar.bz2 | |
AArch64: Fix vector re-interpretation between partial SIMD modes
While writing a patch series I started getting incorrect codegen out from
VEC_PERM on partial struct types.
It turns out that this was happening because the TARGET_CAN_CHANGE_MODE_CLASS
implementation has a slight bug in it. The hook only checked for SIMD to
Partial but never Partial to SIMD. This resulted in incorrect subregs to be
generated from the fallback code in VEC_PERM_EXPR expansions.
I have unfortunately not been able to trigger it using a standalone testcase as
the mid-end optimizes away the permute every time I try to describe a permute
that would result in the bug.
The patch now rejects any conversion of partial SIMD struct types, unless they
are both partial structures of the same number of registers or one is a SIMD
type who's size is less than 8 bytes.
gcc/ChangeLog:
* config/aarch64/aarch64.cc (aarch64_can_change_mode_class): Restrict
conversions between partial struct types properly.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/aarch64/aarch64.cc | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index fd92212..523d49a 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -26731,9 +26731,10 @@ aarch64_can_change_mode_class (machine_mode from, bool from_pred_p = (from_flags & VEC_SVE_PRED); bool to_pred_p = (to_flags & VEC_SVE_PRED); - bool from_full_advsimd_struct_p = (from_flags == (VEC_ADVSIMD | VEC_STRUCT)); bool to_partial_advsimd_struct_p = (to_flags == (VEC_ADVSIMD | VEC_STRUCT | VEC_PARTIAL)); + bool from_partial_advsimd_struct_p = (from_flags == (VEC_ADVSIMD | VEC_STRUCT + | VEC_PARTIAL)); /* Don't allow changes between predicate modes and other modes. Only predicate registers can hold predicate modes and only @@ -26755,9 +26756,10 @@ aarch64_can_change_mode_class (machine_mode from, || GET_MODE_UNIT_SIZE (from) != GET_MODE_UNIT_SIZE (to))) return false; - /* Don't allow changes between partial and full Advanced SIMD structure - modes. */ - if (from_full_advsimd_struct_p && to_partial_advsimd_struct_p) + /* Don't allow changes between partial and other registers only if + one is a normal SIMD register, allow only if not larger than 64-bit. */ + if ((to_partial_advsimd_struct_p ^ from_partial_advsimd_struct_p) + && (known_gt (GET_MODE_SIZE (to), 8) || known_gt (GET_MODE_SIZE (to), 8))) return false; if (maybe_ne (BITS_PER_SVE_VECTOR, 128u)) |