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authorKyrylo Tkachov <kyrylo.tkachov@arm.com>2014-11-18 16:26:02 +0000
committerKyrylo Tkachov <ktkachov@gcc.gnu.org>2014-11-18 16:26:02 +0000
commit58bd290e5b19164a956e08ffadc3684640c61e39 (patch)
tree860fa677c2ffb4af460b210fd65759f0807666f5 /gcc
parent7b69b603ec8f75d1132849f7604667596811d74e (diff)
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[ARM/AArch64] Improve modeled latency between FP operations and FP->GP register moves
* config/arm/cortex-a15-neon.md (cortex_a15_vfp_to_from_gp): Split into... (cortex_a15_gp_to_vfp): ...This. (cortex_a15_fp_to_gp): ...And this. Define and comment bypass from vfp operations to fp->gp moves. From-SVN: r217725
Diffstat (limited to 'gcc')
-rw-r--r--gcc/ChangeLog8
-rw-r--r--gcc/config/arm/cortex-a15-neon.md16
2 files changed, 21 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a15197e..4a825c1 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2014-11-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * config/arm/cortex-a15-neon.md (cortex_a15_vfp_to_from_gp):
+ Split into...
+ (cortex_a15_gp_to_vfp): ...This.
+ (cortex_a15_fp_to_gp): ...And this.
+ Define and comment bypass from vfp operations to fp->gp moves.
+
2014-11-18 Martin Liska <mliska@suse.cz>
* var-tracking.c (vt_find_locations): New fibonacci_node is used.
diff --git a/gcc/config/arm/cortex-a15-neon.md b/gcc/config/arm/cortex-a15-neon.md
index 02d4a53..bc09cd6 100644
--- a/gcc/config/arm/cortex-a15-neon.md
+++ b/gcc/config/arm/cortex-a15-neon.md
@@ -655,10 +655,20 @@
(eq_attr "type" "fmov"))
"ca15_issue1,ca15_cx_perm")
-(define_insn_reservation "cortex_a15_vfp_to_from_gp" 5
+(define_insn_reservation "cortex_a15_gp_to_vfp" 5
(and (eq_attr "tune" "cortexa15")
- (eq_attr "type" "f_mcr, f_mcrr, f_mrc, f_mrrc"))
- "ca15_issue1,ca15_ls1+ca15_ls2")
+ (eq_attr "type" "f_mcr, f_mcrr"))
+ "ca15_issue1,ca15_ls")
+
+(define_insn_reservation "cortex_a15_mov_vfp_to_gp" 5
+ (and (eq_attr "tune" "cortexa15")
+ (eq_attr "type" "f_mrc, f_mrrc"))
+ "ca15_issue1,ca15_ls")
+
+;; Moves from floating point registers to general purpose registers
+;; induce additional latency.
+(define_bypass 10 "cortex_a15_vfp*, cortex_a15_neon*, cortex_a15_gp_to_vfp" "cortex_a15_mov_vfp_to_gp")
+
(define_insn_reservation "cortex_a15_vfp_ariths" 7
(and (eq_attr "tune" "cortexa15")