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| author | Sergey Shalnov <Sergey.Shalnov@intel.com> | 2017-10-24 10:34:55 +0000 |
|---|---|---|
| committer | Kirill Yukhin <kyukhin@gcc.gnu.org> | 2017-10-24 10:34:55 +0000 |
| commit | 585a449d7307c46919fa9b2d6a0ee63fcb692789 (patch) | |
| tree | eece9293b9dd8e2ab723d02a536fef36aef24f27 /gcc | |
| parent | bc2a7cebfda15f53bc8fa4b596e96a87b53193fe (diff) | |
| download | gcc-585a449d7307c46919fa9b2d6a0ee63fcb692789.zip gcc-585a449d7307c46919fa9b2d6a0ee63fcb692789.tar.gz gcc-585a449d7307c46919fa9b2d6a0ee63fcb692789.tar.bz2 | |
Avoid 512-bit mode MOV for prefer-avx256 option in Intel AVX512 configuration
gcc/
* config/i386/i386.md(*movsf_internal, *movdf_internal):
Avoid 512-bit AVX modes for TARGET_PREFER_AVX256.
From-SVN: r254038
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/i386/i386.md | 12 |
2 files changed, 13 insertions, 4 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f42428c..82d69ed 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2017-10-06 Sergey Shalnov <Sergey.Shalnov@intel.com> + + * config/i386/i386.md(*movsf_internal, *movdf_internal): + Avoid 512-bit AVX modes for TARGET_PREFER_AVX256. + 2017-10-24 Eric Botcazou <ebotcazou@adacore.com> PR middle-end/82569 diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 57d2582..d5792eb 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -3575,8 +3575,10 @@ /* movaps is one byte shorter for non-AVX targets. */ (eq_attr "alternative" "13,17") - (cond [(ior (match_operand 0 "ext_sse_reg_operand") - (match_operand 1 "ext_sse_reg_operand")) + (cond [(and (ior (not (match_test "TARGET_PREFER_AVX256")) + (not (match_test "TARGET_AVX512VL"))) + (ior (match_operand 0 "ext_sse_reg_operand") + (match_operand 1 "ext_sse_reg_operand"))) (const_string "V8DF") (ior (not (match_test "TARGET_SSE2")) (match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")) @@ -3750,8 +3752,10 @@ better to maintain the whole registers in single format to avoid problems on using packed logical operations. */ (eq_attr "alternative" "6") - (cond [(ior (match_operand 0 "ext_sse_reg_operand") - (match_operand 1 "ext_sse_reg_operand")) + (cond [(and (ior (not (match_test "TARGET_PREFER_AVX256")) + (not (match_test "TARGET_AVX512VL"))) + (ior (match_operand 0 "ext_sse_reg_operand") + (match_operand 1 "ext_sse_reg_operand"))) (const_string "V16SF") (ior (match_test "TARGET_SSE_PARTIAL_REG_DEPENDENCY") (match_test "TARGET_SSE_SPLIT_REGS")) |