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author | Jeff Law <law@gcc.gnu.org> | 1993-04-04 18:08:33 -0600 |
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committer | Jeff Law <law@gcc.gnu.org> | 1993-04-04 18:08:33 -0600 |
commit | 575bb005a4d0b040b48f3ec1214fba93a0014722 (patch) | |
tree | 3cc4f20ff1244d2b70cabc4165f551b7b7a26c66 /gcc | |
parent | 84721fbde7a0bc86a1e3b279293394829ba43746 (diff) | |
download | gcc-575bb005a4d0b040b48f3ec1214fba93a0014722.zip gcc-575bb005a4d0b040b48f3ec1214fba93a0014722.tar.gz gcc-575bb005a4d0b040b48f3ec1214fba93a0014722.tar.bz2 |
pa.c (short_memory_operand): Delete.
* pa.c (short_memory_operand): Delete.
(emit_move_sequence): Do not use short_memory_operand When testing
for secondary reloads for FP loads/stores.
From-SVN: r4014
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/config/pa/pa.c | 31 |
1 files changed, 6 insertions, 25 deletions
diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c index 365f3c8..6edb348 100644 --- a/gcc/config/pa/pa.c +++ b/gcc/config/pa/pa.c @@ -219,29 +219,6 @@ pic_operand (op, mode) } int -short_memory_operand (op, mode) - rtx op; - enum machine_mode mode; -{ - if (GET_CODE (op) == MEM) - { - if (GET_CODE (XEXP (op, 0)) == REG) - return 1; - else if (GET_CODE (XEXP (op, 0)) == PLUS) - { - rtx op1 = XEXP (XEXP (op, 0), 0); - rtx op2 = XEXP (XEXP (op, 0), 1); - - if (GET_CODE (op1) == REG) - return (GET_CODE (op2) == CONST_INT && INT_5_BITS (op2)); - else if (GET_CODE (op2) == REG) - return (GET_CODE (op1) == CONST_INT && INT_5_BITS (op1)); - } - } - return 0; -} - -int fp_reg_operand (op, mode) rtx op; enum machine_mode mode; @@ -729,7 +706,9 @@ emit_move_sequence (operands, mode, scratch_reg) REG+D addresses where D does not fit in 5 bits. */ if (fp_reg_operand (operand0, mode) && GET_CODE (operand1) == MEM - && !short_memory_operand (operand1, mode) + /* Using DFmode forces only short displacements be be + recognized as valid in reg+d addressing modes. */ + && ! memory_address_p (DFmode, XEXP (operand1, 0)) && scratch_reg) { emit_move_insn (scratch_reg, XEXP (operand1 , 0)); @@ -739,7 +718,9 @@ emit_move_sequence (operands, mode, scratch_reg) } else if (fp_reg_operand (operand1, mode) && GET_CODE (operand0) == MEM - && !short_memory_operand (operand0, mode) + /* Using DFmode forces only short displacements be be + recognized as valid in reg+d addressing modes. */ + && ! memory_address_p (DFmode, XEXP (operand0, 0)) && scratch_reg) { emit_move_insn (scratch_reg, XEXP (operand0 , 0)); |