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| author | Joey Ye <joey.ye@arm.com> | 2012-04-13 08:05:39 +0000 |
|---|---|---|
| committer | Joey Ye <jye2@gcc.gnu.org> | 2012-04-13 08:05:39 +0000 |
| commit | 572a49c87c812ea9c43b0fd4e4049f9978f3476c (patch) | |
| tree | cd0a59eef33c4b56fe8636a20ee892d2bcdf304b /gcc | |
| parent | 50f751248974d136717c7d1d7aa0a05087b0b094 (diff) | |
| download | gcc-572a49c87c812ea9c43b0fd4e4049f9978f3476c.zip gcc-572a49c87c812ea9c43b0fd4e4049f9978f3476c.tar.gz gcc-572a49c87c812ea9c43b0fd4e4049f9978f3476c.tar.bz2 | |
constraints.md (Pe): New constraint.
2012-04-13 Joey Ye <joey.ye@arm.com>
* config/arm/constraints.md (Pe): New constraint.
* config/arm/arm.md: New split for imm 256-510.
testsuite:
* gcc.target/arm/thumb1-imm.c: New testcase.
From-SVN: r186406
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 15 | ||||
| -rw-r--r-- | gcc/config/arm/constraints.md | 7 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/thumb1-imm.c | 10 |
5 files changed, 40 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c3c0c4a..4b688ea 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2012-04-13 Joey Ye <joey.ye@arm.com> + + * config/arm/constraints.md (Pe): New constraint. + * config/arm/arm.md: New split for imm 256-510. + 2012-04-13 Terry Guo <terry.guo@arm.com> * config/arm/arm-cores.def: Added core cortex-m0plus. diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 3cdc1535..79eff0e 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -5652,6 +5652,21 @@ }" ) +;; For thumb1 split imm move [256-510] into mov [1-255] and add #255 +(define_split + [(set (match_operand:SI 0 "register_operand" "") + (match_operand:SI 1 "const_int_operand" ""))] + "TARGET_THUMB1 && satisfies_constraint_Pe (operands[1])" + [(set (match_dup 2) (match_dup 1)) + (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 3)))] + " + { + operands[1] = GEN_INT (INTVAL (operands[1]) - 255); + operands[2] = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0]; + operands[3] = GEN_INT (255); + }" +) + ;; When generating pic, we need to load the symbol offset into a register. ;; So that the optimizer does not confuse this with a normal symbol load ;; we use an unspec. The offset will be loaded from a constant pool entry, diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md index 3ff968b..6b59e87 100644 --- a/gcc/config/arm/constraints.md +++ b/gcc/config/arm/constraints.md @@ -30,7 +30,7 @@ ;; The following multi-letter normal constraints have been used: ;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di, Dt, Dz -;; in Thumb-1 state: Pa, Pb, Pc, Pd +;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe ;; in Thumb-2 state: Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py ;; The following memory constraints have been used: @@ -172,6 +172,11 @@ (and (match_code "const_int") (match_test "TARGET_THUMB1 && ival >= 0 && ival <= 7"))) +(define_constraint "Pe" + "@internal In Thumb-1 state a constant in the range 256 to +510" + (and (match_code "const_int") + (match_test "TARGET_THUMB1 && ival >= 256 && ival <= 510"))) + (define_constraint "Ps" "@internal In Thumb-2 state a constant in the range -255 to +255" (and (match_code "const_int") diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index d3f1464..2884b93 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2012-04-13 Joey Ye <joey.ye@arm.com> + + * gcc.target/arm/thumb1-imm.c: New testcase. + 2012-04-12 Uros Bizjak <ubizjak@gmail.com> PR target/52932 diff --git a/gcc/testsuite/gcc.target/arm/thumb1-imm.c b/gcc/testsuite/gcc.target/arm/thumb1-imm.c new file mode 100644 index 0000000..b47c08c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/thumb1-imm.c @@ -0,0 +1,10 @@ +/* Check for thumb1 imm [255-510] moves. */ +/* { dg-require-effective-target arm_thumb1_ok } */ + +int f() +{ + return 257; +} + +/* { dg-final { scan-assembler-not "ldr" } } */ + |