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| author | Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> | 2015-10-05 11:08:45 +0000 |
|---|---|---|
| committer | Ramana Radhakrishnan <ramana@gcc.gnu.org> | 2015-10-05 11:08:45 +0000 |
| commit | 562eadf8e0f3a993ce3c2369a98baf0bf942091c (patch) | |
| tree | b918daa14af6c79fe7cbe9dc090f78edc7da3ef1 /gcc | |
| parent | 057ce49719a82ad05978d0abca9d9dc95a3f4958 (diff) | |
| download | gcc-562eadf8e0f3a993ce3c2369a98baf0bf942091c.zip gcc-562eadf8e0f3a993ce3c2369a98baf0bf942091c.tar.gz gcc-562eadf8e0f3a993ce3c2369a98baf0bf942091c.tar.bz2 | |
[Patch ARM/ AArch64] Fix typo in vcvt_f16.c testcase .
This test worked by accident. While looking at why this was failing randomly in my builds, I discovered a bug in the way in which the testcases were written up in this case.
2015-10-05 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c (TEST_MSG): Fix typo.
(exec_vcvt): Add comments.
From-SVN: r228470
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c | 6 |
2 files changed, 9 insertions, 2 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index c1282b3..3cb201e 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2015-10-05 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> + + * gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c (TEST_MSG): Fix typo. + (exec_vcvt): Add comments. + 2015-10-04 Uros Bizjak <ubizjak@gmail.com> PR rtl-optimization/67447 diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c index 48e50e1..c3e4d4f 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c @@ -21,7 +21,7 @@ exec_vcvt (void) { clean_results (); -#define TEST_MSG vcvt_f32_f16 +#define TEST_MSG "vcvt_f32_f16" { VECT_VAR_DECL (buffer_src, float, 16, 4) [] = { 16.0, 15.0, 14.0, 13.0 }; @@ -39,7 +39,7 @@ exec_vcvt (void) clean_results (); -#define TEST_MSG vcvt_f16_f32 +#define TEST_MSG "vcvt_f16_f32" { VECT_VAR_DECL (buffer_src, float, 32, 4) [] = { 1.5, 2.5, 3.5, 4.5 }; DECL_VARIABLE (vector_src, float, 32, 4); @@ -54,6 +54,8 @@ exec_vcvt (void) } #undef TEST_MSG + /* We run more tests for AArch64 as the relevant intrinsics + do not exist on AArch32. */ #if defined (__aarch64__) clean_results (); |