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| author | Kito Cheng <kito.cheng@sifive.com> | 2024-01-19 17:52:44 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2024-01-19 18:06:25 +0800 |
| commit | 54519030b05e2a85565cd65c88afe7da4670dd86 (patch) | |
| tree | 6a5ccd4f5f479b6b9601b5ab29ee9000f3b1cab3 /gcc | |
| parent | 19260a04ba6f75b1fae52afab50dcb43d44eb259 (diff) | |
| download | gcc-54519030b05e2a85565cd65c88afe7da4670dd86.zip gcc-54519030b05e2a85565cd65c88afe7da4670dd86.tar.gz gcc-54519030b05e2a85565cd65c88afe7da4670dd86.tar.bz2 | |
RISC-V: Update testcase due to message update
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-27.c: Update scan message.
* gcc.target/riscv/arch-28.c: Ditto.
* gcc.target/riscv/attribute-10.c: Ditto.
* gcc.target/riscv/rvv/base/big_endian-2.c: Ditto.
* gcc.target/riscv/rvv/base/zvl-unimplemented-1.c: Ditto.
* gcc.target/riscv/rvv/base/zvl-unimplemented-2.c: Ditto.
Diffstat (limited to 'gcc')
6 files changed, 6 insertions, 6 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/arch-27.c b/gcc/testsuite/gcc.target/riscv/arch-27.c index 03f07dee..95cebc1 100644 --- a/gcc/testsuite/gcc.target/riscv/arch-27.c +++ b/gcc/testsuite/gcc.target/riscv/arch-27.c @@ -4,4 +4,4 @@ int foo() { } -/* { dg-error "'i', 'e' or 'g' must be the first extension" "" { target *-*-* } 0 } */ +/* { dg-error "i, e or g must be the first extension" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-28.c b/gcc/testsuite/gcc.target/riscv/arch-28.c index 0f83c03..21c748e 100644 --- a/gcc/testsuite/gcc.target/riscv/arch-28.c +++ b/gcc/testsuite/gcc.target/riscv/arch-28.c @@ -4,4 +4,4 @@ int foo() { } -/* { dg-error "'i', 'e' or 'g' must be the first extension" "" { target *-*-* } 0 } */ +/* { dg-error "i, e or g must be the first extension" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-10.c b/gcc/testsuite/gcc.target/riscv/attribute-10.c index 8a7f0a8..4aaa2bb 100644 --- a/gcc/testsuite/gcc.target/riscv/attribute-10.c +++ b/gcc/testsuite/gcc.target/riscv/attribute-10.c @@ -5,4 +5,4 @@ int foo() } /* { dg-error "extension 'u' is unsupported standard single letter extension" "" { target { "riscv*-*-*" } } 0 } */ /* { dg-error "extension 'n' is unsupported standard single letter extension" "" { target { "riscv*-*-*" } } 0 } */ -/* { dg-error "'i', 'e' or 'g' must be the first extension" "" { target { "riscv*-*-*" } } 0 } */ +/* { dg-error "i, e or g must be the first extension" "" { target { "riscv*-*-*" } } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/big_endian-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/big_endian-2.c index 86cf583..45cc97e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/big_endian-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/big_endian-2.c @@ -2,4 +2,4 @@ /* { dg-options "-march=rv64gc_zve32x -mabi=lp64d -mbig-endian -O3" } */ #pragma riscv intrinsic "vector" -vint32m1_t foo (vint32m1_t) {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC cannot support RVV in big-endian mode" } +vint32m1_t foo (vint32m1_t) {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC does not support RVV in big-endian mode" } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c index 03f6703..1912a24 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c @@ -1,4 +1,4 @@ /* { dg-do compile } */ /* { dg-options "-O3 -march=rv64gcv_zvl8192b -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax" } */ -void foo () {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC can not support VLEN > 4096bit for 'V' Extension" } +void foo () {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC does not support VLEN > 4096bit for 'V' Extension" } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c index 075112f..884e834 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c @@ -1,4 +1,4 @@ /* { dg-do compile } */ /* { dg-options "-O3 -march=rv64gcv_zvl8192b -mabi=lp64d --param riscv-autovec-preference=scalable" } */ -void foo () {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC can not support VLEN > 4096bit for 'V' Extension" } +void foo () {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC does not support VLEN > 4096bit for 'V' Extension" } |