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authorJose E. Marchesi <jose.marchesi@oracle.com>2023-07-14 13:54:06 +0200
committerJose E. Marchesi <jose.marchesi@oracle.com>2023-07-14 14:17:38 +0200
commit53d12ecd624ec901d8449cfa1917f6f90e910927 (patch)
treeef3733d8bfb2cf5b2613167eff63413d5959975b /gcc
parent9206641d0899e4bae3ad6765129661ff3bcc423a (diff)
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bpf: enable instruction scheduling
This patch adds a dummy FSM to bpf.md in order to get INSN_SCHEDULING defined. If the later is not defined, the `combine' pass generates paradoxical subregs of mems, which seems to then be mishandled by LRA, resulting in invalid code. Tested in bpf-unknown-none. gcc/ChangeLog: 2023-07-14 Jose E. Marchesi <jose.marchesi@oracle.com> PR target/110657 * config/bpf/bpf.md: Enable instruction scheduling.
Diffstat (limited to 'gcc')
-rw-r--r--gcc/config/bpf/bpf.md11
1 files changed, 11 insertions, 0 deletions
diff --git a/gcc/config/bpf/bpf.md b/gcc/config/bpf/bpf.md
index f6be0a2..329f62f 100644
--- a/gcc/config/bpf/bpf.md
+++ b/gcc/config/bpf/bpf.md
@@ -20,6 +20,17 @@
(include "predicates.md")
(include "constraints.md")
+;;;; Instruction Scheduler FSM
+
+;; This is just to get INSN_SCHEDULING defined, so that combine does
+;; not make paradoxical subregs of memory. These subregs seems to
+;; confuse LRA that ends generating wrong instructions.
+
+(define_automaton "frob")
+(define_cpu_unit "frob_unit" "frob")
+(define_insn_reservation "frobnicator" 814
+ (const_int 0) "frob_unit")
+
;;;; Unspecs
(define_c_enum "unspec" [