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| author | Eric Botcazou <ebotcazou@libertysurf.fr> | 2004-02-01 16:19:12 +0100 |
|---|---|---|
| committer | Eric Botcazou <ebotcazou@gcc.gnu.org> | 2004-02-01 15:19:12 +0000 |
| commit | 5202c5fea43373ecc71110db9b660358168a6ae4 (patch) | |
| tree | e52b99655362926acd7cd1d41dcde88cbb5e5ca0 /gcc | |
| parent | 38394947aadf94f0c4612719f059632bd0003560 (diff) | |
| download | gcc-5202c5fea43373ecc71110db9b660358168a6ae4.zip gcc-5202c5fea43373ecc71110db9b660358168a6ae4.tar.gz gcc-5202c5fea43373ecc71110db9b660358168a6ae4.tar.bz2 | |
sol2-bi.h: Handle TARGET_CPU_ultrasparc3.
* config/sparc/sol2-bi.h: Handle TARGET_CPU_ultrasparc3.
(CPP_CPU_SPEC): Handle -mcpu=ultrasparc3.
(ASM_CPU_SPEC): Likewise
* config/sparc/sol2.h: Handle TARGET_CPU_ultrasparc3.
(ASM_CPU_SPEC): Remove -mcpu=v8plus. Handle -mcpu=ultrasparc3.
From-SVN: r77074
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/sparc/sol2-bi.h | 17 | ||||
| -rw-r--r-- | gcc/config/sparc/sol2.h | 7 |
3 files changed, 28 insertions, 4 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 432a836..63063ce 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2004-02-01 Eric Botcazou <ebotcazou@libertysurf.fr> + + * config/sparc/sol2-bi.h: Handle TARGET_CPU_ultrasparc3. + (CPP_CPU_SPEC): Handle -mcpu=ultrasparc3. + (ASM_CPU_SPEC): Likewise + * config/sparc/sol2.h: Handle TARGET_CPU_ultrasparc3. + (ASM_CPU_SPEC): Remove -mcpu=v8plus. Handle -mcpu=ultrasparc3. + 2004-02-01 Roger Sayle <roger@eyesopen.com> * builtins.c (expand_builtin_pow): If flag_unsafe_math_optimizations diff --git a/gcc/config/sparc/sol2-bi.h b/gcc/config/sparc/sol2-bi.h index 0a76374..43180c9 100644 --- a/gcc/config/sparc/sol2-bi.h +++ b/gcc/config/sparc/sol2-bi.h @@ -18,6 +18,7 @@ #undef ASM_CPU32_DEFAULT_SPEC #define ASM_CPU32_DEFAULT_SPEC "-xarch=v8plus" #endif + #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc #undef CPP_CPU64_DEFAULT_SPEC #define CPP_CPU64_DEFAULT_SPEC "" @@ -27,6 +28,15 @@ #define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG "a" #endif +#if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 +#undef CPP_CPU64_DEFAULT_SPEC +#define CPP_CPU64_DEFAULT_SPEC "" +#undef ASM_CPU32_DEFAULT_SPEC +#define ASM_CPU32_DEFAULT_SPEC "-xarch=v8plusb" +#undef ASM_CPU64_DEFAULT_SPEC +#define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG "b" +#endif + #if DEFAULT_ARCH32_P #define DEF_ARCH32_SPEC(__str) "%{!m64:" __str "}" #define DEF_ARCH64_SPEC(__str) "%{m64:" __str "}" @@ -45,15 +55,16 @@ %{mcpu=sparclite|mcpu-f930|mcpu=f934:-D__sparclite__} \ %{mcpu=v8:" DEF_ARCH32_SPEC("-D__sparcv8") "} \ %{mcpu=supersparc:-D__supersparc__ " DEF_ARCH32_SPEC("-D__sparcv8") "} \ -%{mcpu=v9|mcpu=ultrasparc:" DEF_ARCH32_SPEC("-D__sparcv8") "} \ +%{mcpu=v9|mcpu=ultrasparc|mcpu=ultrasparc3:" DEF_ARCH32_SPEC("-D__sparcv8") "} \ %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \ " #undef ASM_CPU_SPEC #define ASM_CPU_SPEC "\ -%{mcpu=ultrasparc:" DEF_ARCH32_SPEC("-xarch=v8plusa") DEF_ARCH64_SPEC(AS_SPARC64_FLAG "a") "} \ %{mcpu=v9:" DEF_ARCH32_SPEC("-xarch=v8plus") DEF_ARCH64_SPEC(AS_SPARC64_FLAG) "} \ -%{!mcpu=ultrasparc:%{!mcpu=v9:%{mcpu*:" DEF_ARCH32_SPEC("-xarch=v8") DEF_ARCH64_SPEC(AS_SPARC64_FLAG) "}}} \ +%{mcpu=ultrasparc:" DEF_ARCH32_SPEC("-xarch=v8plusa") DEF_ARCH64_SPEC(AS_SPARC64_FLAG "a") "} \ +%{mcpu=ultrasparc3:" DEF_ARCH32_SPEC("-xarch=v8plusb") DEF_ARCH64_SPEC(AS_SPARC64_FLAG "b") "} \ +%{!mcpu=ultrasparc3:%{!mcpu=ultrasparc:%{!mcpu=v9:%{mcpu*:" DEF_ARCH32_SPEC("-xarch=v8") DEF_ARCH64_SPEC(AS_SPARC64_FLAG) "}}}} \ %{!mcpu*:%(asm_cpu_default)} \ " diff --git a/gcc/config/sparc/sol2.h b/gcc/config/sparc/sol2.h index abc39b5..1138941 100644 --- a/gcc/config/sparc/sol2.h +++ b/gcc/config/sparc/sol2.h @@ -36,11 +36,16 @@ Boston, MA 02111-1307, USA. */ #define ASM_CPU_DEFAULT_SPEC "-xarch=v8plusa" #endif +#if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 +#undef ASM_CPU_DEFAULT_SPEC +#define ASM_CPU_DEFAULT_SPEC "-xarch=v8plusb" +#endif + #undef ASM_CPU_SPEC #define ASM_CPU_SPEC "\ -%{mcpu=v8plus:-xarch=v8plus} \ %{mcpu=v9:-xarch=v8plus} \ %{mcpu=ultrasparc:-xarch=v8plusa} \ +%{mcpu=ultrasparc3:-xarch=v8plusb} \ %{!mcpu*:%(asm_cpu_default)} \ " |