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| author | Jakub Jelinek <jakub@redhat.com> | 2010-08-20 22:54:25 +0200 |
|---|---|---|
| committer | Jakub Jelinek <jakub@gcc.gnu.org> | 2010-08-20 22:54:25 +0200 |
| commit | 50d724a75026efc61783b772dae0f12a823fb720 (patch) | |
| tree | 24bf4e4c7e3829e93a93dc829c6b9c0309b4cc7a /gcc | |
| parent | c6d8116af92b7c733ff5b3180e1ae1a7becbb377 (diff) | |
| download | gcc-50d724a75026efc61783b772dae0f12a823fb720.zip gcc-50d724a75026efc61783b772dae0f12a823fb720.tar.gz gcc-50d724a75026efc61783b772dae0f12a823fb720.tar.bz2 | |
re PR target/45336 (pextr{b,w,d}, (worse than) redundant extensions)
PR target/45336
* config/i386/sse.md (*sse4_1_pextrb): Add SWI48 mode iterator
to cover zero extension into 64-bit register.
(*sse2_pextrw): Likewise.
(*sse4_1_pextrd_zext): New insn.
From-SVN: r163420
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/i386/sse.md | 30 |
2 files changed, 30 insertions, 8 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8b93321..6ccc0a1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2010-08-20 Jakub Jelinek <jakub@redhat.com> + + PR target/45336 + * config/i386/sse.md (*sse4_1_pextrb): Add SWI48 mode iterator + to cover zero extension into 64-bit register. + (*sse2_pextrw): Likewise. + (*sse4_1_pextrd_zext): New insn. + 2010-08-20 Iain Sandoe <iains@gcc.gnu.org> revert r163410, partially revert r163267. diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index b505c8e..3f756d9 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -7075,14 +7075,14 @@ (set_attr "length_immediate" "1") (set_attr "mode" "TI")]) -(define_insn "*sse4_1_pextrb" - [(set (match_operand:SI 0 "register_operand" "=r") - (zero_extend:SI +(define_insn "*sse4_1_pextrb_<mode>" + [(set (match_operand:SWI48 0 "register_operand" "=r") + (zero_extend:SWI48 (vec_select:QI (match_operand:V16QI 1 "register_operand" "x") (parallel [(match_operand:SI 2 "const_0_to_15_operand" "n")]))))] "TARGET_SSE4_1" - "%vpextrb\t{%2, %1, %0|%0, %1, %2}" + "%vpextrb\t{%2, %1, %k0|%k0, %1, %2}" [(set_attr "type" "sselog") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") @@ -7102,14 +7102,14 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "TI")]) -(define_insn "*sse2_pextrw" - [(set (match_operand:SI 0 "register_operand" "=r") - (zero_extend:SI +(define_insn "*sse2_pextrw_<mode>" + [(set (match_operand:SWI48 0 "register_operand" "=r") + (zero_extend:SWI48 (vec_select:HI (match_operand:V8HI 1 "register_operand" "x") (parallel [(match_operand:SI 2 "const_0_to_7_operand" "n")]))))] "TARGET_SSE2" - "%vpextrw\t{%2, %1, %0|%0, %1, %2}" + "%vpextrw\t{%2, %1, %k0|%k0, %1, %2}" [(set_attr "type" "sselog") (set_attr "prefix_data16" "1") (set_attr "length_immediate" "1") @@ -7142,6 +7142,20 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "TI")]) +(define_insn "*sse4_1_pextrd_zext" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (vec_select:SI + (match_operand:V4SI 1 "register_operand" "x") + (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n")]))))] + "TARGET_64BIT && TARGET_SSE4_1" + "%vpextrd\t{%2, %1, %k0|%k0, %1, %2}" + [(set_attr "type" "sselog") + (set_attr "prefix_extra" "1") + (set_attr "length_immediate" "1") + (set_attr "prefix" "maybe_vex") + (set_attr "mode" "TI")]) + ;; It must come before *vec_extractv2di_1_sse since it is preferred. (define_insn "*sse4_1_pextrq" [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") |