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authorJim Wilson <wilson@gcc.gnu.org>1996-06-08 15:38:52 -0700
committerJim Wilson <wilson@gcc.gnu.org>1996-06-08 15:38:52 -0700
commit5034b7bd856d65dff1d8701877e64d3b773c835d (patch)
treebf9e6f634e2a2cacbe7543e6fb8505809a2bddb4 /gcc
parent03b28f881b5eb9bd943fe079e3850c586529eb64 (diff)
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(override_options): Add vr4100 and vr4300 support.
From-SVN: r12248
Diffstat (limited to 'gcc')
-rw-r--r--gcc/config/mips/mips.c23
1 files changed, 23 insertions, 0 deletions
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 42eed3f..783d93c 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -3290,7 +3290,15 @@ override_options ()
else
{
char *p = mips_cpu_string;
+ int seen_v = FALSE;
+ /* We need to cope with the various "vr" prefixes for the NEC 4300
+ and 4100 processors. */
+ if (*p == 'v' || *p == 'V')
+ {
+ seen_v = TRUE;
+ p++;
+ }
if (*p == 'r' || *p == 'R')
p++;
@@ -3313,6 +3321,16 @@ override_options ()
case '4':
if (!strcmp (p, "4000") || !strcmp (p, "4k") || !strcmp (p, "4K"))
mips_cpu = PROCESSOR_R4000;
+ /* The vr4100 is a non-FP ISA III processor with some extra
+ instructions. */
+ else if (!strcmp (p, "4100")) {
+ mips_cpu = PROCESSOR_R4100;
+ target_flags |= MASK_SOFT_FLOAT ;
+ }
+ /* The vr4300 is a standard ISA III processor, but with a different
+ pipeline. */
+ else if (!strcmp (p, "4300"))
+ mips_cpu = PROCESSOR_R4300;
/* The r4400 is exactly the same as the r4000 from the compiler's
viewpoint. */
else if (!strcmp (p, "4400"))
@@ -3339,6 +3357,9 @@ override_options ()
break;
}
+ if (seen_v && mips_cpu != PROCESSOR_R4300 && mips_cpu != PROCESSOR_R4100)
+ mips_cpu = PROCESSOR_DEFAULT;
+
if (mips_cpu == PROCESSOR_DEFAULT)
{
error ("bad value (%s) for -mcpu= switch", mips_cpu_string);
@@ -3349,6 +3370,8 @@ override_options ()
if ((mips_cpu == PROCESSOR_R3000 && mips_isa > 1)
|| (mips_cpu == PROCESSOR_R6000 && mips_isa > 2)
|| ((mips_cpu == PROCESSOR_R4000
+ || mips_cpu == PROCESSOR_R4100
+ || mips_cpu == PROCESSOR_R4300
|| mips_cpu == PROCESSOR_R4600
|| mips_cpu == PROCESSOR_R4650)
&& mips_isa > 3))