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| author | Lehua Ding <lehua.ding@rivai.ai> | 2023-09-21 11:40:07 +0800 |
|---|---|---|
| committer | Lehua Ding <lehua.ding@rivai.ai> | 2023-09-21 11:46:44 +0800 |
| commit | 4e35cf2ea1fbcdf798b37b2e00d9977683b17b8a (patch) | |
| tree | e525e7e23f92bbc83abf8a3487fbaa6894d61fc3 /gcc | |
| parent | 66c13521f56fee1ec6db7ddd9fb053cf852a84a1 (diff) | |
| download | gcc-4e35cf2ea1fbcdf798b37b2e00d9977683b17b8a.zip gcc-4e35cf2ea1fbcdf798b37b2e00d9977683b17b8a.tar.gz gcc-4e35cf2ea1fbcdf798b37b2e00d9977683b17b8a.tar.bz2 | |
RISC-V: Rename predicate vector_gs_scale_operand_16/32 to more generic names
This little rename vector_gs_scale_operand_16/32 to more generic names
const_1_or_2/4_operand. So it's a little better understood when offered
for use elsewhere.
gcc/ChangeLog:
* config/riscv/predicates.md (const_1_or_2_operand): Rename.
(const_1_or_4_operand): Ditto.
(vector_gs_scale_operand_16): Ditto.
(vector_gs_scale_operand_32): Ditto.
* config/riscv/vector-iterators.md: Adjust.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/riscv/predicates.md | 16 | ||||
| -rw-r--r-- | gcc/config/riscv/vector-iterators.md | 16 |
2 files changed, 16 insertions, 16 deletions
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 4bc7ff2..a4f0324 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -70,6 +70,14 @@ (and (match_code "const_int,const_wide_int,const_vector") (match_test "op == CONST1_RTX (GET_MODE (op))"))) +(define_predicate "const_1_or_2_operand" + (and (match_code "const_int") + (match_test "INTVAL (op) == 1 || INTVAL (op) == 2"))) + +(define_predicate "const_1_or_4_operand" + (and (match_code "const_int") + (match_test "INTVAL (op) == 1 || INTVAL (op) == 4"))) + (define_predicate "reg_or_0_operand" (ior (match_operand 0 "const_0_operand") (match_operand 0 "register_operand"))) @@ -463,14 +471,6 @@ (ior (match_operand 0 "register_operand") (match_code "const_vector"))) -(define_predicate "vector_gs_scale_operand_16" - (and (match_code "const_int") - (match_test "INTVAL (op) == 1 || INTVAL (op) == 2"))) - -(define_predicate "vector_gs_scale_operand_32" - (and (match_code "const_int") - (match_test "INTVAL (op) == 1 || INTVAL (op) == 4"))) - (define_predicate "vector_gs_scale_operand_64" (and (match_code "const_int") (match_test "INTVAL (op) == 1 || (INTVAL (op) == 8 && Pmode == DImode)"))) diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 19f3ec3..5c32a63 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -2925,18 +2925,18 @@ (RVVMF4QI "const_1_operand") (RVVMF8QI "const_1_operand") (RVVM8HI "const_1_operand") (RVVM4HI "vector_gs_scale_operand_16_rv32") - (RVVM2HI "vector_gs_scale_operand_16") (RVVM1HI "vector_gs_scale_operand_16") - (RVVMF2HI "vector_gs_scale_operand_16") (RVVMF4HI "vector_gs_scale_operand_16") + (RVVM2HI "const_1_or_2_operand") (RVVM1HI "const_1_or_2_operand") + (RVVMF2HI "const_1_or_2_operand") (RVVMF4HI "const_1_or_2_operand") (RVVM8HF "const_1_operand") (RVVM4HF "vector_gs_scale_operand_16_rv32") - (RVVM2HF "vector_gs_scale_operand_16") (RVVM1HF "vector_gs_scale_operand_16") - (RVVMF2HF "vector_gs_scale_operand_16") (RVVMF4HF "vector_gs_scale_operand_16") + (RVVM2HF "const_1_or_2_operand") (RVVM1HF "const_1_or_2_operand") + (RVVMF2HF "const_1_or_2_operand") (RVVMF4HF "const_1_or_2_operand") - (RVVM8SI "vector_gs_scale_operand_32_rv32") (RVVM4SI "vector_gs_scale_operand_32") (RVVM2SI "vector_gs_scale_operand_32") - (RVVM1SI "vector_gs_scale_operand_32") (RVVMF2SI "vector_gs_scale_operand_32") + (RVVM8SI "vector_gs_scale_operand_32_rv32") (RVVM4SI "const_1_or_4_operand") (RVVM2SI "const_1_or_4_operand") + (RVVM1SI "const_1_or_4_operand") (RVVMF2SI "const_1_or_4_operand") - (RVVM8SF "vector_gs_scale_operand_32_rv32") (RVVM4SF "vector_gs_scale_operand_32") (RVVM2SF "vector_gs_scale_operand_32") - (RVVM1SF "vector_gs_scale_operand_32") (RVVMF2SF "vector_gs_scale_operand_32") + (RVVM8SF "vector_gs_scale_operand_32_rv32") (RVVM4SF "const_1_or_4_operand") (RVVM2SF "const_1_or_4_operand") + (RVVM1SF "const_1_or_4_operand") (RVVMF2SF "const_1_or_4_operand") (RVVM8DI "vector_gs_scale_operand_64") (RVVM4DI "vector_gs_scale_operand_64") (RVVM2DI "vector_gs_scale_operand_64") (RVVM1DI "vector_gs_scale_operand_64") |