re PR target/89093 (C++ exception handling clobbers d8 VFP register)

	PR target/89093
	* config/arm/arm.c (aapcs_vfp_is_call_or_return_candidate): Diagnose
	if used with general-regs-only.
	(arm_conditional_register_usage): Don't add non-general regs if
	general-regs-only.
	(arm_valid_target_attribute_rec): Handle general-regs-only.
	* config/arm/arm.h (TARGET_HARD_FLOAT): Return false if
	general-regs-only.
	(TARGET_HARD_FLOAT_SUB): Define.
	(TARGET_SOFT_FLOAT): Define as negation of TARGET_HARD_FLOAT_SUB.
	(TARGET_REALLY_IWMMXT): Add && !TARGET_GENERAL_REGS_ONLY.
	(TARGET_REALLY_IWMMXT2): Likewise.
	* config/arm/arm.opt: Add -mgeneral-regs-only.
	* doc/extend.texi: Document ARM general-regs-only target.
	* doc/invoke.texi: Document ARM -mgeneral-regs-only.
libgcc/
	* config/arm/pr-support.c: Add #pragma GCC target("general-regs-only").
	* config/arm/unwind-arm.c: Likewise.
	* unwind-c.c (PERSONALITY_FUNCTION): Add general-regs-only target
	attribute for ARM.
libobjc/
	* exception.c (PERSONALITY_FUNCTION): Add general-regs-only target
	attribute for ARM.
libphobos/
	* libdruntime/gcc/deh.d: Import gcc.attribute.
	(personality_fn_attributes): New enum.
	(scanLSDA, CONTINUE_UNWINDING, gdc_personality, __gdc_personality):
	Add @personality_fn_attributes.
libstdc++-v3/
	* libsupc++/eh_personality.cc (PERSONALITY_FUNCTION): Add
	general-regs-only target attribute for ARM.

Co-Authored-By: Bernd Edlinger <bernd.edlinger@hotmail.de>
Co-Authored-By: Jakub Jelinek <jakub@redhat.com>

From-SVN: r270504

6 files changed, 62 insertions, 6 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3d03275..185cf51 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,23 @@
+2019-04-23  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+	    Bernd Edlinger  <bernd.edlinger@hotmail.de>
+	    Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/89093
+	* config/arm/arm.c (aapcs_vfp_is_call_or_return_candidate): Diagnose
+	if used with general-regs-only.
+	(arm_conditional_register_usage): Don't add non-general regs if
+	general-regs-only.
+	(arm_valid_target_attribute_rec): Handle general-regs-only.
+	* config/arm/arm.h (TARGET_HARD_FLOAT): Return false if
+	general-regs-only.
+	(TARGET_HARD_FLOAT_SUB): Define.
+	(TARGET_SOFT_FLOAT): Define as negation of TARGET_HARD_FLOAT_SUB.
+	(TARGET_REALLY_IWMMXT): Add && !TARGET_GENERAL_REGS_ONLY.
+	(TARGET_REALLY_IWMMXT2): Likewise.
+	* config/arm/arm.opt: Add -mgeneral-regs-only.
+	* doc/extend.texi: Document ARM general-regs-only target.
+	* doc/invoke.texi: Document ARM -mgeneral-regs-only.
+
 2019-04-23  Bin Cheng  <bin.cheng@linux.alibaba.com>
 
 	PR tree-optimization/90078
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 731150d..45abcd8 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -6112,6 +6112,11 @@ aapcs_vfp_is_call_or_return_candidate (enum arm_pcs pcs_variant,
     return false;
 
   *base_mode = new_mode;
+
+  if (TARGET_GENERAL_REGS_ONLY)
+    error ("argument of type %qT not permitted with -mgeneral-regs-only",
+	   type);
+
   return true;
 }
 
@@ -28404,7 +28409,7 @@ arm_conditional_register_usage (void)
 	}
     }
 
-  if (TARGET_REALLY_IWMMXT)
+  if (TARGET_REALLY_IWMMXT && !TARGET_GENERAL_REGS_ONLY)
     {
       regno = FIRST_IWMMXT_GR_REGNUM;
       /* The 2002/10/09 revision of the XScale ABI has wCG0
@@ -30878,6 +30883,9 @@ arm_valid_target_attribute_rec (tree args, struct gcc_options *opts)
       else if (!strcmp (q, "arm"))
 	opts->x_target_flags &= ~MASK_THUMB;
 
+      else if (!strcmp (q, "general-regs-only"))
+	opts->x_target_flags |= MASK_GENERAL_REGS_ONLY;
+
       else if (!strncmp (q, "fpu=", 4))
 	{
 	  int fpu_index;
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 7adafea..4866e1e 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -122,12 +122,18 @@ extern tree arm_fp16_type_node;
 #define TARGET_32BIT_P(flags)  (TARGET_ARM_P (flags) || TARGET_THUMB2_P (flags))
 
 /* Run-time Target Specification.  */
-/* Use hardware floating point instructions. */
-#define TARGET_HARD_FLOAT	(arm_float_abi != ARM_FLOAT_ABI_SOFT	\
+/* Use hardware floating point instructions. -mgeneral-regs-only prevents
+the use of floating point instructions and registers but does not prevent
+emission of floating point pcs attributes.  */
+#define TARGET_HARD_FLOAT_SUB	(arm_float_abi != ARM_FLOAT_ABI_SOFT	\
 				 && bitmap_bit_p (arm_active_target.isa, \
 						  isa_bit_vfpv2) \
 				 && TARGET_32BIT)
-#define TARGET_SOFT_FLOAT	(!TARGET_HARD_FLOAT)
+
+#define TARGET_HARD_FLOAT	(TARGET_HARD_FLOAT_SUB		\
+				 && !TARGET_GENERAL_REGS_ONLY)
+
+#define TARGET_SOFT_FLOAT	(!TARGET_HARD_FLOAT_SUB)
 /* User has permitted use of FP instructions, if they exist for this
    target.  */
 #define TARGET_MAYBE_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
@@ -135,8 +141,10 @@ extern tree arm_fp16_type_node;
 #define TARGET_HARD_FLOAT_ABI		(arm_float_abi == ARM_FLOAT_ABI_HARD)
 #define TARGET_IWMMXT			(arm_arch_iwmmxt)
 #define TARGET_IWMMXT2			(arm_arch_iwmmxt2)
-#define TARGET_REALLY_IWMMXT		(TARGET_IWMMXT && TARGET_32BIT)
-#define TARGET_REALLY_IWMMXT2		(TARGET_IWMMXT2 && TARGET_32BIT)
+#define TARGET_REALLY_IWMMXT		(TARGET_IWMMXT && TARGET_32BIT \
+					 && !TARGET_GENERAL_REGS_ONLY)
+#define TARGET_REALLY_IWMMXT2		(TARGET_IWMMXT2 && TARGET_32BIT \
+					 && !TARGET_GENERAL_REGS_ONLY)
 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT)
 #define TARGET_ARM                      (! TARGET_THUMB)
 #define TARGET_EITHER			1 /* (TARGET_ARM | TARGET_THUMB) */
diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt
index 94c6875..9067d49 100644
--- a/gcc/config/arm/arm.opt
+++ b/gcc/config/arm/arm.opt
@@ -302,3 +302,7 @@ When linking for big-endian targets, generate a legacy BE32 format image.
 mbranch-cost=
 Target RejectNegative Joined UInteger Var(arm_branch_cost) Init(-1)
 Cost to assume for a branch insn.
+
+mgeneral-regs-only
+Target Report RejectNegative Mask(GENERAL_REGS_ONLY) Save
+Generate code which uses the core registers only (r0-r14).
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 0bb1fd2..91679e8 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -4190,6 +4190,15 @@ into the @code{sjli} table needs to be passed as argument.
 These function attributes are supported for ARM targets:
 
 @table @code
+
+@item general-regs-only
+@cindex @code{general-regs-only} function attribute, ARM
+Indicates that no floating-point or Advanced SIMD registers should be
+used when generating code for this function.  If the function explicitly
+uses floating-point code, then the compiler gives an error.  This is
+the same behavior as that of the command-line option
+@option{-mgeneral-regs-only}.
+
 @item interrupt
 @cindex @code{interrupt} function attribute, ARM
 Use this attribute to indicate
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index f4aa9e5..29585cf 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -674,6 +674,7 @@ Objective-C and Objective-C++ Dialects}.
 -mabi=@var{name} @gol
 -mapcs-stack-check  -mno-apcs-stack-check @gol
 -mapcs-reentrant  -mno-apcs-reentrant @gol
+-mgeneral-regs-only @gol
 -msched-prolog  -mno-sched-prolog @gol
 -mlittle-endian  -mbig-endian @gol
 -mbe8  -mbe32 @gol
@@ -17068,6 +17069,12 @@ the hard-float and soft-float ABIs are not link-compatible; you must
 compile your entire program with the same ABI, and link with a
 compatible set of libraries.
 
+@item -mgeneral-regs-only
+@opindex mgeneral-regs-only
+Generate code which uses only the general-purpose registers.  This will prevent
+the compiler from using floating-point and Advanced SIMD registers but will not
+impose any restrictions on the assembler.
+
 @item -mlittle-endian
 @opindex mlittle-endian
 Generate code for a processor running in little-endian mode.  This is