diff options
| author | Jim Wilson <wilson@gcc.gnu.org> | 1994-07-02 19:22:00 -0700 |
|---|---|---|
| committer | Jim Wilson <wilson@gcc.gnu.org> | 1994-07-02 19:22:00 -0700 |
| commit | 48199e329d33db8612cc9482e923ac98d298e7ab (patch) | |
| tree | 27c0c6a9627c5776ead5a687663cd8e72925bd4d /gcc | |
| parent | f0c94be0eb12ba81c9c2c893ba6d85a8bd28267f (diff) | |
| download | gcc-48199e329d33db8612cc9482e923ac98d298e7ab.zip gcc-48199e329d33db8612cc9482e923ac98d298e7ab.tar.gz gcc-48199e329d33db8612cc9482e923ac98d298e7ab.tar.bz2 | |
(smuldi3_highpart, smuldi3_highpart_internal,
umuldi3_highpart, umuldi3_highpart_internal): New patterns.
From-SVN: r7649
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/mips/mips.md | 112 |
1 files changed, 112 insertions, 0 deletions
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index a89d114..98151db 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -1069,6 +1069,118 @@ [(set_attr "type" "imul") (set_attr "mode" "SI") (set_attr "length" "1")]) + +(define_insn "smuldi3_highpart" + [(set (match_operand:DI 0 "register_operand" "=d") + (truncate:DI + (lshiftrt:TI (mult:TI (sign_extend:TI (match_operand:DI 1 "register_operand" "d")) + (sign_extend:TI (match_operand:DI 2 "register_operand" "d"))) + (const_int 64)))) + (clobber (reg:DI 64)) + (clobber (reg:DI 65))] + "TARGET_64BIT" + "* +{ + rtx xoperands[10]; + + xoperands[0] = operands[0]; + xoperands[1] = gen_rtx (REG, DImode, HI_REGNUM); + + output_asm_insn (\"dmult\\t%1,%2\", operands); + output_asm_insn (mips_move_1word (xoperands, insn, TRUE), xoperands); + return \"\"; +}" + [(set_attr "type" "imul") + (set_attr "mode" "DI") + (set_attr "length" "3")]) ;; mult + mfhi + delay + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (truncate:DI + (lshiftrt:TI (mult:TI (sign_extend:TI (match_operand:DI 1 "register_operand" "d")) + (sign_extend:TI (match_operand:DI 2 "register_operand" "d"))) + (const_int 64)))) + (clobber (reg:DI 64)) + (clobber (reg:DI 65))] + "TARGET_64BIT && !TARGET_DEBUG_D_MODE" + [(parallel [(set (reg:DI 64) ;; high register + (truncate:DI + (lshiftrt:TI (mult:TI (sign_extend:TI (match_dup 1)) + (sign_extend:TI (match_dup 2))) + (const_int 64)))) + (clobber (reg:DI 65))]) + (set (match_dup 0) + (reg:DI 64))] + "") + +(define_insn "smuldi3_highpart_internal" + [(set (reg:DI 64) ;; high register + (truncate:DI + (lshiftrt:TI (mult:TI (sign_extend:TI (match_operand:DI 0 "register_operand" "d")) + (sign_extend:TI (match_operand:DI 1 "register_operand" "d"))) + (const_int 64)))) + (clobber (reg:DI 65))] + "TARGET_64BIT" + "dmult\\t%0,%1" + [(set_attr "type" "imul") + (set_attr "mode" "DI") + (set_attr "length" "1")]) + +(define_insn "umuldi3_highpart" + [(set (match_operand:DI 0 "register_operand" "=d") + (truncate:DI + (lshiftrt:TI (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "d")) + (zero_extend:TI (match_operand:DI 2 "register_operand" "d"))) + (const_int 64)))) + (clobber (reg:DI 64)) + (clobber (reg:DI 65))] + "TARGET_64BIT" + "* +{ + rtx xoperands[10]; + + xoperands[0] = operands[0]; + xoperands[1] = gen_rtx (REG, DImode, HI_REGNUM); + + output_asm_insn (\"dmultu\\t%1,%2\", operands); + output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands); + return \"\"; +}" + [(set_attr "type" "imul") + (set_attr "mode" "DI") + (set_attr "length" "3")]) ;; multu + mfhi + delay + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (truncate:DI + (lshiftrt:TI (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "d")) + (zero_extend:TI (match_operand:DI 2 "register_operand" "d"))) + (const_int 64)))) + (clobber (reg:DI 64)) + (clobber (reg:DI 65))] + "TARGET_64BIT && !TARGET_DEBUG_D_MODE" + [(parallel [(set (reg:DI 64) ;; high register + (truncate:DI + (lshiftrt:TI (mult:TI (zero_extend:TI (match_dup 1)) + (zero_extend:TI (match_dup 2))) + (const_int 64)))) + (clobber (reg:DI 65))]) + (set (match_dup 0) + (reg:DI 64))] + "") + +(define_insn "umuldi3_highpart_internal" + [(set (reg:DI 64) ;; high register + (truncate:DI + (lshiftrt:TI (mult:TI (zero_extend:TI (match_operand:DI 0 "register_operand" "d")) + (zero_extend:TI (match_operand:DI 1 "register_operand" "d"))) + (const_int 64)))) + (clobber (reg:DI 65))] + "TARGET_64BIT" + "dmultu\\t%0,%1" + [(set_attr "type" "imul") + (set_attr "mode" "DI") + (set_attr "length" "1")]) ;; ;; .................... |